// Created by IP Generator (Version 2020.3 build 62942)
// Instantiation Template
//
// Insert the following codes into your Verilog file.
//   * Change the_instance_name to your own instance name.
//   * Change the signal names in the port associations


video_pll the_instance_name (
  .pll_rst(pll_rst),      // input
  .clkin1(clkin1),        // input
  .pll_lock(pll_lock),    // output
  .clkout0(clkout0),      // output
  .clkout1(clkout1)       // output
);
