IP Generator (Version 2020.3 build 62942)
Check out license ...
Start generating at 2022-04-23 22:54
Instance: FIFO2_56x32 (D:\FPGA_CODE\Other_work\fruit\Test\Test_fifo\ipcore\FIFO2_56x32\FIFO2_56x32.idf)
Model: Logos DRM Based FIFO (1.5)
Part: Logos-PGL22G-MBG324--6
Create directory 'rtl' ...
Copy 'rtl\ipml_fifo_ctrl_v1_3.v' to 'rtl' ...
Copy 'rtl\ipml_fifo_v1_5.v.xml' to 'rtl' ...
Copy 'rtl\ipml_prefetch_fifo_v1_5.v.xml' to 'rtl' ...
Copy 'rtl\ipml_reg_fifo_v1_0.v' to 'rtl' ...
Copy 'rtl\ipml_sdpram_v1_5.v.xml' to 'rtl' ...
Compile file 'rtl\ipml_sdpram_v1_5.v.xml' to 'rtl\ipml_sdpram_v1_5_FIFO2_56x32.v' ...
Compile file 'rtl\ipml_fifo_v1_5.v.xml' to 'rtl\ipml_fifo_v1_5_FIFO2_56x32.v' ...
Compile file 'rtl\ipml_prefetch_fifo_v1_5.v.xml' to 'rtl\ipml_prefetch_fifo_v1_5_FIFO2_56x32.v' ...
Copy 'ipml_fifo_wrapper_v1_5.v.xml' ...
Compile file 'ipml_fifo_wrapper_v1_5.v.xml' to 'FIFO2_56x32.v' ...
Found top module 'FIFO2_56x32' in file 'FIFO2_56x32.v'.
Copy 'ipml_prefetch_fifo_wrapper_v1_5.v.xml' ...
Compile file 'ipml_prefetch_fifo_wrapper_v1_5.v.xml' to 'FIFO2_56x32_prefetch.v' ...
Copy 'ipml_fifo_wrapper_v1_3_tb.v.xml' ...
Compile file 'ipml_fifo_wrapper_v1_3_tb.v.xml' to 'FIFO2_56x32_tb.v' ...
Create template file 'FIFO2_56x32_tmpl.v' ...
Create template file 'FIFO2_56x32_tmpl.vhdl' ...
There are 4 source files to synthesize.
Synthesis is disabled.
Done: 0 error(s), 0 warning(s)
