i u_ipsl_hmemc_top.u_pll_50_400.clkout3_i
m 0 0
u 80 549
n ckid0_0 {t:u_aq_axi_master.rd_state[5].C} Black box on clock path
p {t:u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1.CLKOUT3}{t:u_ipsl_hmemc_top.u_pll_50_400.clkout3_inferred_clock.I[0]}{t:u_ipsl_hmemc_top.u_pll_50_400.clkout3_inferred_clock.OUT[0]}{p:u_ipsl_hmemc_top.u_pll_50_400.clkout3}{t:u_ipsl_hmemc_top.u_pll_50_400.clkout3}{p:u_ipsl_hmemc_top.pll_aclk_1}{t:u_ipsl_hmemc_top.pll_aclk_1}{t:u_aq_axi_master.ACLK}{p:u_aq_axi_master.ACLK}{t:u_aq_axi_master.rd_state[5].C}
e ckid0_0 {t:u_aq_axi_master.rd_state[5].C} dffr
d ckid0_0 {t:u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1.CLKOUT3} GTP_PLL_E1 Black box on clock path
i u_ipsl_hmemc_top.u_pll_50_400.clkout1_i
m 0 0
u 70 148
n ckid0_1 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[6:0].C} Black box on clock path
p {t:u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1.CLKOUT1}{t:u_ipsl_hmemc_top.u_pll_50_400.clkout1_inferred_clock.I[0]}{t:u_ipsl_hmemc_top.u_pll_50_400.clkout1_inferred_clock.OUT[0]}{p:u_ipsl_hmemc_top.u_pll_50_400.clkout1}{t:u_ipsl_hmemc_top.u_pll_50_400.clkout1}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.pclk}{p:u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.pclk}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc.PCLK}
e ckid0_2 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc.PCLK} GTP_DDRC
d ckid0_1,ckid0_2 {t:u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1.CLKOUT1} GTP_PLL_E1 Black box on clock path
i u_ipsl_hmemc_top.aclk_0
m 0 0
u 1 1
n ckid0_3 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc.ACLK_0} Black box on clock path
p {t:u_ipsl_hmemc_top.aclk_0.O[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.aclk_0}{p:u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.aclk_0}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc.ACLK_0}
e ckid0_3 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc.ACLK_0} GTP_DDRC
d ckid0_3 {t:u_ipsl_hmemc_top.aclk_0.O[0]} variable Clock source is constant
i u_ipsl_hmemc_top.aclk_2
m 0 0
u 1 1
n ckid0_4 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc.ACLK_2} Black box on clock path
p {t:u_ipsl_hmemc_top.aclk_2.O[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.aclk_2}{p:u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.aclk_2}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc.ACLK_2}
e ckid0_4 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc.ACLK_2} GTP_DDRC
d ckid0_4 {t:u_ipsl_hmemc_top.aclk_2.O[0]} variable Clock source is constant
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.IOCLK_DIV_i
m 0 0
u 2 2
n ckid0_5 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc.CORE_DDRC_CORE_CLK} Black box on clock path
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclkdiv_dut.CLKDIVOUT}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.IOCLK_DIV_inferred_clock.I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.IOCLK_DIV_inferred_clock.OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DDRPHY_CLKIN}
e ckid0_6 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DDRPHY_CLKIN} GTP_DDRPHY
d ckid0_5,ckid0_6 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclkdiv_dut.CLKDIVOUT} GTP_IOCLKDIV Black box on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw_ca_04_i
m 0 0
u 5 5
n ckid0_7 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut.OCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut.WCLK}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw_ca_04_inferred_clock.I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw_ca_04_inferred_clock.OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut.OCLK}
e ckid0_7 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut.OCLK} GTP_OSERDES
d ckid0_8 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut.WCLK} GTP_DDC_E1 Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[59]
m 0 0
u 1 1
n ckid0_9 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[59]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[59].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[59].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut.RCLK}
e ckid0_9 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut.RCLK} GTP_OSERDES
d ckid0_10 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[59]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_ca_clk_r_04_i
m 0 0
u 5 5
n ckid0_11 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut.SERCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut.RCLK}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_ca_clk_r_04_inferred_clock.I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_ca_clk_r_04_inferred_clock.OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut.SERCLK}
e ckid0_11 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut.SERCLK} GTP_OSERDES
d ckid0_12 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut.RCLK} GTP_DDC_E1 Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[58]
m 0 0
u 1 1
n ckid0_13 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr58_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[58]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[58].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[58].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr58_dut.RCLK}
e ckid0_13 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr58_dut.RCLK} GTP_OSERDES
d ckid0_14 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[58]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[57]
m 0 0
u 1 1
n ckid0_15 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr57_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[57]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[57].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[57].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr57_dut.RCLK}
e ckid0_15 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr57_dut.RCLK} GTP_OSERDES
d ckid0_16 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[57]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[56]
m 0 0
u 1 1
n ckid0_17 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr56_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[56]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[56].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[56].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr56_dut.RCLK}
e ckid0_17 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr56_dut.RCLK} GTP_OSERDES
d ckid0_18 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[56]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[55]
m 0 0
u 1 1
n ckid0_19 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr55_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[55]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[55].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[55].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr55_dut.RCLK}
e ckid0_19 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr55_dut.RCLK} GTP_OSERDES
d ckid0_20 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[55]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw_ca_03_i
m 0 0
u 12 12
n ckid0_21 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut.OCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut.WCLK}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw_ca_03_inferred_clock.I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw_ca_03_inferred_clock.OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut.OCLK}
e ckid0_21 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut.OCLK} GTP_OSERDES
d ckid0_22 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut.WCLK} GTP_DDC_E1 Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[52]
m 0 0
u 1 1
n ckid0_23 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[52]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[52].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[52].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut.RCLK}
e ckid0_23 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut.RCLK} GTP_OSERDES
d ckid0_24 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[52]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_ca_clk_r_03_i
m 0 0
u 12 12
n ckid0_25 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut.SERCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut.RCLK}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_ca_clk_r_03_inferred_clock.I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_ca_clk_r_03_inferred_clock.OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut.SERCLK}
e ckid0_25 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut.SERCLK} GTP_OSERDES
d ckid0_26 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut.RCLK} GTP_DDC_E1 Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[51]
m 0 0
u 1 1
n ckid0_27 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr51_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[51]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[51].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[51].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr51_dut.RCLK}
e ckid0_27 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr51_dut.RCLK} GTP_OSERDES
d ckid0_28 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[51]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[49]
m 0 0
u 1 1
n ckid0_29 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr49_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[49]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[49].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[49].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr49_dut.RCLK}
e ckid0_29 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr49_dut.RCLK} GTP_OSERDES
d ckid0_30 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[49]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[48]
m 0 0
u 1 1
n ckid0_31 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr48_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[48]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[48].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[48].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr48_dut.RCLK}
e ckid0_31 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr48_dut.RCLK} GTP_OSERDES
d ckid0_32 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[48]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[47]
m 0 0
u 1 1
n ckid0_33 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr47_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[47]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[47].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[47].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr47_dut.RCLK}
e ckid0_33 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr47_dut.RCLK} GTP_OSERDES
d ckid0_34 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[47]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[46]
m 0 0
u 1 1
n ckid0_35 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr46_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[46]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[46].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[46].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr46_dut.RCLK}
e ckid0_35 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr46_dut.RCLK} GTP_OSERDES
d ckid0_36 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[46]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[45]
m 0 0
u 1 1
n ckid0_37 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr45_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[45]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[45].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[45].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr45_dut.RCLK}
e ckid0_37 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr45_dut.RCLK} GTP_OSERDES
d ckid0_38 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[45]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[44]
m 0 0
u 1 1
n ckid0_39 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr44_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[44]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[44].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[44].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr44_dut.RCLK}
e ckid0_39 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr44_dut.RCLK} GTP_OSERDES
d ckid0_40 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[44]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[43]
m 0 0
u 1 1
n ckid0_41 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr43_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[43]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[43].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[43].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr43_dut.RCLK}
e ckid0_41 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr43_dut.RCLK} GTP_OSERDES
d ckid0_42 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[43]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[42]
m 0 0
u 1 1
n ckid0_43 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr42_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[42]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[42].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[42].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr42_dut.RCLK}
e ckid0_43 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr42_dut.RCLK} GTP_OSERDES
d ckid0_44 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[42]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[41]
m 0 0
u 1 1
n ckid0_45 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr41_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[41]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[41].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[41].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr41_dut.RCLK}
e ckid0_45 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr41_dut.RCLK} GTP_OSERDES
d ckid0_46 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[41]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[40]
m 0 0
u 1 1
n ckid0_47 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr40_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[40]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[40].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[40].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr40_dut.RCLK}
e ckid0_47 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr40_dut.RCLK} GTP_OSERDES
d ckid0_48 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[40]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw290_1_i
m 0 0
u 9 9
n ckid0_49 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut.OCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.WCLK_DELAY}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw290_1_inferred_clock.I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw290_1_inferred_clock.OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut.OCLK}
e ckid0_49 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut.OCLK} GTP_OSERDES
d ckid0_50 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.WCLK_DELAY} GTP_DDC_E1 Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[37]
m 0 0
u 1 1
n ckid0_51 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[37]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[37].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[37].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut.RCLK}
e ckid0_51 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut.RCLK} GTP_OSERDES
d ckid0_52 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[37]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_clk_r_i
m 0 0
u 10 10
n ckid0_53 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut.SERCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.RCLK}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_clk_r_inferred_clock.I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_clk_r_inferred_clock.OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut.SERCLK}
e ckid0_53 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut.SERCLK} GTP_OSERDES
d ckid0_54 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.RCLK} GTP_DDC_E1 Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[36]
m 0 0
u 2 2
n ckid0_55 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr36_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[36]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[36].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[36].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr36_dut.RCLK}
e ckid0_55 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr36_dut.RCLK} GTP_OSERDES
d ckid0_56 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[36]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclk_01_i
m 0 0
u 19 19
n ckid0_57 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr36_dut.DESCLK} Black box on clock path
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclkbuf01_dut.CLKOUT}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclk_01_inferred_clock.I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclk_01_inferred_clock.OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr36_dut.DESCLK}
e ckid0_57 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr36_dut.DESCLK} GTP_ISERDES
d ckid0_57 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclkbuf01_dut.CLKOUT} GTP_IOCLKBUF Black box on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_90_1_i
m 0 0
u 8 8
n ckid0_58 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr36_dut.ICLK} Black box on clock path
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.DQSI_DELAY}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_90_1_inferred_clock.I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_90_1_inferred_clock.OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr36_dut.ICLK}
e ckid0_58 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr36_dut.ICLK} GTP_ISERDES
d ckid0_59 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.DQSI_DELAY} GTP_DDC_E1 Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[35]
m 0 0
u 2 2
n ckid0_60 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr35_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[35]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[35].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[35].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr35_dut.RCLK}
e ckid0_60 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr35_dut.RCLK} GTP_OSERDES
d ckid0_61 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[35]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[34]
m 0 0
u 2 2
n ckid0_62 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr34_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[34]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[34].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[34].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr34_dut.RCLK}
e ckid0_62 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr34_dut.RCLK} GTP_OSERDES
d ckid0_63 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[34]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[33]
m 0 0
u 2 2
n ckid0_64 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr33_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[33]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[33].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[33].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr33_dut.RCLK}
e ckid0_64 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr33_dut.RCLK} GTP_OSERDES
d ckid0_65 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[33]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[32]
m 0 0
u 2 2
n ckid0_66 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr32_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[32]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[32].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[32].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr32_dut.RCLK}
e ckid0_66 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr32_dut.RCLK} GTP_OSERDES
d ckid0_67 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[32]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw_1_i
m 0 0
u 1 1
n ckid0_68 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr31_dut.OCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.WCLK}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw_1_inferred_clock.I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw_1_inferred_clock.OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr31_dut.OCLK}
e ckid0_68 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr31_dut.OCLK} GTP_OSERDES
d ckid0_69 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.WCLK} GTP_DDC_E1 Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[31]
m 0 0
u 1 1
n ckid0_70 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr31_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[31]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[31].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[31].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr31_dut.RCLK}
e ckid0_70 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr31_dut.RCLK} GTP_OSERDES
d ckid0_71 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[31]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[29]
m 0 0
u 2 2
n ckid0_72 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr29_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[29]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[29].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[29].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr29_dut.RCLK}
e ckid0_72 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr29_dut.RCLK} GTP_OSERDES
d ckid0_73 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[29]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[28]
m 0 0
u 2 2
n ckid0_74 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr28_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[28]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[28].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[28].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr28_dut.RCLK}
e ckid0_74 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr28_dut.RCLK} GTP_OSERDES
d ckid0_75 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[28]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[27]
m 0 0
u 2 2
n ckid0_76 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr27_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[27]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[27].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[27].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr27_dut.RCLK}
e ckid0_76 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr27_dut.RCLK} GTP_OSERDES
d ckid0_77 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[27]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw_ca_01_i
m 0 0
u 9 9
n ckid0_78 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut.OCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut.WCLK}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw_ca_01_inferred_clock.I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw_ca_01_inferred_clock.OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut.OCLK}
e ckid0_78 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut.OCLK} GTP_OSERDES
d ckid0_79 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut.WCLK} GTP_DDC_E1 Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[25]
m 0 0
u 1 1
n ckid0_80 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[25]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[25].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[25].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut.RCLK}
e ckid0_80 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut.RCLK} GTP_OSERDES
d ckid0_81 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[25]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_ca_clk_r_01_i
m 0 0
u 9 9
n ckid0_82 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut.SERCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut.RCLK}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_ca_clk_r_01_inferred_clock.I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_ca_clk_r_01_inferred_clock.OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut.SERCLK}
e ckid0_82 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut.SERCLK} GTP_OSERDES
d ckid0_83 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut.RCLK} GTP_DDC_E1 Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[24]
m 0 0
u 1 1
n ckid0_84 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr24_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[24]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[24].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[24].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr24_dut.RCLK}
e ckid0_84 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr24_dut.RCLK} GTP_OSERDES
d ckid0_85 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[24]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[23]
m 0 0
u 1 1
n ckid0_86 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr23_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[23]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[23].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[23].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr23_dut.RCLK}
e ckid0_86 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr23_dut.RCLK} GTP_OSERDES
d ckid0_87 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[23]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[22]
m 0 0
u 1 1
n ckid0_88 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr22_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[22]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[22].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[22].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr22_dut.RCLK}
e ckid0_88 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr22_dut.RCLK} GTP_OSERDES
d ckid0_89 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[22]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[21]
m 0 0
u 1 1
n ckid0_90 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr21_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[21]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[21].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[21].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr21_dut.RCLK}
e ckid0_90 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr21_dut.RCLK} GTP_OSERDES
d ckid0_91 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[21]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[20]
m 0 0
u 1 1
n ckid0_92 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr20_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[20]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[20].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[20].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr20_dut.RCLK}
e ckid0_92 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr20_dut.RCLK} GTP_OSERDES
d ckid0_93 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[20]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[19]
m 0 0
u 1 1
n ckid0_94 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr19_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[19]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[19].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[19].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr19_dut.RCLK}
e ckid0_94 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr19_dut.RCLK} GTP_OSERDES
d ckid0_95 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[19]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[18]
m 0 0
u 1 1
n ckid0_96 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr18_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[18]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[18].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[18].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr18_dut.RCLK}
e ckid0_96 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr18_dut.RCLK} GTP_OSERDES
d ckid0_97 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[18]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[17]
m 0 0
u 1 1
n ckid0_98 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr17_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[17]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[17].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[17].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr17_dut.RCLK}
e ckid0_98 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr17_dut.RCLK} GTP_OSERDES
d ckid0_99 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[17]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw290_0_i
m 0 0
u 9 9
n ckid0_100 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr12_dut.OCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.WCLK_DELAY}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw290_0_inferred_clock.I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw290_0_inferred_clock.OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr12_dut.OCLK}
e ckid0_100 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr12_dut.OCLK} GTP_OSERDES
d ckid0_101 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.WCLK_DELAY} GTP_DDC_E1 Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[12]
m 0 0
u 2 2
n ckid0_102 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr12_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[12]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[12].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[12].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr12_dut.RCLK}
e ckid0_102 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr12_dut.RCLK} GTP_OSERDES
d ckid0_103 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[12]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_clk_r_i
m 0 0
u 10 10
n ckid0_104 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr12_dut.SERCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.RCLK}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_clk_r_inferred_clock.I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_clk_r_inferred_clock.OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr12_dut.SERCLK}
e ckid0_104 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr12_dut.SERCLK} GTP_OSERDES
d ckid0_105 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.RCLK} GTP_DDC_E1 Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_90_0_i
m 0 0
u 8 8
n ckid0_106 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr12_dut.ICLK} Black box on clock path
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.DQSI_DELAY}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_90_0_inferred_clock.I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_90_0_inferred_clock.OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr12_dut.ICLK}
e ckid0_106 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr12_dut.ICLK} GTP_ISERDES
d ckid0_107 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.DQSI_DELAY} GTP_DDC_E1 Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[11]
m 0 0
u 2 2
n ckid0_108 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr11_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[11]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[11].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[11].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr11_dut.RCLK}
e ckid0_108 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr11_dut.RCLK} GTP_OSERDES
d ckid0_109 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[11]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[10]
m 0 0
u 2 2
n ckid0_110 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr10_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[10]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[10].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[10].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr10_dut.RCLK}
e ckid0_110 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr10_dut.RCLK} GTP_OSERDES
d ckid0_111 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[10]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw_0_i
m 0 0
u 1 1
n ckid0_112 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr9_dut.OCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.WCLK}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw_0_inferred_clock.I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw_0_inferred_clock.OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr9_dut.OCLK}
e ckid0_112 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr9_dut.OCLK} GTP_OSERDES
d ckid0_113 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.WCLK} GTP_DDC_E1 Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[9]
m 0 0
u 1 1
n ckid0_114 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr9_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[9]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[9].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[9].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr9_dut.RCLK}
e ckid0_114 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr9_dut.RCLK} GTP_OSERDES
d ckid0_115 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[9]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[7]
m 0 0
u 2 2
n ckid0_116 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr7_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[7]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[7].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[7].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr7_dut.RCLK}
e ckid0_116 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr7_dut.RCLK} GTP_OSERDES
d ckid0_117 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[7]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[6]
m 0 0
u 2 2
n ckid0_118 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr6_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[6]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[6].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[6].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr6_dut.RCLK}
e ckid0_118 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr6_dut.RCLK} GTP_OSERDES
d ckid0_119 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[6]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[5]
m 0 0
u 2 2
n ckid0_120 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr5_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[5]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[5].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[5].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr5_dut.RCLK}
e ckid0_120 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr5_dut.RCLK} GTP_OSERDES
d ckid0_121 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[5]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[4]
m 0 0
u 2 2
n ckid0_122 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr4_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[4]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[4].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[4].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr4_dut.RCLK}
e ckid0_122 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr4_dut.RCLK} GTP_OSERDES
d ckid0_123 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[4]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[3]
m 0 0
u 2 2
n ckid0_124 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr3_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[3]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[3].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[3].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr3_dut.RCLK}
e ckid0_124 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr3_dut.RCLK} GTP_OSERDES
d ckid0_125 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[3]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_i[2]
m 0 0
u 1 1
n ckid0_126 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr2_dut.RCLK} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[2]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[2].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys_inferred_clock[2].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr2_dut.RCLK}
e ckid0_126 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr2_dut.RCLK} GTP_OSERDES
d ckid0_127 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[2]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclk_02_i
m 0 0
u 2 2
n ckid0_128 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut.CLKA} Black box on clock path
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclkbuf02_dut.CLKOUT}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclk_02_inferred_clock.I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclk_02_inferred_clock.OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut.CLKA}
e ckid0_128 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut.CLKA} GTP_DDC_E1
d ckid0_128 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclkbuf02_dut.CLKOUT} GTP_IOCLKBUF Black box on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_dqs_clk_regional_i[4]
m 0 0
u 1 1
n ckid0_129 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut.CLKB} Black box on clock path
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[4]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_dqs_clk_regional_inferred_clock[4].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_dqs_clk_regional_inferred_clock[4].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut.CLKB}
e ckid0_129 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut.CLKB} GTP_DDC_E1
d ckid0_130 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[4]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_dqs_clk_regional_i[3]
m 0 0
u 1 1
n ckid0_131 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut.CLKB} Black box on clock path
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[3]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_dqs_clk_regional_inferred_clock[3].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_dqs_clk_regional_inferred_clock[3].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut.CLKB}
e ckid0_131 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut.CLKB} GTP_DDC_E1
d ckid0_132 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[3]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_dqs_clk_regional_i[2]
m 0 0
u 1 1
n ckid0_133 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.CLKB} Black box on clock path
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[2]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_dqs_clk_regional_inferred_clock[2].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_dqs_clk_regional_inferred_clock[2].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.CLKB}
e ckid0_133 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.CLKB} GTP_DDC_E1
d ckid0_134 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[2]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_dqs_clk_regional_i[1]
m 0 0
u 1 1
n ckid0_135 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut.CLKB} Black box on clock path
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[1]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_dqs_clk_regional_inferred_clock[1].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_dqs_clk_regional_inferred_clock[1].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut.CLKB}
e ckid0_135 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut.CLKB} GTP_DDC_E1
d ckid0_136 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[1]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_dqs_clk_regional_i[0]
m 0 0
u 1 1
n ckid0_137 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.CLKB} Black box on clock path
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_dqs_clk_regional_inferred_clock[0].I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_dqs_clk_regional_inferred_clock[0].OUT[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.CLKB}
e ckid0_137 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.CLKB} GTP_DDC_E1
d ckid0_138 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[0]} GTP_DDRPHY Unsupported/too complex instance on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_dll_update_ctrl.dll_update_n_i
m 0 0
u 1 8
n ckid0_139 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.last_dll_step[7:0].C} Clock source is invalid for GCC
p {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_dll_update_ctrl.dll_update_n.Q[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_dll_update_ctrl.dll_update_n_inferred_clock.I[0]}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_dll_update_ctrl.dll_update_n_inferred_clock.OUT[0]}{p:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_dll_update_ctrl.dll_update_n}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_dll_update_ctrl.dll_update_n}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_update_n}{p:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_update_n}{t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.last_dll_step[7:0].C}
e ckid0_139 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.last_dll_step[7:0].C} dffr
d ckid0_140 {t:u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_dll_update_ctrl.dll_update_n.Q[0]} dffr Potential generated clock but with a nonconvertable driver or an unknown conversion method
i video_pll_m0.clkout0_i
m 0 0
u 55 245
n ckid0_141 {t:frame_read_write_m0.read_buf.U_ipml_fifo_afifo_64i_32o_128.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty.C} Black box on clock path
p {t:video_pll_m0.u_pll_e1.CLKOUT0}{t:video_pll_m0.clkout0_inferred_clock.I[0]}{t:video_pll_m0.clkout0_inferred_clock.OUT[0]}{p:video_pll_m0.clkout0}{t:video_pll_m0.clkout0}{t:video_timing_data_m0.video_clk}{p:video_timing_data_m0.video_clk}{t:video_timing_data_m0.read_req.C}
e ckid0_142 {t:video_timing_data_m0.read_req.C} dffre
d ckid0_141,ckid0_142 {t:video_pll_m0.u_pll_e1.CLKOUT0} GTP_PLL_E1 Black box on clock path
i sys_clk
m 0 0
u 78 470
p {p:sys_clk}{t:sd_card_bmp_m0.clk}{p:sd_card_bmp_m0.clk}{t:sd_card_bmp_m0.bmp_read_m0.clk}{p:sd_card_bmp_m0.bmp_read_m0.clk}{t:sd_card_bmp_m0.bmp_read_m0.state[4].C}
e ckid0_143 {t:sd_card_bmp_m0.bmp_read_m0.state[4].C} dffr
c ckid0_143 {p:sys_clk} port Unsupported/too complex instance on clock path
i video_pll_m0.clkout1_i
m 0 0
u 25 59
n ckid0_144 {t:dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[2:0].C} Black box on clock path
p {t:video_pll_m0.u_pll_e1.CLKOUT1}{t:video_pll_m0.clkout1_inferred_clock.I[0]}{t:video_pll_m0.clkout1_inferred_clock.OUT[0]}{p:video_pll_m0.clkout1}{t:video_pll_m0.clkout1}{t:dvi_encoder_m0.pixelclk5x}{p:dvi_encoder_m0.pixelclk5x}{t:dvi_encoder_m0.serdes_4b_10to1_m0.clkx5}{p:dvi_encoder_m0.serdes_4b_10to1_m0.clkx5}{t:dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[2:0].C}
e ckid0_144 {t:dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[2:0].C} sdffr
d ckid0_144 {t:video_pll_m0.u_pll_e1.CLKOUT1} GTP_PLL_E1 Black box on clock path
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw290_ca_04
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw290_ca_03
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_ififo_rpoint_1[2]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_ififo_rpoint_1[1]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_ififo_rpoint_1[0]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_ififo_wpoint_1[2]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_ififo_wpoint_1[1]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_ififo_wpoint_1[0]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_gate_to_loop_1
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw290_ca_01
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_ififo_rpoint_0[2]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_ififo_rpoint_0[1]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_ififo_rpoint_0[0]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_ififo_wpoint_0[2]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_ififo_wpoint_0[1]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_ififo_wpoint_0[0]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_gate_to_loop_0
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_mem_rst
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_odt[3]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_odt[2]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_odt[1]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_odt[0]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_we_n[3]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_we_n[2]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_we_n[1]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_we_n[0]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_cas_n[3]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_cas_n[2]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_cas_n[1]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_cas_n[0]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_ras_n[3]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_ras_n[2]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_ras_n[1]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_ras_n[0]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_cs_n[3]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_cs_n[2]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_cs_n[1]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_cs_n[0]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_cke[3]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_cke[2]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_cke[1]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_cke[0]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_ck[3]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_ck[2]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_ck[1]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_ck[0]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_ba[11]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_ba[10]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_ba[9]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_ba[8]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_ba[7]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_ba[6]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_ba[5]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_ba[4]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_ba[3]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_ba[2]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_ba[1]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_ba[0]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[63]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[62]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[61]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[60]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[59]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[58]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[57]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[56]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[55]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[54]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[53]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[52]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[51]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[50]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[49]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[48]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[47]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[46]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[45]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[44]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[43]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[42]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[41]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[40]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[39]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[38]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[37]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[36]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[35]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[34]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[33]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[32]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[31]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[30]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[29]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[28]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[27]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[26]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[25]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[24]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[23]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[22]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[21]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[20]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[19]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[18]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_addr[17]
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i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_mipi_sw_dyn_i[3]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_mipi_sw_dyn_i[2]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_mipi_sw_dyn_i[1]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_mipi_sw_dyn_i[0]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[179]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[178]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[177]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[176]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[175]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[174]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[173]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[172]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[171]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[170]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[169]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[168]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[167]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[166]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[165]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[164]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[163]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[162]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[161]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[160]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[159]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[158]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[157]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[156]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[155]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[154]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[153]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[152]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[151]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[150]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[149]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[148]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[147]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[146]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[145]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[144]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[143]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[142]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[141]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[140]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[139]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[138]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[137]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[136]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[135]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[134]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[133]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[132]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[131]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[130]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[129]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[128]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[127]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[126]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[125]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[124]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[123]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[122]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[121]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[120]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[119]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[118]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[117]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[116]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[115]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[114]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[113]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[112]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[111]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[110]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[109]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[108]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[107]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[106]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[105]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[104]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[103]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[102]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[101]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[100]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[99]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[98]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[97]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[96]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[95]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[94]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[93]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[92]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[91]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[90]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[89]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[88]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[87]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[86]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[85]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[84]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[83]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[82]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[81]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[80]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[79]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[78]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[77]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[76]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[75]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[74]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[73]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[72]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[71]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[70]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[69]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[68]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[67]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[66]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[65]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[64]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[63]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[62]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[61]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[60]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[59]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[58]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[57]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[56]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[55]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[54]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[53]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[52]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[51]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[50]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[49]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[48]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[47]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[46]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[45]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[44]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[43]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[42]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[41]
m 0 0
u 0 0
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i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[39]
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i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_iol_iodly_ctrl[36]
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i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_rst_dll
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i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wdata_h[31]
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i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wdata_h[23]
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i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wdata_h[22]
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i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wdata_h[21]
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i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wdata_h[20]
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i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wdata_h[17]
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i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wdata_h[15]
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i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wdata_h[13]
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i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wdata_h[12]
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i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wdata_h[11]
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i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wdata_h[10]
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i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wdata_h[9]
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i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wdata_h[8]
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i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wdata_h[7]
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i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wdata_h[6]
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i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wdata_h[5]
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i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wdata_h[4]
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i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wdata_h[3]
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i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wdata_h[1]
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i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wdata_h[0]
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i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wen_h[15]
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i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wen_h[14]
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i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wen_h[13]
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i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wen_h[12]
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i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wen_h[11]
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i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wen_h[10]
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i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wen_h[9]
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i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wen_h[8]
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i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wl_ctrl_l[0]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wl_step_l[7]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wl_step_l[6]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wl_step_l[5]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wl_step_l[4]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wl_step_l[3]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wl_step_l[2]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wl_step_l[1]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_wl_step_l[0]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_gatei_l
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_gatei_h
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs4_dut
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs4_dut_10
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs4_dut_9[1]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs4_dut_9[0]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs4_dut_3[2]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs4_dut_3[1]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs4_dut_3[0]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs4_dut_4[2]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs4_dut_4[1]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs4_dut_4[0]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs4_dut_5
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs4_dut_8
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs4_dut_7
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs4_dut_2
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs4_dut_6
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs4_dut_1
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs3_dut_3
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs3_dut_7
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs3_dut_10[1]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs3_dut_10[0]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs3_dut_5[2]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs3_dut_5[1]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs3_dut_5[0]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs3_dut_6[2]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs3_dut_6[1]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs3_dut_6[0]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs3_dut_1
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs3_dut_9
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs3_dut_8
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs3_dut
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs3_dut_2
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs3_dut_4
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs2_dut_1
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs2_dut_2
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs2_dut[1]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs2_dut[0]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs1_dut_9
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs1_dut_8
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs1_dut_2[1]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs1_dut_2[0]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs1_dut_6[2]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs1_dut_6[1]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs1_dut_6[0]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs1_dut_10[2]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs1_dut_10[1]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs1_dut_10[0]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs1_dut_1
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs1_dut_5
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs1_dut_7
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs1_dut
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs1_dut_4
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs1_dut_3
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs0_dut_1
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs0_dut_2
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs0_dut[1]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.un1_dqs0_dut[0]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_LP_ACK
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_PHYUPD_TYPE[1]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_PHYUPD_TYPE[0]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_PHYUPD_REQ
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_INIT_COMPLETE
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_CTRLUPD_ACK
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA_VALID[3]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA_VALID[2]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA_VALID[1]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA_VALID[0]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[63]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[62]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[61]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[60]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[59]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[58]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[57]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[56]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[55]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[54]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[53]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[52]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[51]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[50]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[49]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[48]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[47]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[46]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[45]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[44]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[43]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[42]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[41]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[40]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[39]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[38]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[37]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[36]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[35]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[34]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[33]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[32]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[31]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[30]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[29]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[28]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[27]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[26]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[25]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[24]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[23]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[22]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[21]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[20]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[19]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[18]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[17]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[16]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[15]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[14]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[13]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[12]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[11]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[10]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[9]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[8]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[7]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[6]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[5]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[4]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[3]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[2]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[1]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_RDDATA[0]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_ERROR_INFO[2]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_ERROR_INFO[1]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_ERROR_INFO[0]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DFI_ERROR
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DLL_UPDATE_REQ
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DDRPHY_UPDATE_DONE
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.DDRPHY_RST_REQ
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.PRDATA[31]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.PRDATA[30]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.PRDATA[29]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.PRDATA[28]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.PRDATA[27]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.PRDATA[26]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.PRDATA[25]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.PRDATA[24]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.PRDATA[23]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.PRDATA[22]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.PRDATA[21]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.PRDATA[20]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.PRDATA[19]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.PRDATA[18]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.PRDATA[17]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.PRDATA[16]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.PRDATA[15]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.PRDATA[14]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.PRDATA[13]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.PRDATA[12]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.PRDATA[11]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.PRDATA[10]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.PRDATA[9]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.PRDATA[8]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.PRDATA[7]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.PRDATA[6]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.PRDATA[5]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.PRDATA[4]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.PRDATA[3]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.PRDATA[2]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.PRDATA[1]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.PRDATA[0]
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.PREADY
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_pll_50_400.clkswitch_flag
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_pll_50_400.clkout5
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_pll_50_400.clkout0_2pad
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_pll_50_400.pll_lock
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_pll_50_400.clkout4
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_pll_50_400.clkout2
m 0 0
u 0 0
i u_ipsl_hmemc_top.u_pll_50_400.clkout0
m 0 0
u 0 0
i video_pll_m0.clkswitch_flag
m 0 0
u 0 0
i video_pll_m0.clkout5
m 0 0
u 0 0
i video_pll_m0.clkout4
m 0 0
u 0 0
i video_pll_m0.clkout3
m 0 0
u 0 0
i video_pll_m0.clkout2
m 0 0
u 0 0
i video_pll_m0.clkout0_2pad
m 0 0
u 0 0
i video_pll_m0.pll_lock
m 0 0
u 0 0
l 0 0 0 0 0
r 0 0 0 0 0 0 0 0
