//****************************************Copyright (c)***********************************//
//----------------------------------------------------------------------------------------
//****************************************************************************************//

module binarization #(
    	parameter		P_LOG_ENABLE   = 0  
 //      parameter            THRESHOLD      = 8'd64   
)(
    //module clock
    input               clk             ,   // 时钟信号
    input               rst_n           ,   // 复位信号（低有效��

    //图像处理前的数据接口
    input               pre_frame_vsync ,   // vsync信号
    input               pre_frame_hsync ,   // hsync信号
    input               pre_frame_de    ,   // data enable信号
    input   [7:0]       color           ,

    //图像处理后的数据接口
    output              post_frame_vsync,   // vsync信号
    output              post_frame_hsync,   // hsync信号
    output              post_frame_de   ,   // data enable信号
    output  [23:0]      orign_color     ,
    output   reg [7:0]  bin_color       ,
    output   reg        monoc           ,   // monochrome��=白，0=黑）
    output              monoc_fall      ,
    input   [7:0]       THRESHOLD 

    //user interface
);

//reg define
reg       monoc_d0         ;
reg       pre_frame_vsync_d;
reg       pre_frame_hsync_d;
reg       pre_frame_de_d   ;
reg [7:0] orign_color_d    ;
//*****************************************************
//**                    main code
//*****************************************************

assign  monoc_fall       = (!monoc) & monoc_d0;
assign  post_frame_vsync = pre_frame_vsync_d  ;
assign  post_frame_hsync = pre_frame_hsync_d  ;
assign  post_frame_de    = pre_frame_de_d     ;
assign  orign_color = {orign_color_d,orign_color_d,orign_color_d};
//寄存以找下降��
always @(posedge clk) begin
    monoc_d0 <= monoc;
end

//二值化
always @(posedge clk or negedge rst_n) begin
    if(!rst_n)
        monoc <= 1'b0;
    else if(color > THRESHOLD)  //阈��
        monoc <= 1'b1;
    else
        monoc <= 1'b0;
end

always @(posedge clk or negedge rst_n) begin
    if(!rst_n)
        bin_color <= 8'hff;
    else if(color > THRESHOLD)  //阈��
        bin_color <= 8'h00;
    else
        bin_color <= 8'hff;
end

//延时2拍以同步时钟信号
always@(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        pre_frame_vsync_d <= 1'd0;
        pre_frame_hsync_d <= 1'd0;
        pre_frame_de_d    <= 1'd0;
        orign_color_d     <= 24'd0;
    end
    else begin
        pre_frame_vsync_d <= pre_frame_vsync;
        pre_frame_hsync_d <= pre_frame_hsync;
        pre_frame_de_d    <= pre_frame_de   ;
        orign_color_d     <= color;
    end
end

	generate
	if (P_LOG_ENABLE == 32'd1) begin: log
		integer BINARIZATION_file   	;
		
		initial begin
//		    BINARIZATION_file  = $fopen ({"D:/FPGA_CODE/Other_work/fruit/Sim/ISP_sim/Data/BINARIZATION.txt"}   , "w" ) ;
		    BINARIZATION_file  = $fopen ({"BINARIZATION.txt"}   , "w" ) ;
		end
		
		always @ ( posedge clk ) begin
			if ( pre_frame_de_d ) begin
		    	$fdisplay (BINARIZATION_file , "%b", bin_color) ;
			end
		end		
	end 
	endgenerate

endmodule
