module line_shift(
    input clk,
    input rst_n,
    input          ycbcr_de,
    input          ycbcr_hs,
    
    input   [7:0]  shiftin,  
    output  [7:0]  taps0x,   
    output  [7:0]  taps1x    
);

reg  [2:0]  clken_dly;
reg  [9:0]  ram_rd_addr;
reg  [9:0]  ram_rd_addr_d0;
reg  [9:0]  ram_rd_addr_d1;
reg  [9:0]  ram_rd_addr_d2;
reg  [9:0]  ram_rd_addr_d3;
reg  [7:0]  shiftin_d0;
reg  [7:0]  shiftin_d1;
reg  [7:0]  shiftin_d2;
reg  [7:0]  taps0x_d0;





always@(posedge clk)begin
    if(ycbcr_hs)
        if(ycbcr_de)
            ram_rd_addr <= ram_rd_addr + 1 ;
        else
            ram_rd_addr <= ram_rd_addr ;
    else
        ram_rd_addr <= 0 ;
end


always@(posedge clk) begin
    clken_dly <= { clken_dly[1:0] , ycbcr_de };
end

always@(posedge clk ) begin
    ram_rd_addr_d0 <= ram_rd_addr;
    ram_rd_addr_d1 <= ram_rd_addr_d0;
end

always@(posedge clk)begin
    shiftin_d0 <= shiftin;
    shiftin_d1 <= shiftin_d0;
    shiftin_d2 <= shiftin_d1;
end

//dpram initial write zero
localparam     depth = 10'd1023 ;

reg       [9:0]       cnt    ;
wire      [7:0]       data1  ;
wire      [7:0]       data2  ;
wire                  wren1  ;
wire                  wren2  ;
wire      [9:0]       wradds1;
wire      [9:0]       wradds2;

always@(posedge clk or negedge rst_n) begin
    if (!rst_n)
      cnt  <=  10'd0  ;
    else if (cnt == depth)
      cnt  <=  cnt    ;
    else 
      cnt <= cnt + 10'd1;
end    

assign  data1 = (cnt == depth)?shiftin_d2:8'd0;
assign  data2 = (cnt == depth)?taps0x_d0:8'd0;
assign  wren1 = (cnt == depth)?clken_dly[2]:1'b1;
assign  wren2 = (cnt == depth)?clken_dly[1]:1'b1;
assign  wradds1 = (cnt == depth)?ram_rd_addr_d1:cnt;
assign  wradds2 = (cnt == depth)?ram_rd_addr:cnt;

dpram ram_1024x8_m0 (
    .clock(clk),          // INPUT
    .wren(wren1),            // INPUT
    .data(data1),            // INPUT[7:0] 
    .wraddress(wradds1),  // INPUT[9:0] 
    .rdaddress(ram_rd_addr),  // INPUT[9:0] 
    .q(taps0x)                  // OUTPUT[7:0]
);
//dpram ram_1024x8_m0 (
//    .clock(clk),          // INPUT
//    .wren(clken_dly[2]),            // INPUT
//    .data(shiftin_d2),            // INPUT[7:0] 
//    .wraddress(ram_rd_addr_d1),  // INPUT[9:0] 
//    .rdaddress(ram_rd_addr),  // INPUT[9:0] 
//    .q(taps0x)                  // OUTPUT[7:0]
//);
//寄存一次前一行图像的数据
always@(posedge clk ) begin
    taps0x_d0 <= taps0x;
end

dpram ram_1024x8_m1 (
    .clock(clk),          // INPUT
//    .wren(clken_dly[1]),            // INPUT
    .wren(wren2),
    .data(data2),            // INPUT[7:0] 
    .wraddress(wradds2),  // INPUT[9:0] 
    .rdaddress(ram_rd_addr_d0),  // INPUT[9:0] 
    .q(taps1x)                  // OUTPUT[7:0]
);

//dpram ram_1024x8_m1 (
//    .clock(clk),          // INPUT
////    .wren(clken_dly[1]),            // INPUT
//    .wren(clken_dly[0]),
//    .data(taps0x_d0),            // INPUT[7:0] 
//    .wraddress(ram_rd_addr),  // INPUT[9:0] 
//    .rdaddress(ram_rd_addr_d0),  // INPUT[9:0] 
//    .q(taps1x)                  // OUTPUT[7:0]
//);

endmodule 