#Build: Fabric Compiler 2020.3, Build 62942, Sep 29 13:34 2020
#Install: D:\pango\PDS_2020.3\bin
#Application name: pds_shell.exe
#OS: Windows 10 10.0.19042
#Hostname: DESKTOP-0NUJMPK
Generated by Fabric Compiler (version 2020.3 build 62942) at Fri May 27 22:57:26 2022
Executing : add_design -verilog D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v
Executing : add_design -verilog D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v successfully.
Executing : add_design -verilog D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp
Executing : add_design -verilog D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp successfully.
Executing : add_design -verilog D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp
Executing : add_design -verilog D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp successfully.
Executing : add_design -verilog D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp
Executing : add_design -verilog D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp successfully.
Executing : add_design -verilog D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp
Executing : add_design -verilog D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp successfully.
Executing : add_design -verilog D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp
Executing : add_design -verilog D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp successfully.
Executing : add_design -verilog D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp
Executing : add_design -verilog D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp successfully.
Executing : add_design -verilog D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp
Executing : add_design -verilog D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp successfully.
Executing : add_design -verilog D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp
Executing : add_design -verilog D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp successfully.
Executing : add_design -verilog D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp
Executing : add_design -verilog D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp successfully.
Executing : add_design -verilog D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp
Executing : add_design -verilog D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp successfully.
Executing : add_design -verilog D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp
Executing : add_design -verilog D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp successfully.
Executing : add_design -verilog D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp
Executing : add_design -verilog D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp successfully.
Executing : add_constraint -fdc D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc
Executing : add_constraint -fdc D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc successfully.
Executing : set_arch -family Logos -device PGL22G -package MBG324 -speedgrade -6
Executing : set_arch -family Logos -device PGL22G -package MBG324 -speedgrade -6 successfully.


Executing : compile
Process "Compile" started.
Current time: Fri May 27 22:57:26 2022
Compiling architecture definition.
Analyzing project file 'D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/dbcore.pds'.
License checkout: fabric_ads
Compiling verification operator library.
Loading technology operator library.
Compiling technology operator library.
Compiling technology operator (valence) library.
I: Enable Verilog2k features and keywords
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v(line number: 1)] Analyzing module CORES (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev} D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp
I: Verilog-0001: Analyzing file D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp
I: Verilog-0002: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp(line number: 90)] Analyzing module ips_dbc_cfg_reg_file_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev} D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev} D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp
I: Verilog-0001: Analyzing file D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp
I: Verilog-0002: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 301)] Analyzing module ips_dbc_compare_256b_v1_0 (library work)
I: Verilog-0002: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Analyzing module subtract_16b (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev} D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev} D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp
I: Verilog-0001: Analyzing file D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp
I: Verilog-0002: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp(line number: 89)] Analyzing module ips_dbc_data_capture_mem_v1_1 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev} D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev} D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp
I: Verilog-0001: Analyzing file D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp
I: Verilog-0002: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 2822)] Analyzing module ips_dbc_debug_core_v1_4 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev} D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev} D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp
I: Verilog-0001: Analyzing file D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp
I: Verilog-0002: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp(line number: 271)] Analyzing module ips_dbc_hub_decode_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev} D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev} D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp
I: Verilog-0001: Analyzing file D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp
I: Verilog-0002: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp(line number: 251)] Analyzing module ips_dbc_rd_addr_gen_v1_3 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev} D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev} D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp
I: Verilog-0001: Analyzing file D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp
I: Verilog-0002: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp(line number: 489)] Analyzing module ips_dbc_storage_condition_v1_3 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev} D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev} D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp
I: Verilog-0001: Analyzing file D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp
I: Verilog-0002: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp(line number: 177)] Analyzing module ips_dbc_storage_qualification_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev} D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev} D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp
I: Verilog-0001: Analyzing file D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp
I: Verilog-0002: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 409)] Analyzing module ips_dbc_trig_unit_v1_3 (library work)
W: Verilog-2018: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 819)] The value type of attribute syn_allow_retiming is illegal, ignore the attribute
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev} D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev} D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp
I: Verilog-0001: Analyzing file D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp
I: Verilog-0002: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp(line number: 278)] Analyzing module ips_dbc_trigger_condition_v1_3 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev} D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev} D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp
I: Verilog-0001: Analyzing file D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp
I: Verilog-0002: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp(line number: 142)] Analyzing module ips_dbc_trigger_output_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev} D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev} D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp
I: Verilog-0001: Analyzing file D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp
I: Verilog-0002: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp(line number: 282)] Analyzing module ips_jtag_hub_v1_3 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev} D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp successfully.
 0.284394s wall, 0.156250s user + 0.125000s system = 0.281250s CPU (98.9%)
Start rtl-elaborate.
I: Top module is unspecified.
I: Module "CORES" is set as top module.
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v(line number: 1)] Elaborating module CORES
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/library/operator/gtp_lib.v(line number: 22308)] Elaborating module GTP_SCANCHAIN_E1
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp(line number: 282)] Elaborating module ips_jtag_hub_v1_3
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 2822)] Elaborating module ips_dbc_debug_core_v1_4
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp(line number: 271)] Elaborating module ips_dbc_hub_decode_v1_2
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 409)] Elaborating module ips_dbc_trig_unit_v1_3
W: Sdm-2008: The attribute named register_balancing is not legal, then it has no effect, ignore its value.
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp(line number: 90)] Elaborating module ips_dbc_cfg_reg_file_v1_0
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 301)] Elaborating module ips_dbc_compare_256b_v1_0
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Elaborating module subtract_16b
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Elaborating module subtract_16b
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Elaborating module subtract_16b
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Elaborating module subtract_16b
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Elaborating module subtract_16b
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Elaborating module subtract_16b
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Elaborating module subtract_16b
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Elaborating module subtract_16b
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Elaborating module subtract_16b
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Elaborating module subtract_16b
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Elaborating module subtract_16b
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Elaborating module subtract_16b
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Elaborating module subtract_16b
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Elaborating module subtract_16b
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Elaborating module subtract_16b
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Elaborating module subtract_16b
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 301)] Elaborating module ips_dbc_compare_256b_v1_0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 459)] Net trigger in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 577)] Net value in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 578)] Net value2 in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[0].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[0].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[1].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[1].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[2].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[2].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[3].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[3].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[4].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[4].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[5].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[5].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[6].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[6].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[7].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[7].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[8].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[8].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[9].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[9].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[10].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[10].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[11].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[11].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[12].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[12].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[13].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[13].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[14].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[14].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[15].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[15].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[16].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[16].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[17].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[17].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[18].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[18].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[19].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[19].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[20].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[20].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[21].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[21].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[22].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[22].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[23].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[23].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[24].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[24].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[25].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[25].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[26].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[26].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[27].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[27].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[28].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[28].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[29].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[29].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[30].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[30].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[31].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[31].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[32].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[32].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[33].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[33].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[34].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[34].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[35].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[35].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[36].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[36].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[37].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[37].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[38].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[38].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[39].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[39].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[40].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[40].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[41].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[41].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[42].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[42].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[43].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[43].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[44].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[44].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[45].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[45].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[46].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[46].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[47].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[47].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[48].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[48].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[49].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[49].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[50].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[50].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[51].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[51].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[52].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[52].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[53].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[53].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[54].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[54].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[55].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[55].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[56].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[56].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[57].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[57].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[58].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[58].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[59].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[59].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[60].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[60].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[61].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[61].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[62].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[62].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[63].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[63].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[64].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[64].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[65].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[65].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[66].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[66].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[67].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[67].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[68].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[68].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[69].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[69].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[70].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[70].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[71].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[71].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[72].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[72].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[73].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[73].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[74].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[74].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[75].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[75].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[76].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[76].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[77].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[77].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[78].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[78].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[79].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[79].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[80].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[80].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[81].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[81].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[82].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[82].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[83].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[83].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[84].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[84].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[85].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[85].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[86].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[86].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[87].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[87].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[88].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[88].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[89].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[89].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[90].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[90].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[91].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[91].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[92].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[92].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[93].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[93].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[94].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[94].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[95].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[95].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[96].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[96].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[97].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[97].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[98].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[98].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[99].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[99].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[100].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[100].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[101].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[101].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[102].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[102].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[103].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[103].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[104].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[104].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[105].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[105].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[106].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[106].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[107].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[107].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[108].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[108].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[109].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[109].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[110].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[110].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[111].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[111].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[112].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[112].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[113].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[113].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[114].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[114].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[115].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[115].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[116].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[116].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[117].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[117].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[118].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[118].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[119].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[119].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[120].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[120].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[121].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[121].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[122].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[122].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[123].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[123].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[124].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[124].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[125].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[125].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[126].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[126].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[127].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[127].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[128].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[128].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[129].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[129].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[130].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[130].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[131].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[131].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[132].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[132].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[133].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[133].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[134].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[134].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[135].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[135].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[136].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[136].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[137].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[137].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[138].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[138].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[139].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[139].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[140].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[140].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[141].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[141].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[142].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[142].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[143].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[143].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[144].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[144].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[145].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[145].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[146].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[146].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[147].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[147].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[148].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[148].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[149].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[149].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[150].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[150].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[151].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[151].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[152].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[152].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[153].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[153].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[154].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[154].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[155].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[155].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[156].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[156].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[157].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[157].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[158].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[158].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[159].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[159].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[160].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[160].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[161].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[161].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[162].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[162].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[163].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[163].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[164].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[164].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[165].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[165].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[166].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[166].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[167].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[167].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[168].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[168].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[169].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[169].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[170].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[170].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[171].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[171].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[172].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[172].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[173].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[173].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[174].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[174].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[175].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[175].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[176].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[176].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[177].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[177].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[178].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[178].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[179].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[179].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[180].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[180].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[181].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[181].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[182].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[182].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[183].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[183].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[184].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[184].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[185].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[185].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[186].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[186].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[187].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[187].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[188].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[188].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[189].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[189].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[190].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[190].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[191].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[191].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[192].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[192].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[193].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[193].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[194].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[194].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[195].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[195].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[196].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[196].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[197].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[197].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[198].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[198].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[199].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[199].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[200].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[200].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[201].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[201].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[202].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[202].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[203].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[203].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[204].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[204].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[205].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[205].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[206].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[206].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[207].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[207].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[208].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[208].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[209].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[209].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[210].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[210].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[211].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[211].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[212].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[212].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[213].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[213].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[214].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[214].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[215].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[215].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[216].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[216].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[217].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[217].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[218].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[218].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[219].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[219].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[220].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[220].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[221].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[221].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[222].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[222].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[223].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[223].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[224].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[224].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[225].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[225].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[226].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[226].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[227].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[227].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[228].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[228].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[229].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[229].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[230].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[230].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[231].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[231].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[232].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[232].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[233].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[233].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[234].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[234].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[235].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[235].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[236].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[236].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[237].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[237].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[238].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[238].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[239].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[239].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[240].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[240].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[241].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[241].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[242].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[242].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[243].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[243].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[244].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[244].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[245].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[245].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[246].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[246].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[247].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[247].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[248].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[248].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[249].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[249].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[250].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[250].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 625)] Net genblk4.G_MATCH_NO_EDGE[251].mu_bit_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 626)] Net genblk4.G_MATCH_NO_EDGE[251].signal_single in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 804)] Net G_MATCH_OPTIMIZE_BALANCED.match_comb_ff in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 819)] Net G_MATCH_OPTIMIZE_SPEED.match_comb_ff in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 866)] Net G_MATCH_COUNTER.mu_cnt_mode in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 869)] Net G_MATCH_COUNTER.mu_cnt_value in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 872)] Net G_MATCH_COUNTER.mu_counter in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 873)] Net G_MATCH_COUNTER.mu_counter_plus in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 875)] Net G_MATCH_COUNTER.match_src_w in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 892)] Net G_MATCH_COUNTER.match_enable in module ips_dbc_trig_unit_v1_3 does not have a driver, tie it to 0
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp(line number: 278)] Elaborating module ips_dbc_trigger_condition_v1_3
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp(line number: 90)] Elaborating module ips_dbc_cfg_reg_file_v1_0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp(line number: 408)] Net trig_neg_whole in module ips_dbc_trigger_condition_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp(line number: 412)] Net trig_contiguous in module ips_dbc_trigger_condition_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp(line number: 413)] Net trig_seq_level in module ips_dbc_trigger_condition_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp(line number: 415)] Net trig_seq_neg in module ips_dbc_trigger_condition_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp(line number: 416)] Net trig_mode in module ips_dbc_trigger_condition_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp(line number: 513)] Net seq_match_s in module ips_dbc_trigger_condition_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp(line number: 531)] Net trig_seq_pipeline in module ips_dbc_trigger_condition_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp(line number: 537)] Net G_TRIG_SEQ_PIPELINEBASE.trig_seq_pipeline_reg in module ips_dbc_trigger_condition_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp(line number: 552)] Net trig_seq in module ips_dbc_trigger_condition_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp(line number: 575)] Net genblk10.G_TRIG_NOMUX_BALANCED.trigger_reg in module ips_dbc_trigger_condition_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp(line number: 587)] Net genblk10.G_TRIG_NOMUX_SPEED.trigger_en in module ips_dbc_trigger_condition_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp(line number: 588)] Net genblk10.G_TRIG_NOMUX_SPEED.trigger_en_next in module ips_dbc_trigger_condition_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp(line number: 598)] Net genblk10.G_TRIG_NOMUX_SPEED.trigger_reg in module ips_dbc_trigger_condition_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp(line number: 615)] Net G_TRIG_MUX_BALANCED.trigger_reg in module ips_dbc_trigger_condition_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp(line number: 627)] Net G_TRIG_MUX_SPEED.trigger_en in module ips_dbc_trigger_condition_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp(line number: 628)] Net G_TRIG_MUX_SPEED.trigger_en_next in module ips_dbc_trigger_condition_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp(line number: 638)] Net G_TRIG_MUX_SPEED.trigger_reg in module ips_dbc_trigger_condition_v1_3 does not have a driver, tie it to 0
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp(line number: 489)] Elaborating module ips_dbc_storage_condition_v1_3
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp(line number: 90)] Elaborating module ips_dbc_cfg_reg_file_v1_0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp(line number: 900)] Net counter_nsa[0] in module ips_dbc_storage_condition_v1_3 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp(line number: 900)] Net counter_nsa[1] in module ips_dbc_storage_condition_v1_3 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp(line number: 900)] Net counter_nsa[2] in module ips_dbc_storage_condition_v1_3 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp(line number: 900)] Net counter_nsa[3] in module ips_dbc_storage_condition_v1_3 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp(line number: 900)] Net counter_nsa[4] in module ips_dbc_storage_condition_v1_3 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp(line number: 900)] Net counter_nsa[5] in module ips_dbc_storage_condition_v1_3 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp(line number: 900)] Net counter_nsa[6] in module ips_dbc_storage_condition_v1_3 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp(line number: 900)] Net counter_nsa[7] in module ips_dbc_storage_condition_v1_3 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp(line number: 900)] Net counter_nsa[8] in module ips_dbc_storage_condition_v1_3 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp(line number: 900)] Net counter_nsa[9] in module ips_dbc_storage_condition_v1_3 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp(line number: 900)] Net counter_nsa[10] in module ips_dbc_storage_condition_v1_3 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp(line number: 900)] Net counter_nsa[11] in module ips_dbc_storage_condition_v1_3 does not have a driver, tie it to 0
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp(line number: 89)] Elaborating module ips_dbc_data_capture_mem_v1_1
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp(line number: 251)] Elaborating module ips_dbc_rd_addr_gen_v1_3
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 4126)] Net DATA_SYNC.DATA_SYNC_PIPELINE.i in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[1] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[2] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[3] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[4] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[5] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[6] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[7] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[8] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[9] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[10] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[11] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[12] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[13] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[14] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[15] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[17] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[19] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[1] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[2] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[3] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[4] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[5] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[6] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[7] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[8] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[9] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[10] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[11] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[12] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[13] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[14] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[15] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[17] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2020: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[19] in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5215)] Net G_M_1.mu_signal_concat_1 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5218)] Net G_M_1.mu_signal_combine_1 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5221)] Net G_M_1.signal_combine_1 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5255)] Net G_M_2.mu_signal_concat_2 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5258)] Net G_M_2.mu_signal_combine_2 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5261)] Net G_M_2.signal_combine_2 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5295)] Net G_M_3.mu_signal_concat_3 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5298)] Net G_M_3.mu_signal_combine_3 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5301)] Net G_M_3.signal_combine_3 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5335)] Net G_M_4.mu_signal_concat_4 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5338)] Net G_M_4.mu_signal_combine_4 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5341)] Net G_M_4.signal_combine_4 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5375)] Net G_M_5.mu_signal_concat_5 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5378)] Net G_M_5.mu_signal_combine_5 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5381)] Net G_M_5.signal_combine_5 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5415)] Net G_M_6.mu_signal_concat_6 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5418)] Net G_M_6.mu_signal_combine_6 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5421)] Net G_M_6.signal_combine_6 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5455)] Net G_M_7.mu_signal_concat_7 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5458)] Net G_M_7.mu_signal_combine_7 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5461)] Net G_M_7.signal_combine_7 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5495)] Net G_M_8.mu_signal_concat_8 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5498)] Net G_M_8.mu_signal_combine_8 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5501)] Net G_M_8.signal_combine_8 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5535)] Net G_M_9.mu_signal_concat_9 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5538)] Net G_M_9.mu_signal_combine_9 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5541)] Net G_M_9.signal_combine_9 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5575)] Net G_M_10.mu_signal_concat_10 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5578)] Net G_M_10.mu_signal_combine_10 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5581)] Net G_M_10.signal_combine_10 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5615)] Net G_M_11.mu_signal_concat_11 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5618)] Net G_M_11.mu_signal_combine_11 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5621)] Net G_M_11.signal_combine_11 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5655)] Net G_M_12.mu_signal_concat_12 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5658)] Net G_M_12.mu_signal_combine_12 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5661)] Net G_M_12.signal_combine_12 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5695)] Net G_M_13.mu_signal_concat_13 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5698)] Net G_M_13.mu_signal_combine_13 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5701)] Net G_M_13.signal_combine_13 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5735)] Net G_M_14.mu_signal_concat_14 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5738)] Net G_M_14.mu_signal_combine_14 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5741)] Net G_M_14.signal_combine_14 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5775)] Net G_M_15.mu_signal_concat_15 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5778)] Net G_M_15.mu_signal_combine_15 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5781)] Net G_M_15.signal_combine_15 in module ips_dbc_debug_core_v1_4 does not have a driver, tie it to 0
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v(line number: 122)] Give initial value 0 for the no drive pin TCK in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v(line number: 122)] Give initial value 0 for the no drive pin TDI in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v(line number: 122)] Give initial value 0 for the no drive pin TMS in module instance
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v(line number: 136)] Net hub_tdo[1] in module CORES does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v(line number: 136)] Net hub_tdo[2] in module CORES does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v(line number: 136)] Net hub_tdo[3] in module CORES does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v(line number: 136)] Net hub_tdo[4] in module CORES does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v(line number: 136)] Net hub_tdo[5] in module CORES does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v(line number: 136)] Net hub_tdo[6] in module CORES does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v(line number: 136)] Net hub_tdo[7] in module CORES does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v(line number: 136)] Net hub_tdo[8] in module CORES does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v(line number: 136)] Net hub_tdo[9] in module CORES does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v(line number: 136)] Net hub_tdo[10] in module CORES does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v(line number: 136)] Net hub_tdo[11] in module CORES does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v(line number: 136)] Net hub_tdo[12] in module CORES does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v(line number: 136)] Net hub_tdo[13] in module CORES does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v(line number: 136)] Net hub_tdo[14] in module CORES does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v(line number: 136)] Net hub_tdo[15] in module CORES does not have a driver, tie it to 0
Executing : rtl-elaborate successfully.
 0.676837s wall, 0.468750s user + 0.187500s system = 0.656250s CPU (97.0%)
Start rtl-prep.
Executing : rtl-prep successfully.
 1.097150s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (101.1%)
Start rtl-infer.
I: Removed inst tu_sig_dly that is redundant to signal_dly[251:0].
I: Sdm-0001: Found Ram block_ram.ram_data, depth=2048, width=253.
Executing : rtl-infer successfully.
 4.203347s wall, 3.953125s user + 0.203125s system = 4.156250s CPU (98.9%)
Start rtl-control-opt.
Executing : rtl-control-opt successfully.
 0.159771s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (97.8%)
Start rtl-data-opt.
Executing : rtl-data-opt successfully.
 0.755400s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (97.2%)
Start FSM inference.
Executing : FSM inference successfully.
 0.090760s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (103.3%)
Start sdm2adm.
I: Constant propagation done on N359 (bmsWIDEMUX).
I: Constant propagation done on N360 (bmsWIDEMUX).
I: Constant propagation done on N361 (bmsWIDEMUX).
I: Constant propagation done on N362 (bmsWIDEMUX).
I: Constant propagation done on N363 (bmsWIDEMUX).
I: Constant propagation done on N364 (bmsWIDEMUX).
I: Constant propagation done on N365 (bmsWIDEMUX).
I: Constant propagation done on N366 (bmsWIDEMUX).
I: Constant propagation done on N367 (bmsWIDEMUX).
I: Constant propagation done on N368 (bmsWIDEMUX).
Executing : sdm2adm successfully.
 0.630901s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (96.6%)
Saving design to DB.
Action compile: Real time elapsed is 10.000 sec
Action compile: CPU time elapsed is 8.344 sec
Current time: Fri May 27 22:57:35 2022
Action compile: Peak memory pool usage is 147,079,168 bytes
Process "Compile" done.
Executing : compile successfully.


Executing : synthesize -ADS -disable_io_insertion -infer_clock_en false
Process "Synthesize" started.
Current time: Fri May 27 22:57:35 2022
Compiling architecture definition.
Analyzing project file 'D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/dbcore.pds'.
License checkout: fabric_ads
Compiling verification operator library.
Compiling common defs.
Loading technology operator library.
Compiling technology operator library.
Compiling technology operator (valence) library.
Reading design from compile DB
Reading design from compile DB successfully.
NOTE: The technology fpga was specified.
NOTE: delay_model specified was generic_cmos.
NOTE: Using the fpga syntax tables...
Totals:
 Calls to malloc = 0
 Calls to calloc = 352549

Constraint check start.
Compiling prim grid devices.
Building architecture model.
Loading device packaging model 'MBG324'.
Building architecture floorplan logic view.
Executing : get_pins u_GTP_SCANCHAIN_PG.TCK_USER
Executing : get_pins u_GTP_SCANCHAIN_PG.TCK_USER successfully.
Executing : create_clock -name DebugCore_JCLK [get_pins u_GTP_SCANCHAIN_PG.TCK_USER] -period 50.000 -waveform {0.000 25.000}
Executing : create_clock -name DebugCore_JCLK [get_pins u_GTP_SCANCHAIN_PG.TCK_USER] -period 50.000 -waveform {0.000 25.000} successfully.
Executing : get_pins u_GTP_SCANCHAIN_PG.CAPDR
Executing : get_pins u_GTP_SCANCHAIN_PG.CAPDR successfully.
Executing : create_clock -name DebugCore_CAPTURE [get_pins u_GTP_SCANCHAIN_PG.CAPDR] -period 100.000 -waveform {25.000 75.000}
Executing : create_clock -name DebugCore_CAPTURE [get_pins u_GTP_SCANCHAIN_PG.CAPDR] -period 100.000 -waveform {25.000 75.000} successfully.
Executing : set_clock_groups -name DebugCoreClockGroup -asynchronous -group {DebugCore_JCLK DebugCore_CAPTURE}
Executing : set_clock_groups -name DebugCoreClockGroup -asynchronous -group {DebugCore_JCLK DebugCore_CAPTURE} successfully.
W: ConstraintEditor-4019: Port 'dbc_urck_in' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'dbc_utdi_in' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_clk' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[0]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[1]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[2]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[3]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[4]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[5]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[6]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[7]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[8]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[9]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[10]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[11]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[12]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[13]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[14]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[15]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[16]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[17]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[18]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[19]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[20]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[21]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[22]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[23]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[24]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[25]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[26]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[27]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[28]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[29]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[30]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[31]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[32]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[33]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[34]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[35]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[36]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[37]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[38]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[39]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[40]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[41]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[42]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[43]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[44]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[45]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[46]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[47]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[48]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[49]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[50]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[51]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[52]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[53]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[54]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[55]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[56]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[57]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[58]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[59]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[60]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[61]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[62]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[63]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[64]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[65]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[66]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[67]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[68]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[69]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[70]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[71]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[72]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[73]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[74]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[75]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[76]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[77]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[78]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[79]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[80]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[81]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[82]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[83]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[84]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[85]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[86]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[87]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[88]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[89]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[90]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[91]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[92]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[93]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[94]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[95]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[96]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[97]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[98]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[99]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[100]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[101]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[102]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[103]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[104]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[105]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[106]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[107]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[108]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[109]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[110]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[111]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[112]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[113]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[114]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[115]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[116]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[117]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[118]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[119]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[120]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[121]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[122]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[123]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[124]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[125]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[126]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[127]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[128]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[129]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[130]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[131]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[132]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[133]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[134]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[135]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[136]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[137]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[138]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[139]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[140]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[141]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[142]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[143]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[144]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[145]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[146]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[147]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[148]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[149]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[150]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[151]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[152]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[153]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[154]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[155]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[156]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[157]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[158]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[159]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[160]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[161]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[162]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[163]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[164]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[165]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[166]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[167]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[168]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[169]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[170]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[171]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[172]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[173]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[174]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[175]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[176]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[177]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[178]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[179]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[180]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[181]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[182]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[183]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[184]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[185]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[186]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[187]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[188]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[189]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[190]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[191]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[192]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[193]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[194]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[195]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[196]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[197]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[198]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[199]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[200]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[201]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[202]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[203]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[204]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[205]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[206]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[207]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[208]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[209]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[210]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[211]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[212]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[213]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[214]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[215]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[216]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[217]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[218]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[219]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[220]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[221]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[222]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[223]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[224]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[225]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[226]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[227]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[228]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[229]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[230]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[231]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[232]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[233]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[234]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[235]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[236]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[237]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[238]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[239]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[240]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[241]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[242]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[243]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[244]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[245]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[246]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[247]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[248]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[249]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[250]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_data_i[251]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_rstn' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[0]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[1]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[2]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[3]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[4]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[5]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[6]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[7]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[8]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[9]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[10]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[11]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[12]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[13]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[14]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[15]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[16]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[17]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[18]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[19]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[20]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[21]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[22]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[23]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[24]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[25]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[26]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[27]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[28]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[29]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[30]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[31]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[32]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[33]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[34]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[35]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[36]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[37]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[38]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[39]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[40]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[41]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[42]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[43]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[44]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[45]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[46]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[47]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[48]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[49]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[50]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[51]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[52]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[53]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[54]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[55]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[56]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[57]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[58]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[59]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[60]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[61]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[62]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[63]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[64]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[65]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[66]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[67]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[68]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[69]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[70]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[71]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[72]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[73]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[74]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[75]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[76]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[77]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[78]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[79]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[80]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[81]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[82]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[83]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[84]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[85]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[86]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[87]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[88]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[89]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[90]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[91]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[92]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[93]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[94]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[95]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[96]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[97]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[98]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[99]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[100]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[101]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[102]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[103]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[104]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[105]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[106]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[107]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[108]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[109]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[110]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[111]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[112]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[113]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[114]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[115]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[116]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[117]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[118]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[119]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[120]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[121]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[122]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[123]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[124]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[125]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[126]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[127]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[128]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[129]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[130]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[131]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[132]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[133]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[134]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[135]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[136]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[137]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[138]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[139]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[140]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[141]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[142]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[143]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[144]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[145]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[146]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[147]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[148]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[149]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[150]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[151]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[152]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[153]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[154]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[155]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[156]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[157]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[158]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[159]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[160]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[161]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[162]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[163]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[164]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[165]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[166]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[167]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[168]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[169]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[170]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[171]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[172]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[173]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[174]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[175]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[176]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[177]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[178]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[179]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[180]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[181]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[182]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[183]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[184]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[185]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[186]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[187]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[188]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[189]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[190]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[191]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[192]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[193]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[194]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[195]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[196]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[197]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[198]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[199]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[200]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[201]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[202]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[203]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[204]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[205]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[206]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[207]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[208]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[209]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[210]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[211]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[212]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[213]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[214]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[215]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[216]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[217]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[218]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[219]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[220]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[221]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[222]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[223]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[224]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[225]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[226]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[227]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[228]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[229]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[230]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[231]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[232]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[233]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[234]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[235]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[236]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[237]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[238]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[239]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[240]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[241]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[242]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[243]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[244]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[245]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[246]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[247]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[248]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[249]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[250]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig0_i[251]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig1_i[0]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig1_i[1]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig1_i[2]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig1_i[3]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig1_i[4]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig1_i[5]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig1_i[6]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig1_i[7]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig2_i[0]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig2_i[1]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig2_i[2]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig2_i[3]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig2_i[4]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig2_i[5]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig2_i[6]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig2_i[7]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig3_i[0]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig3_i[1]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig3_i[2]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig3_i[3]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig3_i[4]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig3_i[5]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig3_i[6]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig3_i[7]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig4_i[0]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig4_i[1]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig4_i[2]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig4_i[3]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig4_i[4]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig4_i[5]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig4_i[6]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig4_i[7]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig5_i[0]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig5_i[1]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig5_i[2]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig5_i[3]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig5_i[4]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig5_i[5]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig5_i[6]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig5_i[7]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig6_i[0]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig6_i[1]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig6_i[2]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig6_i[3]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig6_i[4]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig6_i[5]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig6_i[6]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig6_i[7]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig7_i[0]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig7_i[1]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig7_i[2]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig7_i[3]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig7_i[4]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig7_i[5]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig7_i[6]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig7_i[7]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig8_i[0]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig8_i[1]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig8_i[2]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig8_i[3]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig8_i[4]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig8_i[5]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig8_i[6]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig8_i[7]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig9_i[0]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig9_i[1]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig9_i[2]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig9_i[3]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig9_i[4]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig9_i[5]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig9_i[6]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig9_i[7]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig10_i[0]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig10_i[1]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig10_i[2]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig10_i[3]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig10_i[4]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig10_i[5]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig10_i[6]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig10_i[7]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig11_i[0]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig11_i[1]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig11_i[2]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig11_i[3]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig11_i[4]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig11_i[5]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig11_i[6]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig11_i[7]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig12_i[0]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig12_i[1]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig12_i[2]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig12_i[3]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig12_i[4]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig12_i[5]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig12_i[6]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig12_i[7]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig13_i[0]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig13_i[1]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig13_i[2]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig13_i[3]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig13_i[4]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig13_i[5]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig13_i[6]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig13_i[7]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig14_i[0]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig14_i[1]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig14_i[2]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig14_i[3]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig14_i[4]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig14_i[5]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig14_i[6]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig14_i[7]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig15_i[0]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig15_i[1]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig15_i[2]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig15_i[3]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig15_i[4]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig15_i[5]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig15_i[6]' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_trig15_i[7]' unspecified I/O constraint.
Constraint check end.
Start pre-mapping.
Executing : pre-mapping successfully.
 0.368019s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (101.9%)
Start mod-gen.
W: Public-4008: Instance 'u_larger_than/result_equal_to' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/result_equal_to_16' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/result_larger_than' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/result_larger_than_8h[1:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/result_larger_than_8l' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[15].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[15].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[0].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[0].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[1].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[1].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[2].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[2].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[3].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[3].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[4].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[4].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[5].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[5].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[6].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[6].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[7].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[7].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[8].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[8].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[9].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[9].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[10].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[10].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[11].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[11].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[12].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[12].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[13].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[13].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[14].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[14].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/result_equal_to' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/result_equal_to_16' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/result_larger_than' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/result_larger_than_8h[1:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/result_larger_than_8l' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[15].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[15].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[0].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[0].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[1].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[1].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[2].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[2].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[3].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[3].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[4].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[4].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[5].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[5].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[6].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[6].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[7].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[7].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[8].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[8].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[9].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[9].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[10].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[10].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[11].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[11].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[12].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[12].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[13].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[13].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[14].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[14].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u0_trig_unit/test_reg0' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u0_trig_unit/u_cfg_reg_file/cfg_rdlast' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_Storage_Condition/u_cfg_reg_file/cfg_rdlast' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_Trigger_Condition/u_cfg_reg_file/cfg_rdlast' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
I: Constant propagation done on u_debug_core_0/u_Storage_Condition/N266 (bmsREDOR).
I: Constant propagation done on u_debug_core_0/u_Storage_Condition/N229 (bmsWIDEMUX).
I: Constant propagation done on u_debug_core_0/u_Storage_Condition/N410 (bmsREDAND).
I: Constant propagation done on u_debug_core_0/u0_trig_unit/N14214 (bmsREDAND).
I: Constant propagation done on u_debug_core_0/u0_trig_unit/N14212 (bmsWIDEINV).
I: Constant propagation done on u_debug_core_0/u_Storage_Condition/N397 (bmsREDAND).
I: Constant propagation done on u_debug_core_0/u0_trig_unit/N14213 (bmsREDAND).
I: Removed bmsWIDEDFFCPE inst u_debug_core_0/u0_trig_unit/signal_dly[251:0] that is redundant to u_debug_core_0/TRIG0_ff[1][251:0]
I: Constant propagation done on u_jtag_hub/N0 (bmsWIDEINV).
I: Constant propagation done on u_debug_core_0/u_Storage_Condition/u_cfg_reg_file/N101_bc0 (bmsREDAND).
I: Constant propagation done on u_debug_core_0/u_Storage_Condition/u_cfg_reg_file/N101_sum0 (bmsREDXOR).
Executing : mod-gen successfully.
 1.960159s wall, 1.921875s user + 0.015625s system = 1.937500s CPU (98.8%)
Start logic-optimization.
I: Removed bmsREDAND inst u_debug_core_0/u0_trig_unit/u_cfg_reg_file/ND2[756] that is redundant to u_debug_core_0/u0_trig_unit/u_cfg_reg_file/N363
Executing : logic-optimization successfully.
 14.799461s wall, 14.375000s user + 0.265625s system = 14.640625s CPU (98.9%)
Start tech-mapping phase 1.
W: Public-4008: Instance 'conf_sel[1]' of 'GTP_DFF' unit is dangling and will be cleaned.
W: Public-4008: Instance 'conf_sel[2]' of 'GTP_DFF' unit is dangling and will be cleaned.
W: Public-4008: Instance 'conf_sel[3]' of 'GTP_DFF' unit is dangling and will be cleaned.
W: Public-4008: Instance 'conf_sel[4]' of 'GTP_DFF' unit is dangling and will be cleaned.
W: Public-4008: Instance 'conf_sel[5]' of 'GTP_DFF' unit is dangling and will be cleaned.
W: Public-4008: Instance 'conf_sel[6]' of 'GTP_DFF' unit is dangling and will be cleaned.
W: Public-4008: Instance 'conf_sel[7]' of 'GTP_DFF' unit is dangling and will be cleaned.
W: Public-4008: Instance 'conf_sel[8]' of 'GTP_DFF' unit is dangling and will be cleaned.
W: Public-4008: Instance 'conf_sel[9]' of 'GTP_DFF' unit is dangling and will be cleaned.
W: Public-4008: Instance 'conf_sel[10]' of 'GTP_DFF' unit is dangling and will be cleaned.
W: Public-4008: Instance 'conf_sel[11]' of 'GTP_DFF' unit is dangling and will be cleaned.
W: Public-4008: Instance 'conf_sel[12]' of 'GTP_DFF' unit is dangling and will be cleaned.
W: Public-4008: Instance 'conf_sel[13]' of 'GTP_DFF' unit is dangling and will be cleaned.
W: Public-4008: Instance 'conf_sel[14]' of 'GTP_DFF' unit is dangling and will be cleaned.
W: Public-4008: Instance 'conf_sel[15]' of 'GTP_DFF' unit is dangling and will be cleaned.
Executing : tech-mapping phase 1 successfully.
 0.277902s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (101.2%)
Start tech-mapping phase 2.
