Generated by Fabric Compiler ( version 2020.3 <build 62942> ) at Mon May 30 21:04:31 2022

Timing Constraint:
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create_clock -name {sys_clk} [get_ports {sys_clk}] -period {20} -waveform {0.000 10.000}
create_clock -name {coms_pclk} [get_ports {cmos_pclk}] -period {10.000} -waveform {0.000 5.000}
create_clock -name {DebugCore_JCLK} [get_pins {u_GTP_SCANCHAIN_PG.TCK_USER}] -period {50.000} -waveform {0.000 25.000}
create_clock -name {DebugCore_CAPTURE} [get_pins {u_GTP_SCANCHAIN_PG.CAPDR}] -period {100.000} -waveform {25.000 75.000}
set_clock_groups -name {DebugCoreClockGroup} -asynchronous -group {DebugCore_JCLK DebugCore_CAPTURE}

Inferred clocks commands :
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create_generated_clock  -name {sys_clk|video_pll_m0/u_pll_e1/CLKOUT0_Inferred}  -master_clock {sys_clk}  -source [get_ports {sys_clk}]  -edges {1 2 3}  -edge_shift {0.000000 -2.307692 -4.615385}  [get_pins {video_pll_m0/u_pll_e1.CLKOUT0}]  -add
create_generated_clock  -name {sys_clk|video_pll_m0/u_pll_e1/CLKOUT1_Inferred}  -master_clock {sys_clk}  -source [get_ports {sys_clk}]  -edges {1 2 3}  -edge_shift {0.000000 -8.461538 -16.923077}  [get_pins {video_pll_m0/u_pll_e1.CLKOUT1}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/DQS_CLK_REGIONAL[0]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.DQS_CLK_REGIONAL[0]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/DQS_CLK_REGIONAL[1]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.DQS_CLK_REGIONAL[1]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/DQS_CLK_REGIONAL[2]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.DQS_CLK_REGIONAL[2]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/DQS_CLK_REGIONAL[3]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.DQS_CLK_REGIONAL[3]}]  -add
create_generated_clock  -name {sys_clk|u_ipsl_hmic_h_top/u_pll_50_400/u_pll_e1/CLKOUT3_Inferred}  -master_clock {sys_clk}  -source [get_ports {sys_clk}]  -edges {1 2 3}  -edge_shift {0.000000 -5.000000 -10.000000}  [get_pins {u_ipsl_hmic_h_top/u_pll_50_400/u_pll_e1.CLKOUT3}]  -add
create_generated_clock  -name {sys_clk|u_ipsl_hmic_h_top/u_pll_50_400/u_pll_e1/CLKOUT1_Inferred}  -master_clock {sys_clk}  -source [get_ports {sys_clk}]  -edges {1 2 3}  -edge_shift {0.000000 0.000000 0.000000}  [get_pins {u_ipsl_hmic_h_top/u_pll_50_400/u_pll_e1.CLKOUT1}]  -add
create_generated_clock  -name {sys_clk|u_ipsl_hmic_h_top/u_pll_50_400/u_pll_e1/CLKOUT0_Inferred}  -master_clock {sys_clk}  -source [get_ports {sys_clk}]  -edges {1 2 3}  -edge_shift {0.000000 -8.750000 -17.500000}  [get_pins {u_ipsl_hmic_h_top/u_pll_50_400/u_pll_e1.CLKOUT0}]  -add
create_generated_clock  -name {sys_clk|u_ipsl_hmic_h_top/u_pll_50_400/u_pll_e1/CLKOUT0_Inferred|u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/ioclkdiv_dut/CLKDIVOUT_Inferred}  -master_clock {sys_clk|u_ipsl_hmic_h_top/u_pll_50_400/u_pll_e1/CLKOUT0_Inferred}  -source [get_pins {u_ipsl_hmic_h_top/u_pll_50_400/u_pll_e1.CLKOUT0}]  -edges {1 2 3}  -edge_shift {0.000000 1.250000 2.500000}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/ioclkdiv_dut.CLKDIVOUT}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/DQS_CLK_REGIONAL[4]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.DQS_CLK_REGIONAL[4]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[3]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[3]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/dqs0_dut/DQSI_DELAY_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/dqs0_dut.DQSI_DELAY}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[4]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[4]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[5]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[5]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[6]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[6]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[7]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[7]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[10]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[10]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[11]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[11]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[12]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[12]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[27]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[27]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/dqs2_dut/DQSI_DELAY_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/dqs2_dut.DQSI_DELAY}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[28]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[28]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[29]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[29]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[32]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[32]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[33]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[33]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[34]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[34]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[35]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[35]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[36]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[36]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/dqs0_dut/RCLK_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/dqs0_dut.RCLK}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[2]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[2]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/dqs0_dut/WCLK_DELAY_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/dqs0_dut.WCLK_DELAY}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[9]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[9]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/dqs0_dut/WCLK_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/dqs0_dut.WCLK}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/dqs1_dut/RCLK_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/dqs1_dut.RCLK}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[17]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[17]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/dqs1_dut/WCLK_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/dqs1_dut.WCLK}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[18]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[18]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[19]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[19]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[20]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[20]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[21]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[21]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[22]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[22]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[23]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[23]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[24]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[24]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[25]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[25]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/dqs2_dut/RCLK_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/dqs2_dut.RCLK}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/dqs2_dut/WCLK_DELAY_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/dqs2_dut.WCLK_DELAY}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[31]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[31]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/dqs2_dut/WCLK_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/dqs2_dut.WCLK}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[37]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[37]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/dqs3_dut/RCLK_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/dqs3_dut.RCLK}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[40]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[40]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/dqs3_dut/WCLK_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/dqs3_dut.WCLK}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[41]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[41]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[42]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[42]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[43]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[43]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[44]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[44]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[45]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[45]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[46]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[46]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[47]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[47]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[48]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[48]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[49]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[49]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[51]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[51]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[52]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[52]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/dqs4_dut/RCLK_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/dqs4_dut.RCLK}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[55]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[55]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/dqs4_dut/WCLK_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/dqs4_dut.WCLK}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[56]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[56]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[57]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[57]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[58]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[58]}]  -add
create_clock  -name {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy/IOL_CLK_SYS[59]_Inferred} -period {1000} -waveform { 0 500}  [get_pins {u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy.IOL_CLK_SYS[59]}]  -add


Logical Constraint:
+------------------------------------------------------------------------------+
| Object                                      | Attribute     | Value         
+------------------------------------------------------------------------------+
| u_ipsl_hmic_h_top/u_pll_50_400/u_pll_e1     | PAP_LOC       | PLL_82_71     
+------------------------------------------------------------------------------+

IO Constraint :
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| PORT                   | DIRECTION     | LOC     | VCCIO     | IOSTANDARD     | BUS_KEEPER     | SLEW     | DRIVE     | OFF_CHIP_TERMINATION     | PMOS_FINGER     | NMOS_FINGER     | HYS_DRIVE_MODE     | VREF_MODE     | VREF_MODE_VALUE     | DDR_TERM_MODE     | DIFF_IN_TERM_MODE     | OPEN_DRAIN     | IN_DELAY     | OUT_DELAY     | DIFF_DRV_STRENGTH     | DIFFOUT_EN0     | DIFFOUT_EN1     | CP_IN_MAG     | CP_HYS     | CP_DYN_TERM     | DIFF_DriveStr_0     | DIFF_DriveStr_1     | TX_VCM_0     | TX_VCM_1     | IO_REGISTER     | VIRTUAL_IO     
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| cmos_scl               | inout         | J14     | 3.3       | LVCMOS33       | PULLUP         | FAST     | 4         |                          |                 |                 |                    | NOHYS         |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| cmos_sda               | inout         | J15     | 3.3       | LVCMOS33       | PULLUP         | FAST     | 4         |                          |                 |                 |                    | NOHYS         |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_dq_ch0[0]          | inout         | T8      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_dq_ch0[1]          | inout         | T6      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_dq_ch0[2]          | inout         | R6      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_dq_ch0[3]          | inout         | R9      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_dq_ch0[4]          | inout         | T9      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_dq_ch0[5]          | inout         | N4      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_dq_ch0[6]          | inout         | N5      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_dq_ch0[7]          | inout         | P6      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_dq_ch0[8]          | inout         | T4      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_dq_ch0[9]          | inout         | V9      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_dq_ch0[10]         | inout         | U9      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_dq_ch0[11]         | inout         | V7      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_dq_ch0[12]         | inout         | U7      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_dq_ch0[13]         | inout         | V6      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_dq_ch0[14]         | inout         | U6      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_dq_ch0[15]         | inout         | V5      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_dqs_ch0[0]         | inout         | N6      | 1.5       | SSTL15D_I      | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   | ON                    |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_dqs_ch0[1]         | inout         | U8      | 1.5       | SSTL15D_I      | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   | ON                    |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_dqsn_ch0[0]        | inout         | N7      | 1.5       | SSTL15D_I      | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   | ON                    |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_dqsn_ch0[1]        | inout         | V8      | 1.5       | SSTL15D_I      | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   | ON                    |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| cmos_xclk              | output        | H13     | 3.3       | LVCMOS33       | PULLUP         | FAST     | 4         |                          |                 |                 | OFF                |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_addr_ch0[0]        | output        | M4      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_addr_ch0[1]        | output        | M3      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_addr_ch0[2]        | output        | P2      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_addr_ch0[3]        | output        | P1      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_addr_ch0[4]        | output        | L5      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_addr_ch0[5]        | output        | M5      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_addr_ch0[6]        | output        | N2      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_addr_ch0[7]        | output        | N1      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_addr_ch0[8]        | output        | K4      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_addr_ch0[9]        | output        | M1      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_addr_ch0[10]       | output        | M6      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_addr_ch0[11]       | output        | L1      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_addr_ch0[12]       | output        | K2      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_addr_ch0[13]       | output        | K1      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_addr_ch0[14]       | output        | J2      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_addr_ch0[15]       | output        | J1      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_ba_ch0[0]          | output        | U2      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_ba_ch0[1]          | output        | U1      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_ba_ch0[2]          | output        | T2      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_casn_ch0           | output        | T1      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_cke_ch0            | output        | L4      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_csn_ch0            | output        | R1      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_ddr_clk_w          | output        | U3      | 1.5       | SSTL15D_I      | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_ddr_clkn_w         | output        | V3      | 1.5       | SSTL15D_I      | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_dm_rdqs_ch0[0]     | output        | R8      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_dm_rdqs_ch0[1]     | output        | U5      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_loop_out           | output        | P8      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_loop_out_h         | output        | U4      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_odt_ch0            | output        | V2      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_rasn_ch0           | output        | R2      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_rstn_ch0           | output        | M2      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_wen_ch0            | output        | V1      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| tmds_clk_n             | output        | A16     | 3.3       | LVTTL33        | NONE           | FAST     | 12        |                          |                 |                 | OFF                |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| tmds_clk_p             | output        | B16     | 3.3       | LVTTL33        | NONE           | FAST     | 12        |                          |                 |                 | OFF                |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| tmds_data_n[0]         | output        | A14     | 3.3       | LVTTL33        | NONE           | FAST     | 12        |                          |                 |                 | OFF                |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| tmds_data_n[1]         | output        | A11     | 3.3       | LVTTL33        | NONE           | FAST     | 12        |                          |                 |                 | OFF                |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| tmds_data_n[2]         | output        | A10     | 3.3       | LVTTL33        | NONE           | FAST     | 12        |                          |                 |                 | OFF                |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| tmds_data_p[0]         | output        | B14     | 3.3       | LVTTL33        | NONE           | FAST     | 12        |                          |                 |                 | OFF                |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| tmds_data_p[1]         | output        | B11     | 3.3       | LVTTL33        | NONE           | FAST     | 12        |                          |                 |                 | OFF                |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| tmds_data_p[2]         | output        | B10     | 3.3       | LVTTL33        | NONE           | FAST     | 12        |                          |                 |                 | OFF                |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| uart_tx                | output        | C10     | 3.3       | LVCMOS33       |                | SLOW     | 4         |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| cmos_db[0]             | input         | E18     | 3.3       | LVCMOS33       | PULLUP         |          |           |                          |                 |                 |                    | NOHYS         |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| cmos_db[1]             | input         | D18     | 3.3       | LVCMOS33       | PULLUP         |          |           |                          |                 |                 |                    | NOHYS         |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| cmos_db[2]             | input         | F14     | 3.3       | LVCMOS33       | PULLUP         |          |           |                          |                 |                 |                    | NOHYS         |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| cmos_db[3]             | input         | F13     | 3.3       | LVCMOS33       | PULLUP         |          |           |                          |                 |                 |                    | NOHYS         |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| cmos_db[4]             | input         | E17     | 3.3       | LVCMOS33       | PULLUP         |          |           |                          |                 |                 |                    | NOHYS         |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| cmos_db[5]             | input         | D17     | 3.3       | LVCMOS33       | PULLUP         |          |           |                          |                 |                 |                    | NOHYS         |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| cmos_db[6]             | input         | G14     | 3.3       | LVCMOS33       | PULLUP         |          |           |                          |                 |                 |                    | NOHYS         |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| cmos_db[7]             | input         | G13     | 3.3       | LVCMOS33       | PULLUP         |          |           |                          |                 |                 |                    | NOHYS         |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| cmos_href              | input         | H14     | 3.3       | LVCMOS33       | PULLUP         |          |           |                          |                 |                 |                    | NOHYS         |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| cmos_pclk              | input         | J17     | 3.3       | LVCMOS33       | PULLUP         |          |           |                          |                 |                 |                    | NOHYS         |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| cmos_vsync             | input         | J18     | 3.3       | LVCMOS33       | PULLUP         |          |           |                          |                 |                 |                    | NOHYS         |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| key_in[1]              | input         | V12     | 3.3       | LVTTL33        |                |          |           |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| key_in[2]              | input         | P17     | 3.3       | LVTTL33        |                |          |           |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| key_in[3]              | input         | L12     | 3.3       | LVTTL33        |                |          |           |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_loop_in            | input         | P7      | 1.5       | SSTL15_I       | UNUSED         |          |           |                          |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| pad_loop_in_h          | input         | V4      | 1.5       | SSTL15_I       | UNUSED         |          |           |                          |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| rst_n                  | input         | U12     | 3.3       | LVCMOS33       | PULLUP         |          |           |                          |                 |                 |                    | NOHYS         |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| sys_clk                | input         | B5      | 3.3       | LVCMOS33       | PULLUP         |          |           |                          |                 |                 |                    | NOHYS         |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
| uart_rx                | input         | A12     | 3.3       | LVTTL33        |                |          |           |                          |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                 |               |            |                 |                     |                     |              |              |                 |                
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


Device mapping started.
Optimizing circuit logic.
Checking design netlist.
Processing tech operator.
Clock Signal:
+-----------------------------------------------------------------------------------------------------------------------+
| Driver_Pin_Name     | Clk_Source_Inst                             | Clk_Inst_Name     | Net_Name        | Fanout     
+-----------------------------------------------------------------------------------------------------------------------+
| CAPDR               | u_CORES/u_GTP_SCANCHAIN_PG                  | clkbufg_3         | ntclkbufg_0     | 11         
| CLKOUT1             | u_ipsl_hmic_h_top/u_pll_50_400/u_pll_e1     | clkbufg_4         | ntclkbufg_1     | 180        
| CLKOUT3             | u_ipsl_hmic_h_top/u_pll_50_400/u_pll_e1     | clkbufg_5         | ntclkbufg_2     | 393        
| TCK_USER            | u_CORES/u_GTP_SCANCHAIN_PG                  | clkbufg_6         | ntclkbufg_3     | 880        
+-----------------------------------------------------------------------------------------------------------------------+


Reset Signal:
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Net_Name                                                                                     | Rst_Source_Inst                                                                              | Fanout     
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| I1/BDD/Matrixe_3X3_m0/N0_1                                                                   | I1/BDD/Matrixe_3X3_m0/N0_1                                                                   | 3148       
| I1/N608                                                                                      | I1/N587                                                                                      | 2          
| I1/N609                                                                                      | I1/N588                                                                                      | 1          
| I1/N582                                                                                      | I1/N582                                                                                      | 2          
| I1/N583                                                                                      | I1/N583                                                                                      | 1          
| I1/N572                                                                                      | I1/N572                                                                                      | 2          
| I1/N573                                                                                      | I1/N573                                                                                      | 1          
| I1/N577                                                                                      | I1/N577                                                                                      | 2          
| I1/N578                                                                                      | I1/N578                                                                                      | 1          
| N48_0                                                                                        | N48_0                                                                                        | 31         
| _$$_GND_$$_                                                                                  | _$$_GND_$$_                                                                                  | 117        
| dvi_encoder_m0/serdes_4b_10to1_m0/N100 [4]                                                   | dvi_encoder_m0/serdes_4b_10to1_m0/TMDS_mod5[2]                                               | 3          
| u_CORES/u_debug_core_0/u_Trigger_Condition/u_cfg_reg_file/N21                                | u_CORES/u_debug_core_0/N69                                                                   | 3167       
| u_CORES/u_jtag_hub/N3                                                                        | u_CORES/u_jtag_hub/N3                                                                        | 1          
| I1/BDD/Matrixe_3X3_m0/N0                                                                     | I1/BDD/Matrixe_3X3_m0/N0                                                                     | 1          
| i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/N0                            | i2c_config_m0/i2c_master_top_m0/byte_controller/N12                                          | 95         
| u_CORES/u_debug_core_0/u_rd_addr_gen/N3                                                      | u_CORES/u_debug_core_0/u_hub_data_decode/N0                                                  | 66         
| u_CORES/u_debug_core_0/u_rd_addr_gen/N54                                                     | u_CORES/u_debug_core_0/u_rd_addr_gen/N35_2                                                   | 2          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_ddrc_top/u_ddrc_reset_ctrl_v1_1/N0                           | u_ipsl_hmic_h_top/u_ipsl_hmic_h_ddrc_top/u_ddrc_reset_ctrl_v1_1/N0                           | 138        
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/srb_rst_dll                                          | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_reset_ctrl_v1_1/srb_rst_dll                 | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_rst_dll                         | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy                           | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_dqs_rst [0]                     | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy                           | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_dqs_rst [1]                     | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy                           | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_dqs_rst [2]                     | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy                           | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_dqs_rst [3]                     | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy                           | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_dqs_rst [4]                     | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/u_gtp_ddrphy                           | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/srb_dqs_rstn                                         | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_reset_ctrl_v1_1/srb_dqs_rstn                | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [3]                     | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[3].inv_dut                 | 2          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [4]                     | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[4].inv_dut                 | 2          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [5]                     | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[5].inv_dut                 | 2          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [6]                     | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[6].inv_dut                 | 2          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [7]                     | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[7].inv_dut                 | 2          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [10]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[10].inv_dut                | 2          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [11]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[11].inv_dut                | 2          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [12]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[12].inv_dut                | 2          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [27]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[27].inv_dut                | 2          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [28]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[28].inv_dut                | 2          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [29]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[29].inv_dut                | 2          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [32]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[32].inv_dut                | 2          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [33]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[33].inv_dut                | 2          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [34]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[34].inv_dut                | 2          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [35]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[35].inv_dut                | 2          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [36]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[36].inv_dut                | 2          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [2]                     | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[2].inv_dut                 | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [9]                     | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[9].inv_dut                 | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [17]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[17].inv_dut                | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [18]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[18].inv_dut                | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [19]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[19].inv_dut                | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [20]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[20].inv_dut                | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [21]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[21].inv_dut                | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [22]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[22].inv_dut                | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [23]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[23].inv_dut                | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [24]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[24].inv_dut                | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [25]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[25].inv_dut                | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [31]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[31].inv_dut                | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [37]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[37].inv_dut                | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [40]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[40].inv_dut                | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [41]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[41].inv_dut                | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [42]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[42].inv_dut                | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [43]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[43].inv_dut                | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [44]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[44].inv_dut                | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [45]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[45].inv_dut                | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [46]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[46].inv_dut                | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [47]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[47].inv_dut                | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [48]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[48].inv_dut                | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [49]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[49].inv_dut                | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [51]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[51].inv_dut                | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [52]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[52].inv_dut                | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [55]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[55].inv_dut                | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [56]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[56].inv_dut                | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [57]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[57].inv_dut                | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [58]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[58].inv_dut                | 1          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/buffer_iol_lrs [59]                    | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_phy_io_v1_1/gtp_int_dut[59].inv_dut                | 1          
| I1/BDD/Matrixe_3X3_m0/line_Shift_m0/N39_1                                                    | I1/BDD/Matrixe_3X3_m0/line_Shift_m0/N39_1                                                    | 10         
| I1/BED/Matrixe_3X3_m0/line_Shift_m0/N39_1                                                    | I1/BED/Matrixe_3X3_m0/line_Shift_m0/N39_1                                                    | 10         
| I1/th_BDD_g/Matrixe_3X3_m0/line_Shift_m0/N39                                                 | I1/th_BDD_g/Matrixe_3X3_m0/line_Shift_m0/N39                                                 | 10         
| I1/th_BED_py/Matrixe_3X3_m0/line_Shift_m0/N39                                                | I1/th_BED_y/Matrixe_3X3_m0/line_Shift_m0/N39                                                 | 14         
| frame_read_write_m0/read_fifo_aclr                                                           | frame_read_write_m0/frame_fifo_read_m0/fifo_aclr                                             | 88         
| frame_read_write_m0/write_fifo_aclr                                                          | frame_read_write_m0/frame_fifo_write_m0/fifo_aclr                                            | 83         
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_ddrc_top/u_ddrc_reset_ctrl_v1_1/u_ddrc_apb_reset_v1_1/N0     | u_ipsl_hmic_h_top/u_ipsl_hmic_h_ddrc_top/u_ddrc_reset_ctrl_v1_1/u_ddrc_apb_reset_v1_1/N0     | 10         
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


CE Signal:
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Net_Name                                                                                       | CE_Source_Inst                                                                                           | Fanout     
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| I1/N574                                                                                        | I1/N367_0_5                                                                                              | 8          
| I1/N697                                                                                        | I1/N697_0_7                                                                                              | 6          
| cmos_write_req_gen_m0/N6                                                                       | cmos_write_req_gen_m0/N6                                                                                 | 4          
| i2c_config_m0/_N6                                                                              | i2c_config_m0/N67_2                                                                                      | 10         
| i2c_config_m0/N67                                                                              | i2c_config_m0/N67_9                                                                                      | 4          
| u1/N1509                                                                                       | u1/N1509_0_3                                                                                             | 8          
| u1/N1461                                                                                       | u1/N1461_0_3                                                                                             | 8          
| u1/N1541                                                                                       | u1/N1541_0_3                                                                                             | 8          
| u1/N1557                                                                                       | u1/N1548                                                                                                 | 8          
| u1/N1493                                                                                       | u1/N1493_0_3                                                                                             | 8          
| u1/N1525                                                                                       | u1/N1525_0_3                                                                                             | 8          
| u1/N1569                                                                                       | u1/N1569_13                                                                                              | 56         
| u1/N1632                                                                                       | u1/N1632_7                                                                                               | 56         
| u1/N1637                                                                                       | u1/N1637_3                                                                                               | 5          
| u1/N1449                                                                                       | u1/N1449_2_3                                                                                             | 8          
| u1/N1641                                                                                       | u1/N1641                                                                                                 | 60         
| u1/N1477                                                                                       | u1/N1477_0_3                                                                                             | 8          
| u_aq_axi_master/N444                                                                           | u_aq_axi_master/N444                                                                                     | 32         
| u_aq_axi_master/N512                                                                           | u_aq_axi_master/N512_9                                                                                   | 6          
| u_aq_axi_master/N540                                                                           | u_aq_axi_master/N540                                                                                     | 1          
| u_aq_axi_master/N536                                                                           | u_aq_axi_master/N536                                                                                     | 8          
| u_aq_axi_master/_N23                                                                           | u_aq_axi_master/N519                                                                                     | 29         
| u_aq_axi_master/N507                                                                           | u_aq_axi_master/N507                                                                                     | 2          
| u_aq_axi_master/N587                                                                           | u_aq_axi_master/N512_1                                                                                   | 21         
| u_aq_axi_master/N500                                                                           | u_aq_axi_master/N498                                                                                     | 8          
| u_aq_axi_master/_N14                                                                           | u_aq_axi_master/N467                                                                                     | 29         
| u_aq_axi_master/_N2                                                                            | u_aq_axi_master/N19                                                                                      | 2          
| u_aq_axi_master/N475                                                                           | u_aq_axi_master/N460_4                                                                                   | 21         
| u_aq_axi_master/N460                                                                           | u_aq_axi_master/N460_2_6                                                                                 | 7          
| nt_rst_n                                                                                       | rst_n_ibuf                                                                                               | 3          
| I1/HVcount/N31                                                                                 | I1/HVcount/N31_10                                                                                        | 12         
| I1/VPS/N600                                                                                    | I1/VPS/N600                                                                                              | 4          
| I1/VPS/N608                                                                                    | I1/VPS/N608                                                                                              | 4          
| I1/VPS/N623                                                                                    | I1/VPS/N623                                                                                              | 3          
| I1/VPS/N488                                                                                    | I1/VPS/N488_3                                                                                            | 10         
| I1/VPS/N738                                                                                    | I1/VPS/h_valid                                                                                           | 10         
| I1/VPS/N633                                                                                    | I1/VPS/N633_3                                                                                            | 22         
| I1/VPS/N705                                                                                    | I1/VPS/N705                                                                                              | 4          
| I1/VPS/N700                                                                                    | I1/VPS/N700                                                                                              | 4          
| I1/VPS/N643                                                                                    | I1/VPS/N643                                                                                              | 12         
| I1/VPS/N678                                                                                    | I1/VPS/N678_6                                                                                            | 12         
| I1/VPS/N683                                                                                    | I1/VPS/N683_6                                                                                            | 12         
| I1/VPS/N675                                                                                    | I1/VPS/N675                                                                                              | 12         
| I1/VPS/N627                                                                                    | I1/VPS/N627_4                                                                                            | 5          
| I1/VPS/N612                                                                                    | I1/VPS/N612                                                                                              | 4          
| I1/VPS/N501                                                                                    | I1/VPS/N501_3                                                                                            | 10         
| I1/VPS/N742                                                                                    | I1/VPS/v_valid                                                                                           | 10         
| I1/VPS/N715                                                                                    | I1/VPS/N715                                                                                              | 4          
| I1/VPS/N710                                                                                    | I1/VPS/N710                                                                                              | 4          
| I1/VPS/N688                                                                                    | I1/VPS/N688_6                                                                                            | 12         
| I1/VPS/N693                                                                                    | I1/VPS/N693_6                                                                                            | 12         
| I1/VPS_g/N600                                                                                  | I1/VPS_g/N600                                                                                            | 4          
| I1/VPS_g/N608                                                                                  | I1/VPS_g/N608                                                                                            | 4          
| I1/VPS_g/N623                                                                                  | I1/VPS_g/N623                                                                                            | 3          
| I1/VPS_g/N488                                                                                  | I1/VPS_g/N488_5                                                                                          | 10         
| I1/VPS_g/N738                                                                                  | I1/VPS_g/h_valid                                                                                         | 10         
| I1/VPS_y/N633                                                                                  | I1/VPS_g/N633_5                                                                                          | 88         
| I1/VPS_g/N643                                                                                  | I1/VPS_g/N643                                                                                            | 12         
| I1/VPS_g/N675                                                                                  | I1/VPS_g/N675                                                                                            | 12         
| I1/VPS_g/N627                                                                                  | I1/VPS_g/N627_7                                                                                          | 5          
| I1/VPS_y/N612                                                                                  | I1/VPS_g/N612                                                                                            | 16         
| I1/VPS_g/N501                                                                                  | I1/VPS_g/N501_6                                                                                          | 10         
| I1/VPS_g/N742                                                                                  | I1/VPS_g/v_valid                                                                                         | 10         
| I1/VPS_o/N600                                                                                  | I1/VPS_o/N600                                                                                            | 4          
| I1/VPS_o/N608                                                                                  | I1/VPS_o/N608                                                                                            | 4          
| I1/VPS_o/N488                                                                                  | I1/VPS_o/N488_6                                                                                          | 10         
| I1/VPS_o/N738                                                                                  | I1/VPS_o/h_valid                                                                                         | 10         
| I1/VPS_o/N501                                                                                  | I1/VPS_o/N501_5                                                                                          | 10         
| I1/VPS_o/N742                                                                                  | I1/VPS_o/v_valid                                                                                         | 10         
| I1/VPS_py/N600                                                                                 | I1/VPS_py/N600                                                                                           | 4          
| I1/VPS_py/N608                                                                                 | I1/VPS_py/N608                                                                                           | 4          
| I1/VPS_py/N488                                                                                 | I1/VPS_py/N488_3                                                                                         | 10         
| I1/VPS_py/N738                                                                                 | I1/VPS_py/h_valid                                                                                        | 10         
| I1/VPS_py/N501                                                                                 | I1/VPS_py/N501_5                                                                                         | 10         
| I1/VPS_py/N742                                                                                 | I1/VPS_py/v_valid                                                                                        | 10         
| I1/VPS_y/N600                                                                                  | I1/VPS_y/N600                                                                                            | 4          
| I1/VPS_y/N608                                                                                  | I1/VPS_y/N608                                                                                            | 4          
| I1/VPS_y/N488                                                                                  | I1/VPS_y/N488_5                                                                                          | 10         
| I1/VPS_y/N738                                                                                  | I1/VPS_y/h_valid                                                                                         | 10         
| I1/VPS_y/N501                                                                                  | I1/VPS_y/N501_3                                                                                          | 10         
| I1/VPS_y/N742                                                                                  | I1/VPS_y/v_valid                                                                                         | 10         
| I1/threshold_binary/N590                                                                       | I1/threshold_binary/N590                                                                                 | 20         
| I1/threshold_binary/N593                                                                       | I1/threshold_binary/N593                                                                                 | 20         
| I1/threshold_binary/N597                                                                       | I1/threshold_binary/N597                                                                                 | 20         
| I1/threshold_binary/N585                                                                       | I1/threshold_binary/N585                                                                                 | 20         
| I1/threshold_binary/N588                                                                       | I1/threshold_binary/N588                                                                                 | 20         
| I1/threshold_binary/N599                                                                       | I1/threshold_binary/N599                                                                                 | 20         
| I1/threshold_binary/N582                                                                       | I1/threshold_binary/N582                                                                                 | 20         
| I1/threshold_binary/N635                                                                       | I1/threshold_binary/N265                                                                                 | 4          
| I1/threshold_binary/N595                                                                       | I1/threshold_binary/N595                                                                                 | 20         
| frame_read_write_m0/frame_fifo_read_m0/N182                                                    | frame_read_write_m0/frame_fifo_read_m0/N182_2                                                            | 19         
| frame_read_write_m0/frame_fifo_read_m0/N193                                                    | frame_read_write_m0/frame_fifo_read_m0/N193                                                              | 19         
| frame_read_write_m0/frame_fifo_read_m0/N163                                                    | frame_read_write_m0/frame_fifo_read_m0/N163_1_8                                                          | 7          
| frame_read_write_m0/frame_fifo_read_m0/N211                                                    | frame_read_write_m0/frame_fifo_read_m0/N211                                                              | 16         
| frame_read_write_m0/frame_fifo_write_m0/N147                                                   | frame_read_write_m0/frame_fifo_write_m0/N147_4_6                                                         | 6          
| frame_read_write_m0/frame_fifo_write_m0/N166                                                   | frame_read_write_m0/frame_fifo_write_m0/N166_2                                                           | 19         
| frame_read_write_m0/frame_fifo_write_m0/N177                                                   | frame_read_write_m0/frame_fifo_write_m0/N177                                                             | 19         
| u1/uart_rx_inst/N182                                                                           | u1/uart_rx_inst/N182                                                                                     | 3          
| u1/uart_rx_inst/N60                                                                            | u1/uart_rx_inst/N60                                                                                      | 8          
| u1/uart_tx_inst/N164                                                                           | u1/uart_tx_inst/N164                                                                                     | 3          
| u1/uart_tx_inst/N70                                                                            | u1/uart_tx_inst/N70                                                                                      | 8          
| u_CORES/update_wire                                                                            | u_CORES/u_GTP_SCANCHAIN_PG                                                                               | 1          
| u_CORES/u_jtag_hub/N156                                                                        | u_CORES/u_jtag_hub/N156_0                                                                                | 9          
| video_timing_data_m0/color_bar_m0/N231                                                         | video_timing_data_m0/color_bar_m0/N231_9                                                                 | 12         
| I1/VPS/divede1/_N6                                                                             | I1/VPS/divede1/N107                                                                                      | 19         
| I1/VPS/divede1/N90                                                                             | I1/VPS/divede1/N90                                                                                       | 18         
| I1/VPS/divede1/N125                                                                            | I1/VPS/divede1/N125                                                                                      | 36         
| I1/VPS/divede1/N128                                                                            | I1/VPS/divede1/N128                                                                                      | 10         
| I1/VPS/divede1/N97                                                                             | I1/VPS/divede1/status_0                                                                                  | 21         
| _$$_VCC_$$_                                                                                    | _$$_VCC_$$_                                                                                              | 122        
| I1/VPS_g/divede1/_N6                                                                           | I1/VPS_g/divede1/N107                                                                                    | 19         
| I1/VPS_g/divede1/N90                                                                           | I1/VPS_g/divede1/N90                                                                                     | 18         
| I1/VPS_g/divede1/N125                                                                          | I1/VPS_g/divede1/N125                                                                                    | 36         
| I1/VPS_g/divede1/N128                                                                          | I1/VPS_g/divede1/N128                                                                                    | 10         
| I1/VPS_g/divede1/N97                                                                           | I1/VPS_g/divede1/status_0                                                                                | 21         
| I1/VPS_o/divede1/_N6                                                                           | I1/VPS_o/divede1/N107                                                                                    | 19         
| I1/VPS_o/divede1/N90                                                                           | I1/VPS_o/divede1/N90                                                                                     | 18         
| I1/VPS_o/divede1/N125                                                                          | I1/VPS_o/divede1/N125                                                                                    | 36         
| I1/VPS_o/divede1/N128                                                                          | I1/VPS_o/divede1/N128                                                                                    | 10         
| I1/VPS_o/divede1/N97                                                                           | I1/VPS_o/divede1/status_0                                                                                | 21         
| I1/VPS_py/divede1/_N6                                                                          | I1/VPS_py/divede1/N107                                                                                   | 19         
| I1/VPS_py/divede1/N90                                                                          | I1/VPS_py/divede1/N90                                                                                    | 18         
| I1/VPS_py/divede1/N125                                                                         | I1/VPS_py/divede1/N125                                                                                   | 36         
| I1/VPS_py/divede1/N128                                                                         | I1/VPS_py/divede1/N128                                                                                   | 10         
| I1/VPS_py/divede1/N97                                                                          | I1/VPS_py/divede1/status_0                                                                               | 21         
| I1/VPS_y/divede1/_N6                                                                           | I1/VPS_y/divede1/N107                                                                                    | 19         
| I1/VPS_y/divede1/N90                                                                           | I1/VPS_y/divede1/N90                                                                                     | 18         
| I1/VPS_y/divede1/N125                                                                          | I1/VPS_y/divede1/N125                                                                                    | 36         
| I1/VPS_y/divede1/N128                                                                          | I1/VPS_y/divede1/N128                                                                                    | 10         
| I1/VPS_y/divede1/N97                                                                           | I1/VPS_y/divede1/status_0                                                                                | 21         
| I1/kk/ax_debounce_m0/N65                                                                       | I1/kk/ax_debounce_m0/N61inv                                                                              | 32         
| I1/kk/count10_m0/N24                                                                           | I1/kk/ax_debounce_m0/button_negedge                                                                      | 4          
| I1/temp_de                                                                                     | I1/threshold_binary/de_r                                                                                 | 14         
| I1/tb_dilation_de_py                                                                           | I1/th_BDD_y/per_frame_clken_r[1]                                                                         | 14         
| i2c_config_m0/i2c_master_top_m0/byte_controller/N163                                           | i2c_config_m0/i2c_master_top_m0/byte_controller/N163_12                                                  | 9          
| i2c_config_m0/i2c_master_top_m0/byte_controller/N149                                           | i2c_config_m0/i2c_master_top_m0/byte_controller/N149_1                                                   | 11         
| u_CORES/u_debug_core_0/u0_trig_unit/N14217                                                     | u_CORES/u_debug_core_0/u0_trig_unit/N14217                                                               | 757        
| u_CORES/u_debug_core_0/u_Storage_Condition/N400                                                | u_CORES/u_debug_core_0/u_Storage_Condition/N400                                                          | 12         
| u_CORES/u_debug_core_0/u_Storage_Condition/N408                                                | u_CORES/u_debug_core_0/u_Storage_Condition/N408                                                          | 11         
| u_CORES/u_debug_core_0/u_Storage_Condition/N404                                                | u_CORES/u_debug_core_0/u_Storage_Condition/N404                                                          | 16         
| u_CORES/u_debug_core_0/u_Storage_Condition/N416                                                | u_CORES/u_debug_core_0/u_Storage_Condition/N416_3                                                        | 12         
| u_CORES/u_debug_core_0/u_Trigger_Condition/N114                                                | u_CORES/u_debug_core_0/u_Trigger_Condition/N114                                                          | 3          
| u_CORES/conf_sel [0]                                                                           | u_CORES/u_jtag_hub/conf_sel[0]                                                                           | 5          
| u_CORES/u_debug_core_0/u_hub_data_decode/N357                                                  | u_CORES/u_debug_core_0/u_hub_data_decode/N357                                                            | 5          
| u_CORES/u_debug_core_0/u_rd_addr_gen/N696                                                      | u_CORES/u_debug_core_0/u_rd_addr_gen/N696_3                                                              | 11         
| u_CORES/u_debug_core_0/u_rd_addr_gen/N700                                                      | u_CORES/u_debug_core_0/u_rd_addr_gen/N700                                                                | 12         
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_ddrc_top/u_ddrc_reset_ctrl_v1_1/ddrc_init_done                 | u_ipsl_hmic_h_top/u_ipsl_hmic_h_ddrc_top/u_ddrc_reset_ctrl_v1_1/u_ddrc_apb_reset_v1_1/ddrc_init_done     | 2          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_ddrc_top/u_ddrc_reset_ctrl_v1_1/N110                           | u_ipsl_hmic_h_top/u_ipsl_hmic_h_ddrc_top/u_ddrc_reset_ctrl_v1_1/N110_5                                   | 5          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_ddrc_top/u_ddrc_reset_ctrl_v1_1/N104                           | u_ipsl_hmic_h_top/u_ipsl_hmic_h_ddrc_top/u_ddrc_reset_ctrl_v1_1/N104_5                                   | 2          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_ddrc_top/u_ddrc_reset_ctrl_v1_1/N3                             | u_ipsl_hmic_h_top/u_ipsl_hmic_h_ddrc_top/u_ddrc_reset_ctrl_v1_1/N3_mux3_4                                | 5          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_dll_update_ctrl_v1_1/N77                      | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_dll_update_ctrl_v1_1/N77_8                              | 4          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_reset_ctrl_v1_1/N236                          | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_reset_ctrl_v1_1/N236_1_6                                | 8          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_reset_ctrl_v1_1/N190                          | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_reset_ctrl_v1_1/N190                                    | 2          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_reset_ctrl_v1_1/N244                          | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_reset_ctrl_v1_1/N148_1                                  | 2          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_reset_ctrl_v1_1/N226                          | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_reset_ctrl_v1_1/N226_15                                 | 11         
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_training_ctrl_v1_1/N23                        | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_training_ctrl_v1_1/N23                                  | 3          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_update_ctrl_v1_1/N395 [0]                     | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_update_ctrl_v1_1/N385                                   | 4          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_update_ctrl_v1_1/N394                         | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_update_ctrl_v1_1/N380_1                                 | 2          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_update_ctrl_v1_1/N355                         | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_update_ctrl_v1_1/N355_3                                 | 16         
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_update_ctrl_v1_1/N358                         | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_update_ctrl_v1_1/N358_1                                 | 8          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_update_ctrl_v1_1/N374                         | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_update_ctrl_v1_1/N374                                   | 8          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_update_ctrl_v1_1/N403                         | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_update_ctrl_v1_1/N403                                   | 4          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_update_ctrl_v1_1/N316                         | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_update_ctrl_v1_1/N316_8                                 | 2          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_update_ctrl_v1_1/N368                         | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_update_ctrl_v1_1/N368                                   | 8          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_update_ctrl_v1_1/N310                         | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_update_ctrl_v1_1/N310_8                                 | 2          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_update_ctrl_v1_1/dll_update_pos               | u_ipsl_hmic_h_top/u_ipsl_hmic_h_phy_top/u_ddrphy_update_ctrl_v1_1/N272                                   | 8          
| I1/afbin_de                                                                                    | I1/bin/pre_frame_de_d                                                                                    | 10         
| I1/dilation_de                                                                                 | I1/BDD/per_frame_clken_r[1]                                                                              | 10         
| frame_read_write_m0/read_buf/U_ipml_fifo_afifo_64i_16o_128/U_ipml_fifo_ctrl/N77_1              | frame_read_write_m0/read_buf/U_ipml_fifo_afifo_64i_16o_128/U_ipml_fifo_ctrl/N77_1                        | 11         
| frame_read_write_m0/read_buf/U_ipml_fifo_afifo_64i_16o_128/U_ipml_fifo_ctrl/N0_1               | frame_read_write_m0/read_buf/U_ipml_fifo_afifo_64i_16o_128/U_ipml_fifo_ctrl/N0_1                         | 9          
| read_en                                                                                        | video_timing_data_m0/color_bar_m0/video_active_d0                                                        | 2          
| frame_read_write_m0/write_buf/U_ipml_fifo_afifo_16i_64o_512/U_ipml_fifo_ctrl/N67_1             | frame_read_write_m0/write_buf/U_ipml_fifo_afifo_16i_64o_512/U_ipml_fifo_ctrl/N67_1                       | 9          
| frame_read_write_m0/write_buf/U_ipml_fifo_afifo_16i_64o_512/U_ipml_fifo_ctrl/N0_1              | frame_read_write_m0/write_buf/U_ipml_fifo_afifo_16i_64o_512/U_ipml_fifo_ctrl/N0_1                        | 11         
| wr_burst_data_req                                                                              | u_aq_axi_master/N6                                                                                       | 2          
| i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/N276                            | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/N276                                      | 18         
| i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/N251                            | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/N251                                      | 16         
| i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/N259                            | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/N38inv                                    | 6          
| u1/N927_0                                                                                      | u1/N927_0                                                                                                | 7          
| u1/save_fruit/u_ipm_distributed_fifo_FIFO56x32/N0_1                                            | u1/save_fruit/u_ipm_distributed_fifo_FIFO56x32/N0_1                                                      | 7          
| u_CORES/u_debug_core_0/u0_trig_unit/u_cfg_reg_file/N1392                                       | u_CORES/u_debug_core_0/u0_trig_unit/u_cfg_reg_file/N1392                                                 | 10         
| u_CORES/u_debug_core_0/u_Storage_Condition/u_cfg_reg_file/N212                                 | u_CORES/u_debug_core_0/u_Storage_Condition/u_cfg_reg_file/N212                                           | 4          
| u_CORES/u_debug_core_0/u_Trigger_Condition/u_cfg_reg_file/N145                                 | u_CORES/u_debug_core_0/u_Trigger_Condition/u_cfg_reg_file/N145                                           | 2          
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_ddrc_top/u_ddrc_reset_ctrl_v1_1/u_ddrc_apb_reset_v1_1/N383     | u_ipsl_hmic_h_top/u_ipsl_hmic_h_ddrc_top/u_ddrc_reset_ctrl_v1_1/u_ddrc_apb_reset_v1_1/N383               | 7          
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


Other High Fanout Signal:
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Net_Name                                                                                          | Driver                                                                                           | Fanout     
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| video_clk                                                                                         | video_clkbufg                                                                                    | 7100       
| u_CORES/u_debug_core_0/data_start_d1                                                              | u_CORES/u_debug_core_0/data_start_d1                                                             | 1260       
| ntclkbufg_3                                                                                       | clkbufg_6                                                                                        | 880        
| u_CORES/u_debug_core_0/conf_rst                                                                   | u_CORES/u_debug_core_0/u_hub_data_decode/conf_rst                                                | 787        
| ntclkbufg_2                                                                                       | clkbufg_5                                                                                        | 393        
| I1/th_BED_py/Matrixe_3X3_m0/ycbcr_de_r [0]                                                        | I1/th_BED_y/Matrixe_3X3_m0/ycbcr_de_r[0]                                                         | 257        
| I1/th_BED_py/Matrixe_3X3_m0/ycbcr_hs_r [0]                                                        | I1/th_BED_y/Matrixe_3X3_m0/ycbcr_hs_r[0]                                                         | 257        
| I1/th_BDD_py/Matrixe_3X3_m0/ycbcr_hs_r [0]                                                        | I1/th_BDD_y/Matrixe_3X3_m0/ycbcr_hs_r[0]                                                         | 257        
| I1/th_BDD_py/Matrixe_3X3_m0/ycbcr_de_r [0]                                                        | I1/th_BDD_y/Matrixe_3X3_m0/ycbcr_de_r[0]                                                         | 257        
| u1/save_fruit/u_ipm_distributed_fifo_FIFO56x32/wr_addr [0]                                        | u1/save_fruit/u_ipm_distributed_fifo_FIFO56x32/u_ipm_distributed_fifo_ctr/wptr[0]                | 227        
| u1/save_fruit/u_ipm_distributed_fifo_FIFO56x32/rd_addr [0]                                        | u1/save_fruit/u_ipm_distributed_fifo_FIFO56x32/u_ipm_distributed_fifo_ctr/rptr[0]                | 227        
| u1/save_fruit/u_ipm_distributed_fifo_FIFO56x32/wr_addr [1]                                        | u1/save_fruit/u_ipm_distributed_fifo_FIFO56x32/u_ipm_distributed_fifo_ctr/wptr[1]                | 226        
| u1/save_fruit/u_ipm_distributed_fifo_FIFO56x32/wr_addr [2]                                        | u1/save_fruit/u_ipm_distributed_fifo_FIFO56x32/u_ipm_distributed_fifo_ctr/wptr[2]                | 226        
| u1/save_fruit/u_ipm_distributed_fifo_FIFO56x32/wr_addr [3]                                        | u1/save_fruit/u_ipm_distributed_fifo_FIFO56x32/u_ipm_distributed_fifo_ctr/wptr[3]                | 226        
| u1/save_fruit/u_ipm_distributed_fifo_FIFO56x32/rd_addr [2]                                        | u1/save_fruit/u_ipm_distributed_fifo_FIFO56x32/u_ipm_distributed_fifo_ctr/rptr[2]                | 226        
| u1/save_fruit/u_ipm_distributed_fifo_FIFO56x32/rd_addr [3]                                        | u1/save_fruit/u_ipm_distributed_fifo_FIFO56x32/u_ipm_distributed_fifo_ctr/rptr[3]                | 226        
| u1/save_fruit/u_ipm_distributed_fifo_FIFO56x32/rd_addr [1]                                        | u1/save_fruit/u_ipm_distributed_fifo_FIFO56x32/u_ipm_distributed_fifo_ctr/rptr[1]                | 226        
| u_CORES/u_debug_core_0/u0_trig_unit/u_cfg_reg_file/bit_cnt [0]                                    | u_CORES/u_debug_core_0/u0_trig_unit/u_cfg_reg_file/bit_cnt[0]                                    | 194        
| u_CORES/u_debug_core_0/u0_trig_unit/u_cfg_reg_file/bit_cnt [2]                                    | u_CORES/u_debug_core_0/u0_trig_unit/u_cfg_reg_file/bit_cnt[2]                                    | 193        
| ntclkbufg_1                                                                                       | clkbufg_4                                                                                        | 180        
| u1/save_cnt [0]                                                                                   | u1/save_cnt[0]                                                                                   | 162        
| u1/save_cnt [3]                                                                                   | u1/save_cnt[3]                                                                                   | 149        
| u1/save_cnt [1]                                                                                   | u1/save_cnt[1]                                                                                   | 144        
| sys_clk_g                                                                                         | sys_clkbufg                                                                                      | 131        
| u1/_N9924                                                                                         | u1/N600_42                                                                                       | 126        
| u1/_N9949                                                                                         | u1/N600_67                                                                                       | 108        
| u1/save_cnt [2]                                                                                   | u1/save_cnt[2]                                                                                   | 107        
| u_CORES/u_debug_core_0/u0_trig_unit/u_cfg_reg_file/bit_cnt [1]                                    | u_CORES/u_debug_core_0/u0_trig_unit/u_cfg_reg_file/bit_cnt[1]                                    | 97         
| I1/VPS_y/N631                                                                                     | I1/VPS_g/N140_2                                                                                  | 94         
| I1/TDs/N63                                                                                        | I1/TDs/N63                                                                                       | 90         
| I1/VPS_y/N590                                                                                     | I1/VPS_g/N590_2                                                                                  | 89         
| I1/VPS_y/i [10]                                                                                   | I1/VPS_g/i[10]                                                                                   | 89         
| I1/VPS_y/i [11]                                                                                   | I1/VPS_g/i[11]                                                                                   | 89         
| u1/type7 [44]                                                                                     | u1/type7[5]                                                                                      | 87         
| u1/save_cnt [4]                                                                                   | u1/save_cnt[4]                                                                                   | 86         
| I1/_N5690                                                                                         | I1/VPS_g/N340_mux9_10                                                                            | 85         
| VGA_rgb[23]                                                                                       | I1/disp/rgb_r[0]                                                                                 | 84         
| dvi_encoder_m0/encb/de_reg                                                                        | dvi_encoder_m0/encb/de_reg                                                                       | 75         
| u1/N1296                                                                                          | u1/type4[5]                                                                                      | 74         
| cmos_pclk_g                                                                                       | cmos_pclkbufg                                                                                    | 74         
| u1/type5 [54]                                                                                     | u1/type5[5]                                                                                      | 73         
| u1/_N10634                                                                                        | u1/N651_126                                                                                      | 72         
| u1/_N11312                                                                                        | u1/N704_109                                                                                      | 71         
| u1/_N11294                                                                                        | u1/N704_91_3                                                                                     | 71         
| u1/_N9940                                                                                         | u1/N600_58                                                                                       | 70         
| u_CORES/u_debug_core_0/u_rd_addr_gen/counter [2]                                                  | u_CORES/u_debug_core_0/u_rd_addr_gen/counter[2]                                                  | 69         
| u1/r_r_rd_en                                                                                      | u1/r_r_rd_en                                                                                     | 68         
| u_CORES/u_debug_core_0/u_rd_addr_gen/counter [3]                                                  | u_CORES/u_debug_core_0/u_rd_addr_gen/counter[3]                                                  | 68         
| I1/TDs/N180                                                                                       | I1/TDs/r_frame_cnt[0]                                                                            | 67         
| u_CORES/u_debug_core_0/u_rd_addr_gen/counter [1]                                                  | u_CORES/u_debug_core_0/u_rd_addr_gen/counter[1]                                                  | 67         
| u_CORES/u_debug_core_0/u_rd_addr_gen/counter [6]                                                  | u_CORES/u_debug_core_0/u_rd_addr_gen/counter[6]                                                  | 67         
| u_CORES/u_debug_core_0/u_rd_addr_gen/counter [0]                                                  | u_CORES/u_debug_core_0/u_rd_addr_gen/counter[0]                                                  | 67         
| I1/BED/Matrixe_3X3_m0/ycbcr_hs_r [0]                                                              | I1/BED/Matrixe_3X3_m0/ycbcr_hs_r[0]                                                              | 65         
| I1/BDD/Matrixe_3X3_m0/ycbcr_hs_r [0]                                                              | I1/BDD/Matrixe_3X3_m0/ycbcr_hs_r[0]                                                              | 65         
| I1/BED/Matrixe_3X3_m0/ycbcr_de_r [0]                                                              | I1/BED/Matrixe_3X3_m0/ycbcr_de_r[0]                                                              | 65         
| I1/BDD/Matrixe_3X3_m0/ycbcr_de_r [0]                                                              | I1/BDD/Matrixe_3X3_m0/ycbcr_de_r[0]                                                              | 65         
| u1/wr_en                                                                                          | u1/save_flag                                                                                     | 62         
| u1/type2 [54]                                                                                     | u1/type2[5]                                                                                      | 62         
| u1/_N9906                                                                                         | u1/N600_24                                                                                       | 61         
| u1/_N12592                                                                                        | u1/N806_23                                                                                       | 60         
| u1/type6 [54]                                                                                     | u1/type6[5]                                                                                      | 60         
| u1/type8 [54]                                                                                     | u1/type8[5]                                                                                      | 59         
| u1/save_fruit/u_ipm_distributed_fifo_FIFO56x32/rd_addr [4]                                        | u1/save_fruit/u_ipm_distributed_fifo_FIFO56x32/u_ipm_distributed_fifo_ctr/rptr[4]                | 58         
| video_clk5x                                                                                       | video_clk5xbufg                                                                                  | 57         
| u1/N1259                                                                                          | u1/type3[5]                                                                                      | 57         
| u1/save_fruit/u_ipm_distributed_fifo_FIFO56x32/ipm_distributed_sdpram_FIFO56x32/_N5464            | u1/save_fruit/u_ipm_distributed_fifo_FIFO56x32/ipm_distributed_sdpram_FIFO56x32/mem_1_0_we       | 56         
| u1/save_fruit/u_ipm_distributed_fifo_FIFO56x32/ipm_distributed_sdpram_FIFO56x32/_N5520            | u1/save_fruit/u_ipm_distributed_fifo_FIFO56x32/ipm_distributed_sdpram_FIFO56x32/mem_2_0_we       | 56         
| u1/save_fruit/u_ipm_distributed_fifo_FIFO56x32/ipm_distributed_sdpram_FIFO56x32/_N5408            | u1/save_fruit/u_ipm_distributed_fifo_FIFO56x32/ipm_distributed_sdpram_FIFO56x32/mem_0_0_we       | 56         
| u1/save_fruit/u_ipm_distributed_fifo_FIFO56x32/ipm_distributed_sdpram_FIFO56x32/_N5576            | u1/save_fruit/u_ipm_distributed_fifo_FIFO56x32/ipm_distributed_sdpram_FIFO56x32/mem_3_0_we       | 56         
| u1/save_fruit/u_ipm_distributed_fifo_FIFO56x32/rd_addr [5]                                        | u1/save_fruit/u_ipm_distributed_fifo_FIFO56x32/u_ipm_distributed_fifo_ctr/raddr_msb              | 56         
| I1/r_tds_sc_done_1                                                                                | I1/r_tds_sc_done_1                                                                               | 52         
| u1/type1 [54]                                                                                     | u1/type1[5]                                                                                      | 52         
| u1/_N10599                                                                                        | u1/N651_91_3                                                                                     | 52         
| u1/_N10617                                                                                        | u1/N651_109                                                                                      | 51         
| u_CORES/u_debug_core_0/u0_trig_unit/u_cfg_reg_file/bit_cnt [7]                                    | u_CORES/u_debug_core_0/u0_trig_unit/u_cfg_reg_file/bit_cnt[7]                                    | 50         
| u_aq_axi_master/wr_state_0                                                                        | u_aq_axi_master/wr_state_0                                                                       | 49         
| rd_burst_len[6]                                                                                   | frame_read_write_m0/frame_fifo_read_m0/rd_burst_len[6]                                           | 49         
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_ddrc_top/u_ddrc_reset_ctrl_v1_1/u_ddrc_apb_reset_v1_1/cnt [6]     | u_ipsl_hmic_h_top/u_ipsl_hmic_h_ddrc_top/u_ddrc_reset_ctrl_v1_1/u_ddrc_apb_reset_v1_1/cnt[6]     | 48         
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_ddrc_top/u_ddrc_reset_ctrl_v1_1/u_ddrc_apb_reset_v1_1/cnt [2]     | u_ipsl_hmic_h_top/u_ipsl_hmic_h_ddrc_top/u_ddrc_reset_ctrl_v1_1/u_ddrc_apb_reset_v1_1/cnt[2]     | 47         
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_ddrc_top/u_ddrc_reset_ctrl_v1_1/u_ddrc_apb_reset_v1_1/cnt [1]     | u_ipsl_hmic_h_top/u_ipsl_hmic_h_ddrc_top/u_ddrc_reset_ctrl_v1_1/u_ddrc_apb_reset_v1_1/cnt[1]     | 47         
| I1/VPS/h_nedge_flag                                                                               | I1/VPS/h_nedge_flag                                                                              | 46         
| I1/VPS/v_nedge_flag                                                                               | I1/VPS/v_nedge_flag                                                                              | 46         
| I1/VPS_g/h_nedge_flag                                                                             | I1/VPS_g/h_nedge_flag                                                                            | 46         
| I1/VPS_g/v_nedge_flag                                                                             | I1/VPS_g/v_nedge_flag                                                                            | 46         
| I1/VPS_y/v_nedge_flag                                                                             | I1/VPS_y/v_nedge_flag                                                                            | 46         
| I1/VPS_o/h_nedge_flag                                                                             | I1/VPS_o/h_nedge_flag                                                                            | 46         
| I1/VPS_o/v_nedge_flag                                                                             | I1/VPS_o/v_nedge_flag                                                                            | 46         
| I1/VPS_y/h_nedge_flag                                                                             | I1/VPS_y/h_nedge_flag                                                                            | 46         
| I1/VPS_py/h_nedge_flag                                                                            | I1/VPS_py/h_nedge_flag                                                                           | 46         
| I1/VPS_py/v_nedge_flag                                                                            | I1/VPS_py/v_nedge_flag                                                                           | 46         
| lut_index[0]                                                                                      | i2c_config_m0/lut_index[0]                                                                       | 46         
| lut_index[1]                                                                                      | i2c_config_m0/lut_index[1]                                                                       | 45         
| lut_index[2]                                                                                      | i2c_config_m0/lut_index[2]                                                                       | 45         
| lut_index[7]                                                                                      | i2c_config_m0/lut_index[7]                                                                       | 45         
| lut_index[3]                                                                                      | i2c_config_m0/lut_index[3]                                                                       | 45         
| lut_index[4]                                                                                      | i2c_config_m0/lut_index[4]                                                                       | 45         
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_ddrc_top/u_ddrc_reset_ctrl_v1_1/u_ddrc_apb_reset_v1_1/cnt [5]     | u_ipsl_hmic_h_top/u_ipsl_hmic_h_ddrc_top/u_ddrc_reset_ctrl_v1_1/u_ddrc_apb_reset_v1_1/cnt[5]     | 45         
| lut_index[6]                                                                                      | i2c_config_m0/lut_index[6]                                                                       | 45         
| lut_index[5]                                                                                      | i2c_config_m0/lut_index[5]                                                                       | 45         
| u_ipsl_hmic_h_top/u_ipsl_hmic_h_ddrc_top/u_ddrc_reset_ctrl_v1_1/u_ddrc_apb_reset_v1_1/cnt [0]     | u_ipsl_hmic_h_top/u_ipsl_hmic_h_ddrc_top/u_ddrc_reset_ctrl_v1_1/u_ddrc_apb_reset_v1_1/cnt[0]     | 45         
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


Converting tech operator to gate operator.
Processing gate operator.
Device mapping done.
Total device mapping takes 4.281250 sec.

Device Utilization Summary:
+--------------------------------------------------------------------------+
| Logic Utilization     | Used      | Available     | Utilization(%)     
+--------------------------------------------------------------------------+
| APM                   | 6.5       | 30            | 22                  
| IOCKDLY               | 0         | 24            | 0                   
| FF                    | 8460      | 26304         | 33                  
| LUT                   | 10783     | 17536         | 62                  
| Distributed RAM       | 224       | 4440          | 6                   
| DLL                   | 2         | 6             | 34                  
| DQSL                  | 5         | 18            | 28                  
| DRM                   | 48        | 48            | 100                 
| FUSECODE              | 0         | 1             | 0                   
| IO                    | 83        | 240           | 35                  
| IOCKDIV               | 1         | 12            | 9                   
| IOCKGATE              | 2         | 12            | 17                  
| IPAL                  | 0         | 1             | 0                   
| PLL                   | 2         | 6             | 34                  
| RCKB                  | 0         | 24            | 0                   
| SCANCHAIN             | 1         | 4             | 25                  
| START                 | 0         | 1             | 0                   
| USCM                  | 9         | 20            | 45                  
| HMEMC                 | 1         | 2             | 50                  
| OSC                   | 0         | 1             | 0                   
| ADC                   | 0         | 1             | 0                   
| CRYSTAL               | 0         | 6             | 0                   
| FLSIF                 | 0         | 1             | 0                   
| RESCAL                | 0         | 6             | 0                   
| UDID                  | 0         | 1             | 0                   
+--------------------------------------------------------------------------+

Virtual IO Port Info:
NULL

Inputs and Outputs :
+-------------------------------------------------------------------------------------------------+
| Type       | File Name                                                                         
+-------------------------------------------------------------------------------------------------+
| Input      | D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/synthesize/top_syn.adf     
|            | D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/synthesize/top_syn.fic     
| Output     | D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/top_map.adf     
|            | D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/top_dmr.prt     
|            | D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/top.dmr         
+-------------------------------------------------------------------------------------------------+


Flow Command: dev_map 
Peak memory: 309,219,328 bytes
Total CPU  time to dev_map completion : 8.328 sec
Total real time to dev_map completion : 53.000 sec
