#Generated by Fabric Compiler ( version 2020.3 <build 62942> ) at Mon May 16 22:14:33 2022

add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
add_design "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.v"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp"
add_design "D:/pango/PDS_2020.3/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp"
add_constraint "D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/device_map/ins_rev/cores.fdc"
set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
compile 
synthesize -ads -disable_io_insertion -infer_clock_en false -selected_syn_tool_opt 2 
