# Tue May  7 16:40:49 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03P-Beta2
Install: C:\pango\PDS_2019.1-patch2\syn
OS: Windows 6.1

Hostname: ALINX000007-PC

Implementation : synplify_impl
Synopsys Generic Technology Pre-mapping, Version map2019q1p1, Build 1238R, Built Mar 15 2019 09:38:46


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

Reading constraint file: D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\ddr_324_left.fdc
@L: D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\synthesize\synplify_impl\synplify_scck.rpt 
Printing clock  summary report in "D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\synthesize\synplify_impl\synplify_scck.rpt" file 
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 141MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 141MB)

Adding property PAP_IO_DIRECTION, value "Input", to port sys_clk
Adding property PAP_IO_LOC, value "B5", to port sys_clk
Adding property PAP_IO_VCCIO, value 3.3, to port sys_clk
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port sys_clk
Adding property PAP_IO_PULLUP, value "TRUE", to port sys_clk
Adding property PAP_IO_HYS_DRIVE_MODE, value "NOHYS", to port sys_clk
Adding property PAP_IO_DIRECTION, value "Input", to port rst_n
Adding property PAP_IO_LOC, value "U12", to port rst_n
Adding property PAP_IO_VCCIO, value 3.3, to port rst_n
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port rst_n
Adding property PAP_IO_PULLUP, value "TRUE", to port rst_n
Adding property PAP_IO_HYS_DRIVE_MODE, value "NOHYS", to port rst_n
Adding property PAP_IO_DIRECTION, value "Input", to port key
Adding property PAP_IO_LOC, value "V12", to port key
Adding property PAP_IO_VCCIO, value 3.3, to port key
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port key
Adding property PAP_IO_PULLUP, value "TRUE", to port key
Adding property PAP_IO_HYS_DRIVE_MODE, value "NOHYS", to port key
Adding property PAP_IO_DIRECTION, value "Output", to port led[0]
Adding property PAP_IO_LOC, value "U10", to port led[0]
Adding property PAP_IO_VCCIO, value 3.3, to port led[0]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[0]
Adding property PAP_IO_DRIVE, value 4, to port led[0]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[0]
Adding property PAP_IO_SLEW, value "FAST", to port led[0]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[0]
Adding property PAP_IO_DIRECTION, value "Output", to port led[1]
Adding property PAP_IO_LOC, value "V10", to port led[1]
Adding property PAP_IO_VCCIO, value 3.3, to port led[1]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[1]
Adding property PAP_IO_DRIVE, value 4, to port led[1]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[1]
Adding property PAP_IO_SLEW, value "FAST", to port led[1]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[1]
Adding property PAP_IO_DIRECTION, value "Output", to port led[2]
Adding property PAP_IO_LOC, value "U11", to port led[2]
Adding property PAP_IO_VCCIO, value 3.3, to port led[2]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[2]
Adding property PAP_IO_DRIVE, value 4, to port led[2]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[2]
Adding property PAP_IO_SLEW, value "FAST", to port led[2]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[2]
Adding property PAP_IO_DIRECTION, value "Output", to port led[3]
Adding property PAP_IO_LOC, value "V11", to port led[3]
Adding property PAP_IO_VCCIO, value 3.3, to port led[3]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[3]
Adding property PAP_IO_DRIVE, value 4, to port led[3]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[3]
Adding property PAP_IO_SLEW, value "FAST", to port led[3]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[3]
Adding property PAP_IO_DIRECTION, value "Output", to port sd_ncs
Adding property PAP_IO_LOC, value "V14", to port sd_ncs
Adding property PAP_IO_VCCIO, value 3.3, to port sd_ncs
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port sd_ncs
Adding property PAP_IO_DRIVE, value 4, to port sd_ncs
Adding property PAP_IO_PULLUP, value "TRUE", to port sd_ncs
Adding property PAP_IO_SLEW, value "FAST", to port sd_ncs
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port sd_ncs
Adding property PAP_IO_DIRECTION, value "Output", to port sd_dclk
Adding property PAP_IO_LOC, value "V13", to port sd_dclk
Adding property PAP_IO_VCCIO, value 3.3, to port sd_dclk
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port sd_dclk
Adding property PAP_IO_DRIVE, value 4, to port sd_dclk
Adding property PAP_IO_PULLUP, value "TRUE", to port sd_dclk
Adding property PAP_IO_SLEW, value "FAST", to port sd_dclk
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port sd_dclk
Adding property PAP_IO_DIRECTION, value "Output", to port sd_mosi
Adding property PAP_IO_LOC, value "U14", to port sd_mosi
Adding property PAP_IO_VCCIO, value 3.3, to port sd_mosi
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port sd_mosi
Adding property PAP_IO_DRIVE, value 4, to port sd_mosi
Adding property PAP_IO_PULLUP, value "TRUE", to port sd_mosi
Adding property PAP_IO_SLEW, value "FAST", to port sd_mosi
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port sd_mosi
Adding property PAP_IO_DIRECTION, value "Input", to port sd_miso
Adding property PAP_IO_LOC, value "U13", to port sd_miso
Adding property PAP_IO_VCCIO, value 3.3, to port sd_miso
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port sd_miso
Adding property PAP_IO_PULLUP, value "TRUE", to port sd_miso
Adding property PAP_IO_HYS_DRIVE_MODE, value "NOHYS", to port sd_miso
Adding property PAP_IO_DIRECTION, value "Output", to port clk_led
Adding property PAP_IO_LOC, value "A3", to port clk_led
Adding property PAP_IO_VCCIO, value 3.3, to port clk_led
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port clk_led
Adding property PAP_IO_DRIVE, value 4, to port clk_led
Adding property PAP_IO_PULLUP, value "TRUE", to port clk_led
Adding property PAP_IO_SLEW, value "FAST", to port clk_led
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port clk_led
Adding property PAP_IO_DIRECTION, value "Output", to port pll_lock
Adding property PAP_IO_LOC, value "B4", to port pll_lock
Adding property PAP_IO_VCCIO, value 3.3, to port pll_lock
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port pll_lock
Adding property PAP_IO_DRIVE, value 4, to port pll_lock
Adding property PAP_IO_PULLUP, value "TRUE", to port pll_lock
Adding property PAP_IO_SLEW, value "FAST", to port pll_lock
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port pll_lock
Adding property PAP_IO_DIRECTION, value "Output", to port ddr_init_done
Adding property PAP_IO_LOC, value "B2", to port ddr_init_done
Adding property PAP_IO_VCCIO, value 3.3, to port ddr_init_done
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port ddr_init_done
Adding property PAP_IO_DRIVE, value 4, to port ddr_init_done
Adding property PAP_IO_PULLUP, value "TRUE", to port ddr_init_done
Adding property PAP_IO_SLEW, value "FAST", to port ddr_init_done
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port ddr_init_done
Adding property PAP_IO_DIRECTION, value "Output", to port ddrphy_rst_done
Adding property PAP_IO_LOC, value "A2", to port ddrphy_rst_done
Adding property PAP_IO_VCCIO, value 3.3, to port ddrphy_rst_done
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port ddrphy_rst_done
Adding property PAP_IO_DRIVE, value 4, to port ddrphy_rst_done
Adding property PAP_IO_PULLUP, value "TRUE", to port ddrphy_rst_done
Adding property PAP_IO_SLEW, value "FAST", to port ddrphy_rst_done
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port ddrphy_rst_done
Adding property PAP_IO_DIRECTION, value "Input", to port pad_loop_in
Adding property PAP_IO_LOC, value "P7", to port pad_loop_in
Adding property PAP_IO_VCCIO, value 1.5, to port pad_loop_in
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_loop_in
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_loop_in
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_loop_in
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_loop_in
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_loop_in
Adding property PAP_IO_DIRECTION, value "Input", to port pad_loop_in_h
Adding property PAP_IO_LOC, value "V4", to port pad_loop_in_h
Adding property PAP_IO_VCCIO, value 1.5, to port pad_loop_in_h
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_loop_in_h
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_loop_in_h
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_loop_in_h
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_loop_in_h
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_loop_in_h
Adding property PAP_IO_DIRECTION, value "Output", to port pad_rstn_ch0
Adding property PAP_IO_LOC, value "M2", to port pad_rstn_ch0
Adding property PAP_IO_VCCIO, value 1.5, to port pad_rstn_ch0
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_rstn_ch0
Adding property PAP_IO_DRIVE, value 7.5, to port pad_rstn_ch0
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_rstn_ch0
Adding property PAP_IO_SLEW, value "FAST", to port pad_rstn_ch0
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ddr_clk_w
Adding property PAP_IO_LOC, value "U3", to port pad_ddr_clk_w
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ddr_clk_w
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_ddr_clk_w
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ddr_clk_w
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ddr_clk_w
Adding property PAP_IO_SLEW, value "FAST", to port pad_ddr_clk_w
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ddr_clkn_w
Adding property PAP_IO_LOC, value "V3", to port pad_ddr_clkn_w
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ddr_clkn_w
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_ddr_clkn_w
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ddr_clkn_w
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ddr_clkn_w
Adding property PAP_IO_SLEW, value "FAST", to port pad_ddr_clkn_w
Adding property PAP_IO_DIRECTION, value "Output", to port pad_csn_ch0
Adding property PAP_IO_LOC, value "R1", to port pad_csn_ch0
Adding property PAP_IO_VCCIO, value 1.5, to port pad_csn_ch0
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_csn_ch0
Adding property PAP_IO_DRIVE, value 7.5, to port pad_csn_ch0
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_csn_ch0
Adding property PAP_IO_SLEW, value "FAST", to port pad_csn_ch0
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[0]
Adding property PAP_IO_LOC, value "M4", to port pad_addr_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[10]
Adding property PAP_IO_LOC, value "M6", to port pad_addr_ch0[10]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[10]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[10]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[10]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[10]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[10]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[11]
Adding property PAP_IO_LOC, value "L1", to port pad_addr_ch0[11]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[11]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[11]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[11]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[11]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[11]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[12]
Adding property PAP_IO_LOC, value "K2", to port pad_addr_ch0[12]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[12]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[12]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[12]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[12]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[12]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[13]
Adding property PAP_IO_LOC, value "K1", to port pad_addr_ch0[13]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[13]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[13]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[13]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[13]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[13]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[14]
Adding property PAP_IO_LOC, value "J2", to port pad_addr_ch0[14]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[14]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[14]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[14]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[14]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[14]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[15]
Adding property PAP_IO_LOC, value "J1", to port pad_addr_ch0[15]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[15]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[15]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[15]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[15]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[15]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[1]
Adding property PAP_IO_LOC, value "M3", to port pad_addr_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[2]
Adding property PAP_IO_LOC, value "P2", to port pad_addr_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[2]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[3]
Adding property PAP_IO_LOC, value "P1", to port pad_addr_ch0[3]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[3]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[3]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[3]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[3]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[3]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[4]
Adding property PAP_IO_LOC, value "L5", to port pad_addr_ch0[4]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[4]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[4]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[4]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[4]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[4]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[5]
Adding property PAP_IO_LOC, value "M5", to port pad_addr_ch0[5]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[5]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[5]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[5]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[5]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[5]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[6]
Adding property PAP_IO_LOC, value "N2", to port pad_addr_ch0[6]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[6]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[6]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[6]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[6]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[6]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[7]
Adding property PAP_IO_LOC, value "N1", to port pad_addr_ch0[7]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[7]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[7]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[7]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[7]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[7]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[8]
Adding property PAP_IO_LOC, value "K4", to port pad_addr_ch0[8]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[8]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[8]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[8]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[8]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[8]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[9]
Adding property PAP_IO_LOC, value "M1", to port pad_addr_ch0[9]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[9]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[9]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[9]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[9]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[9]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[0]
Adding property PAP_IO_LOC, value "T8", to port pad_dq_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[0]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[0]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[10]
Adding property PAP_IO_LOC, value "U9", to port pad_dq_ch0[10]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[10]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[10]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[10]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[10]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[10]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[10]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[10]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[10]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[11]
Adding property PAP_IO_LOC, value "V7", to port pad_dq_ch0[11]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[11]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[11]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[11]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[11]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[11]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[11]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[11]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[11]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[12]
Adding property PAP_IO_LOC, value "U7", to port pad_dq_ch0[12]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[12]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[12]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[12]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[12]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[12]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[12]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[12]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[12]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[13]
Adding property PAP_IO_LOC, value "V6", to port pad_dq_ch0[13]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[13]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[13]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[13]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[13]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[13]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[13]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[13]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[13]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[14]
Adding property PAP_IO_LOC, value "U6", to port pad_dq_ch0[14]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[14]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[14]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[14]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[14]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[14]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[14]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[14]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[14]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[15]
Adding property PAP_IO_LOC, value "V5", to port pad_dq_ch0[15]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[15]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[15]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[15]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[15]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[15]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[15]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[15]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[15]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[1]
Adding property PAP_IO_LOC, value "T6", to port pad_dq_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[1]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[1]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[1]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[2]
Adding property PAP_IO_LOC, value "R6", to port pad_dq_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[2]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[2]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[2]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[2]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[3]
Adding property PAP_IO_LOC, value "R9", to port pad_dq_ch0[3]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[3]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[3]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[3]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[3]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[3]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[3]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[3]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[3]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[4]
Adding property PAP_IO_LOC, value "T9", to port pad_dq_ch0[4]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[4]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[4]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[4]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[4]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[4]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[4]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[4]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[4]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[5]
Adding property PAP_IO_LOC, value "N4", to port pad_dq_ch0[5]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[5]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[5]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[5]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[5]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[5]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[5]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[5]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[5]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[6]
Adding property PAP_IO_LOC, value "N5", to port pad_dq_ch0[6]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[6]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[6]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[6]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[6]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[6]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[6]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[6]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[6]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[7]
Adding property PAP_IO_LOC, value "P6", to port pad_dq_ch0[7]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[7]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[7]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[7]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[7]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[7]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[7]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[7]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[7]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[8]
Adding property PAP_IO_LOC, value "T4", to port pad_dq_ch0[8]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[8]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[8]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[8]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[8]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[8]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[8]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[8]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[8]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[9]
Adding property PAP_IO_LOC, value "V9", to port pad_dq_ch0[9]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[9]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[9]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[9]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[9]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[9]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[9]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[9]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[9]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqs_ch0[0]
Adding property PAP_IO_LOC, value "N6", to port pad_dqs_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqs_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqs_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqs_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqs_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqs_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqs_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqs_ch0[1]
Adding property PAP_IO_LOC, value "U8", to port pad_dqs_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqs_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqs_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqs_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqs_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqs_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqs_ch0[1]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqsn_ch0[0]
Adding property PAP_IO_LOC, value "N7", to port pad_dqsn_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqsn_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqsn_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqsn_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqsn_ch0[1]
Adding property PAP_IO_LOC, value "V8", to port pad_dqsn_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqsn_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqsn_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqsn_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_LOC, value "R8", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_LOC, value "U5", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_cke_ch0
Adding property PAP_IO_LOC, value "L4", to port pad_cke_ch0
Adding property PAP_IO_VCCIO, value 1.5, to port pad_cke_ch0
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_cke_ch0
Adding property PAP_IO_DRIVE, value 7.5, to port pad_cke_ch0
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_cke_ch0
Adding property PAP_IO_SLEW, value "FAST", to port pad_cke_ch0
Adding property PAP_IO_DIRECTION, value "Output", to port pad_odt_ch0
Adding property PAP_IO_LOC, value "V2", to port pad_odt_ch0
Adding property PAP_IO_VCCIO, value 1.5, to port pad_odt_ch0
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_odt_ch0
Adding property PAP_IO_DRIVE, value 7.5, to port pad_odt_ch0
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_odt_ch0
Adding property PAP_IO_SLEW, value "FAST", to port pad_odt_ch0
Adding property PAP_IO_DIRECTION, value "Output", to port pad_rasn_ch0
Adding property PAP_IO_LOC, value "R2", to port pad_rasn_ch0
Adding property PAP_IO_VCCIO, value 1.5, to port pad_rasn_ch0
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_rasn_ch0
Adding property PAP_IO_DRIVE, value 7.5, to port pad_rasn_ch0
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_rasn_ch0
Adding property PAP_IO_SLEW, value "FAST", to port pad_rasn_ch0
Adding property PAP_IO_DIRECTION, value "Output", to port pad_casn_ch0
Adding property PAP_IO_LOC, value "T1", to port pad_casn_ch0
Adding property PAP_IO_VCCIO, value 1.5, to port pad_casn_ch0
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_casn_ch0
Adding property PAP_IO_DRIVE, value 7.5, to port pad_casn_ch0
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_casn_ch0
Adding property PAP_IO_SLEW, value "FAST", to port pad_casn_ch0
Adding property PAP_IO_DIRECTION, value "Output", to port pad_wen_ch0
Adding property PAP_IO_LOC, value "V1", to port pad_wen_ch0
Adding property PAP_IO_VCCIO, value 1.5, to port pad_wen_ch0
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_wen_ch0
Adding property PAP_IO_DRIVE, value 7.5, to port pad_wen_ch0
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_wen_ch0
Adding property PAP_IO_SLEW, value "FAST", to port pad_wen_ch0
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[0]
Adding property PAP_IO_LOC, value "U2", to port pad_ba_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[1]
Adding property PAP_IO_LOC, value "U1", to port pad_ba_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[2]
Adding property PAP_IO_LOC, value "T2", to port pad_ba_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[2]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_loop_out
Adding property PAP_IO_LOC, value "P8", to port pad_loop_out
Adding property PAP_IO_VCCIO, value 1.5, to port pad_loop_out
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_loop_out
Adding property PAP_IO_DRIVE, value 7.5, to port pad_loop_out
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_loop_out
Adding property PAP_IO_SLEW, value "FAST", to port pad_loop_out
Adding property PAP_IO_DIRECTION, value "Output", to port pad_loop_out_h
Adding property PAP_IO_LOC, value "U4", to port pad_loop_out_h
Adding property PAP_IO_VCCIO, value 1.5, to port pad_loop_out_h
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_loop_out_h
Adding property PAP_IO_DRIVE, value 7.5, to port pad_loop_out_h
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_loop_out_h
Adding property PAP_IO_SLEW, value "FAST", to port pad_loop_out_h
Adding property PAP_IO_DIRECTION, value "Output", to port err_flag
Adding property PAP_IO_LOC, value "B1", to port err_flag
Adding property PAP_IO_VCCIO, value 3.3, to port err_flag
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port err_flag
Adding property PAP_IO_DRIVE, value 4, to port err_flag
Adding property PAP_IO_PULLUP, value "TRUE", to port err_flag
Adding property PAP_IO_SLEW, value "FAST", to port err_flag
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port err_flag
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_clk_p
Adding property PAP_IO_LOC, value "B16", to port tmds_clk_p
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_clk_p
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_clk_p
Adding property PAP_IO_DRIVE, value 12, to port tmds_clk_p
Adding property PAP_IO_NONE, value "TRUE", to port tmds_clk_p
Adding property PAP_IO_SLEW, value "FAST", to port tmds_clk_p
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_clk_p
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_clk_n
Adding property PAP_IO_LOC, value "A16", to port tmds_clk_n
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_clk_n
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_clk_n
Adding property PAP_IO_DRIVE, value 12, to port tmds_clk_n
Adding property PAP_IO_NONE, value "TRUE", to port tmds_clk_n
Adding property PAP_IO_SLEW, value "FAST", to port tmds_clk_n
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_clk_n
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_p[0]
Adding property PAP_IO_LOC, value "B14", to port tmds_data_p[0]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_p[0]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_p[0]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_p[0]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_p[0]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_p[0]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_p[0]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_p[1]
Adding property PAP_IO_LOC, value "B11", to port tmds_data_p[1]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_p[1]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_p[1]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_p[1]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_p[1]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_p[1]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_p[1]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_p[2]
Adding property PAP_IO_LOC, value "B10", to port tmds_data_p[2]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_p[2]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_p[2]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_p[2]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_p[2]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_p[2]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_p[2]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_n[0]
Adding property PAP_IO_LOC, value "A14", to port tmds_data_n[0]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_n[0]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_n[0]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_n[0]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_n[0]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_n[0]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_n[0]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_n[1]
Adding property PAP_IO_LOC, value "A11", to port tmds_data_n[1]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_n[1]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_n[1]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_n[1]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_n[1]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_n[1]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_n[1]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_n[2]
Adding property PAP_IO_LOC, value "A10", to port tmds_data_n[2]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_n[2]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_n[2]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_n[2]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_n[2]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_n[2]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_n[2]
Adding property PAP_LOC, value "PLL_82_71", to instance u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1

Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)

@N: MO111 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\ipsl_hmemc_top_test.v":42:41:42:48|Tristate driver err_flag (in view: work.ipsl_hmemc_top_test(verilog)) on net err_flag (in view: work.ipsl_hmemc_top_test(verilog)) has its enable tied to GND.
@N: MO111 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":175:41:175:51|Tristate driver DQS_DRIFT_H_1 (in view: work.ipsl_phy_io_Z8(verilog)) on net DQS_DRIFT_H_1 (in view: work.ipsl_phy_io_Z8(verilog)) has its enable tied to GND.
@N: MO111 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":175:41:175:51|Tristate driver DQS_DRIFT_H_2 (in view: work.ipsl_phy_io_Z8(verilog)) on net DQS_DRIFT_H_2 (in view: work.ipsl_phy_io_Z8(verilog)) has its enable tied to GND.
@N: MO111 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":174:41:174:51|Tristate driver DQS_DRIFT_L_1 (in view: work.ipsl_phy_io_Z8(verilog)) on net DQS_DRIFT_L_1 (in view: work.ipsl_phy_io_Z8(verilog)) has its enable tied to GND.
@N: MO111 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":174:41:174:51|Tristate driver DQS_DRIFT_L_2 (in view: work.ipsl_phy_io_Z8(verilog)) on net DQS_DRIFT_L_2 (in view: work.ipsl_phy_io_Z8(verilog)) has its enable tied to GND.
@N: MO111 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":100:41:100:47|Tristate driver PSLVERR (in view: work.ipsl_phy_io_Z8(verilog)) on net PSLVERR (in view: work.ipsl_phy_io_Z8(verilog)) has its enable tied to GND.
@W: MO171 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\encode.v":135:2:135:7|Sequential instance dvi_encoder_m0.encg.c0_q is reduced to a combinational gate by constant propagation. 
@W: MO171 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\encode.v":135:2:135:7|Sequential instance dvi_encoder_m0.encr.c0_q is reduced to a combinational gate by constant propagation. 
@W: MO171 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\encode.v":135:2:135:7|Sequential instance dvi_encoder_m0.encg.c1_q is reduced to a combinational gate by constant propagation. 
@W: MO171 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\encode.v":135:2:135:7|Sequential instance dvi_encoder_m0.encr.c1_q is reduced to a combinational gate by constant propagation. 
@W: FX1172 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\serdes_4b_10to1.v":48:0:48:5|User-specified initial value defined for instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[2:0] is being ignored due to limitations in architecture. 
@W: FX1172 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\serdes_4b_10to1.v":48:0:48:5|User-specified initial value defined for instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_3l[4:0] is being ignored due to limitations in architecture. 
@W: FX1172 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\serdes_4b_10to1.v":48:0:48:5|User-specified initial value defined for instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_3h[4:0] is being ignored due to limitations in architecture. 
@W: FX1172 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\serdes_4b_10to1.v":48:0:48:5|User-specified initial value defined for instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_2l[4:0] is being ignored due to limitations in architecture. 
@W: FX1172 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\serdes_4b_10to1.v":48:0:48:5|User-specified initial value defined for instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_2h[4:0] is being ignored due to limitations in architecture. 
@W: FX1172 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\serdes_4b_10to1.v":48:0:48:5|User-specified initial value defined for instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_1l[4:0] is being ignored due to limitations in architecture. 
@W: FX1172 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\serdes_4b_10to1.v":48:0:48:5|User-specified initial value defined for instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_1h[4:0] is being ignored due to limitations in architecture. 
@W: FX1172 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\serdes_4b_10to1.v":48:0:48:5|User-specified initial value defined for instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_0l[4:0] is being ignored due to limitations in architecture. 
@W: FX1172 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\serdes_4b_10to1.v":48:0:48:5|User-specified initial value defined for instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_0h[4:0] is being ignored due to limitations in architecture. 
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_reset_ctrl.v":141:0:141:5|Removing sequential instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_ddrphy_reset_ctrl.srb_ioclkdiv_rstn because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_ddrphy_reset_ctrl.srb_dqs_rstn. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_reset_ctrl.v":125:0:125:5|Removing sequential instance u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.init_axi_reset2 because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.init_ddrc_rst. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_reset_ctrl.v":125:0:125:5|Removing sequential instance u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.init_axi_reset1 because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.init_ddrc_rst. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_reset_ctrl.v":125:0:125:5|Removing sequential instance u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.init_axi_reset0 because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.init_ddrc_rst. To keep the instance, apply constraint syn_preserve=1 on the instance.
Adding property PAP_IO_DIRECTION, value "Output", to port led[0]
Adding property PAP_IO_LOC, value "U10", to port led[0]
Adding property PAP_IO_VCCIO, value 3.3, to port led[0]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[0]
Adding property PAP_IO_DRIVE, value 4, to port led[0]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[0]
Adding property PAP_IO_SLEW, value "FAST", to port led[0]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[0]
Adding property PAP_IO_DIRECTION, value "Output", to port led[1]
Adding property PAP_IO_LOC, value "V10", to port led[1]
Adding property PAP_IO_VCCIO, value 3.3, to port led[1]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[1]
Adding property PAP_IO_DRIVE, value 4, to port led[1]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[1]
Adding property PAP_IO_SLEW, value "FAST", to port led[1]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[1]
Adding property PAP_IO_DIRECTION, value "Output", to port led[2]
Adding property PAP_IO_LOC, value "U11", to port led[2]
Adding property PAP_IO_VCCIO, value 3.3, to port led[2]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[2]
Adding property PAP_IO_DRIVE, value 4, to port led[2]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[2]
Adding property PAP_IO_SLEW, value "FAST", to port led[2]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[2]
Adding property PAP_IO_DIRECTION, value "Output", to port led[3]
Adding property PAP_IO_LOC, value "V11", to port led[3]
Adding property PAP_IO_VCCIO, value 3.3, to port led[3]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[3]
Adding property PAP_IO_DRIVE, value 4, to port led[3]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[3]
Adding property PAP_IO_SLEW, value "FAST", to port led[3]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[3]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[0]
Adding property PAP_IO_LOC, value "M4", to port pad_addr_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[10]
Adding property PAP_IO_LOC, value "M6", to port pad_addr_ch0[10]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[10]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[10]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[10]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[10]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[10]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[11]
Adding property PAP_IO_LOC, value "L1", to port pad_addr_ch0[11]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[11]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[11]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[11]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[11]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[11]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[12]
Adding property PAP_IO_LOC, value "K2", to port pad_addr_ch0[12]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[12]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[12]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[12]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[12]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[12]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[13]
Adding property PAP_IO_LOC, value "K1", to port pad_addr_ch0[13]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[13]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[13]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[13]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[13]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[13]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[14]
Adding property PAP_IO_LOC, value "J2", to port pad_addr_ch0[14]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[14]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[14]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[14]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[14]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[14]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[15]
Adding property PAP_IO_LOC, value "J1", to port pad_addr_ch0[15]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[15]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[15]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[15]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[15]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[15]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[1]
Adding property PAP_IO_LOC, value "M3", to port pad_addr_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[2]
Adding property PAP_IO_LOC, value "P2", to port pad_addr_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[2]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[3]
Adding property PAP_IO_LOC, value "P1", to port pad_addr_ch0[3]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[3]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[3]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[3]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[3]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[3]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[4]
Adding property PAP_IO_LOC, value "L5", to port pad_addr_ch0[4]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[4]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[4]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[4]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[4]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[4]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[5]
Adding property PAP_IO_LOC, value "M5", to port pad_addr_ch0[5]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[5]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[5]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[5]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[5]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[5]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[6]
Adding property PAP_IO_LOC, value "N2", to port pad_addr_ch0[6]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[6]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[6]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[6]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[6]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[6]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[7]
Adding property PAP_IO_LOC, value "N1", to port pad_addr_ch0[7]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[7]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[7]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[7]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[7]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[7]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[8]
Adding property PAP_IO_LOC, value "K4", to port pad_addr_ch0[8]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[8]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[8]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[8]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[8]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[8]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[9]
Adding property PAP_IO_LOC, value "M1", to port pad_addr_ch0[9]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[9]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[9]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[9]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[9]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[9]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[0]
Adding property PAP_IO_LOC, value "T8", to port pad_dq_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[0]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[0]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[10]
Adding property PAP_IO_LOC, value "U9", to port pad_dq_ch0[10]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[10]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[10]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[10]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[10]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[10]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[10]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[10]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[10]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[11]
Adding property PAP_IO_LOC, value "V7", to port pad_dq_ch0[11]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[11]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[11]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[11]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[11]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[11]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[11]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[11]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[11]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[12]
Adding property PAP_IO_LOC, value "U7", to port pad_dq_ch0[12]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[12]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[12]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[12]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[12]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[12]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[12]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[12]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[12]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[13]
Adding property PAP_IO_LOC, value "V6", to port pad_dq_ch0[13]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[13]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[13]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[13]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[13]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[13]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[13]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[13]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[13]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[14]
Adding property PAP_IO_LOC, value "U6", to port pad_dq_ch0[14]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[14]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[14]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[14]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[14]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[14]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[14]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[14]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[14]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[15]
Adding property PAP_IO_LOC, value "V5", to port pad_dq_ch0[15]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[15]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[15]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[15]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[15]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[15]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[15]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[15]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[15]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[1]
Adding property PAP_IO_LOC, value "T6", to port pad_dq_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[1]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[1]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[1]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[2]
Adding property PAP_IO_LOC, value "R6", to port pad_dq_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[2]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[2]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[2]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[2]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[3]
Adding property PAP_IO_LOC, value "R9", to port pad_dq_ch0[3]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[3]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[3]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[3]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[3]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[3]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[3]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[3]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[3]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[4]
Adding property PAP_IO_LOC, value "T9", to port pad_dq_ch0[4]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[4]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[4]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[4]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[4]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[4]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[4]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[4]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[4]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[5]
Adding property PAP_IO_LOC, value "N4", to port pad_dq_ch0[5]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[5]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[5]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[5]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[5]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[5]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[5]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[5]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[5]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[6]
Adding property PAP_IO_LOC, value "N5", to port pad_dq_ch0[6]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[6]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[6]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[6]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[6]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[6]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[6]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[6]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[6]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[7]
Adding property PAP_IO_LOC, value "P6", to port pad_dq_ch0[7]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[7]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[7]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[7]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[7]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[7]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[7]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[7]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[7]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[8]
Adding property PAP_IO_LOC, value "T4", to port pad_dq_ch0[8]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[8]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[8]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[8]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[8]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[8]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[8]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[8]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[8]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[9]
Adding property PAP_IO_LOC, value "V9", to port pad_dq_ch0[9]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[9]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[9]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[9]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[9]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[9]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[9]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[9]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[9]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqs_ch0[0]
Adding property PAP_IO_LOC, value "N6", to port pad_dqs_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqs_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqs_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqs_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqs_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqs_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqs_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqs_ch0[1]
Adding property PAP_IO_LOC, value "U8", to port pad_dqs_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqs_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqs_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqs_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqs_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqs_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqs_ch0[1]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqsn_ch0[0]
Adding property PAP_IO_LOC, value "N7", to port pad_dqsn_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqsn_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqsn_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqsn_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqsn_ch0[1]
Adding property PAP_IO_LOC, value "V8", to port pad_dqsn_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqsn_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqsn_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqsn_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_LOC, value "R8", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_LOC, value "U5", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[0]
Adding property PAP_IO_LOC, value "U2", to port pad_ba_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[1]
Adding property PAP_IO_LOC, value "U1", to port pad_ba_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[2]
Adding property PAP_IO_LOC, value "T2", to port pad_ba_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[2]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_p[0]
Adding property PAP_IO_LOC, value "B14", to port tmds_data_p[0]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_p[0]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_p[0]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_p[0]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_p[0]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_p[0]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_p[0]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_p[1]
Adding property PAP_IO_LOC, value "B11", to port tmds_data_p[1]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_p[1]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_p[1]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_p[1]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_p[1]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_p[1]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_p[1]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_p[2]
Adding property PAP_IO_LOC, value "B10", to port tmds_data_p[2]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_p[2]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_p[2]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_p[2]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_p[2]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_p[2]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_p[2]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_n[0]
Adding property PAP_IO_LOC, value "A14", to port tmds_data_n[0]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_n[0]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_n[0]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_n[0]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_n[0]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_n[0]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_n[0]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_n[1]
Adding property PAP_IO_LOC, value "A11", to port tmds_data_n[1]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_n[1]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_n[1]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_n[1]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_n[1]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_n[1]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_n[1]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_n[2]
Adding property PAP_IO_LOC, value "A10", to port tmds_data_n[2]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_n[2]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_n[2]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_n[2]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_n[2]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_n[2]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_n[2]
Adding property PAP_IO_DIRECTION, value "Output", to port led[0]
Adding property PAP_IO_LOC, value "U10", to port led[0]
Adding property PAP_IO_VCCIO, value 3.3, to port led[0]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[0]
Adding property PAP_IO_DRIVE, value 4, to port led[0]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[0]
Adding property PAP_IO_SLEW, value "FAST", to port led[0]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[0]
Adding property PAP_IO_DIRECTION, value "Output", to port led[1]
Adding property PAP_IO_LOC, value "V10", to port led[1]
Adding property PAP_IO_VCCIO, value 3.3, to port led[1]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[1]
Adding property PAP_IO_DRIVE, value 4, to port led[1]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[1]
Adding property PAP_IO_SLEW, value "FAST", to port led[1]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[1]
Adding property PAP_IO_DIRECTION, value "Output", to port led[2]
Adding property PAP_IO_LOC, value "U11", to port led[2]
Adding property PAP_IO_VCCIO, value 3.3, to port led[2]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[2]
Adding property PAP_IO_DRIVE, value 4, to port led[2]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[2]
Adding property PAP_IO_SLEW, value "FAST", to port led[2]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[2]
Adding property PAP_IO_DIRECTION, value "Output", to port led[3]
Adding property PAP_IO_LOC, value "V11", to port led[3]
Adding property PAP_IO_VCCIO, value 3.3, to port led[3]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[3]
Adding property PAP_IO_DRIVE, value 4, to port led[3]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[3]
Adding property PAP_IO_SLEW, value "FAST", to port led[3]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[3]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[0]
Adding property PAP_IO_LOC, value "M4", to port pad_addr_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[10]
Adding property PAP_IO_LOC, value "M6", to port pad_addr_ch0[10]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[10]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[10]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[10]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[10]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[10]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[11]
Adding property PAP_IO_LOC, value "L1", to port pad_addr_ch0[11]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[11]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[11]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[11]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[11]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[11]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[12]
Adding property PAP_IO_LOC, value "K2", to port pad_addr_ch0[12]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[12]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[12]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[12]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[12]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[12]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[13]
Adding property PAP_IO_LOC, value "K1", to port pad_addr_ch0[13]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[13]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[13]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[13]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[13]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[13]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[14]
Adding property PAP_IO_LOC, value "J2", to port pad_addr_ch0[14]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[14]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[14]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[14]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[14]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[14]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[15]
Adding property PAP_IO_LOC, value "J1", to port pad_addr_ch0[15]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[15]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[15]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[15]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[15]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[15]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[1]
Adding property PAP_IO_LOC, value "M3", to port pad_addr_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[2]
Adding property PAP_IO_LOC, value "P2", to port pad_addr_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[2]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[3]
Adding property PAP_IO_LOC, value "P1", to port pad_addr_ch0[3]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[3]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[3]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[3]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[3]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[3]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[4]
Adding property PAP_IO_LOC, value "L5", to port pad_addr_ch0[4]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[4]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[4]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[4]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[4]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[4]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[5]
Adding property PAP_IO_LOC, value "M5", to port pad_addr_ch0[5]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[5]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[5]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[5]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[5]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[5]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[6]
Adding property PAP_IO_LOC, value "N2", to port pad_addr_ch0[6]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[6]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[6]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[6]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[6]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[6]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[7]
Adding property PAP_IO_LOC, value "N1", to port pad_addr_ch0[7]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[7]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[7]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[7]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[7]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[7]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[8]
Adding property PAP_IO_LOC, value "K4", to port pad_addr_ch0[8]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[8]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[8]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[8]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[8]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[8]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[9]
Adding property PAP_IO_LOC, value "M1", to port pad_addr_ch0[9]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[9]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[9]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[9]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[9]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[9]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[0]
Adding property PAP_IO_LOC, value "T8", to port pad_dq_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[0]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[0]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[10]
Adding property PAP_IO_LOC, value "U9", to port pad_dq_ch0[10]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[10]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[10]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[10]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[10]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[10]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[10]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[10]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[10]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[11]
Adding property PAP_IO_LOC, value "V7", to port pad_dq_ch0[11]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[11]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[11]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[11]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[11]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[11]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[11]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[11]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[11]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[12]
Adding property PAP_IO_LOC, value "U7", to port pad_dq_ch0[12]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[12]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[12]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[12]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[12]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[12]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[12]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[12]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[12]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[13]
Adding property PAP_IO_LOC, value "V6", to port pad_dq_ch0[13]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[13]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[13]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[13]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[13]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[13]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[13]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[13]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[13]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[14]
Adding property PAP_IO_LOC, value "U6", to port pad_dq_ch0[14]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[14]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[14]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[14]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[14]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[14]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[14]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[14]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[14]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[15]
Adding property PAP_IO_LOC, value "V5", to port pad_dq_ch0[15]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[15]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[15]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[15]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[15]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[15]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[15]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[15]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[15]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[1]
Adding property PAP_IO_LOC, value "T6", to port pad_dq_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[1]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[1]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[1]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[2]
Adding property PAP_IO_LOC, value "R6", to port pad_dq_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[2]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[2]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[2]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[2]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[3]
Adding property PAP_IO_LOC, value "R9", to port pad_dq_ch0[3]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[3]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[3]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[3]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[3]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[3]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[3]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[3]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[3]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[4]
Adding property PAP_IO_LOC, value "T9", to port pad_dq_ch0[4]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[4]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[4]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[4]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[4]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[4]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[4]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[4]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[4]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[5]
Adding property PAP_IO_LOC, value "N4", to port pad_dq_ch0[5]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[5]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[5]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[5]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[5]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[5]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[5]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[5]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[5]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[6]
Adding property PAP_IO_LOC, value "N5", to port pad_dq_ch0[6]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[6]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[6]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[6]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[6]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[6]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[6]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[6]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[6]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[7]
Adding property PAP_IO_LOC, value "P6", to port pad_dq_ch0[7]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[7]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[7]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[7]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[7]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[7]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[7]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[7]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[7]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[8]
Adding property PAP_IO_LOC, value "T4", to port pad_dq_ch0[8]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[8]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[8]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[8]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[8]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[8]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[8]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[8]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[8]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[9]
Adding property PAP_IO_LOC, value "V9", to port pad_dq_ch0[9]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[9]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[9]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[9]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[9]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[9]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[9]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[9]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[9]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqs_ch0[0]
Adding property PAP_IO_LOC, value "N6", to port pad_dqs_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqs_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqs_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqs_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqs_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqs_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqs_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqs_ch0[1]
Adding property PAP_IO_LOC, value "U8", to port pad_dqs_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqs_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqs_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqs_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqs_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqs_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqs_ch0[1]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqsn_ch0[0]
Adding property PAP_IO_LOC, value "N7", to port pad_dqsn_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqsn_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqsn_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqsn_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqsn_ch0[1]
Adding property PAP_IO_LOC, value "V8", to port pad_dqsn_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqsn_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqsn_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqsn_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_LOC, value "R8", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_LOC, value "U5", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[0]
Adding property PAP_IO_LOC, value "U2", to port pad_ba_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[1]
Adding property PAP_IO_LOC, value "U1", to port pad_ba_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[2]
Adding property PAP_IO_LOC, value "T2", to port pad_ba_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[2]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_p[0]
Adding property PAP_IO_LOC, value "B14", to port tmds_data_p[0]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_p[0]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_p[0]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_p[0]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_p[0]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_p[0]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_p[0]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_p[1]
Adding property PAP_IO_LOC, value "B11", to port tmds_data_p[1]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_p[1]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_p[1]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_p[1]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_p[1]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_p[1]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_p[1]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_p[2]
Adding property PAP_IO_LOC, value "B10", to port tmds_data_p[2]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_p[2]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_p[2]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_p[2]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_p[2]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_p[2]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_p[2]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_n[0]
Adding property PAP_IO_LOC, value "A14", to port tmds_data_n[0]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_n[0]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_n[0]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_n[0]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_n[0]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_n[0]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_n[0]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_n[1]
Adding property PAP_IO_LOC, value "A11", to port tmds_data_n[1]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_n[1]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_n[1]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_n[1]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_n[1]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_n[1]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_n[1]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_n[2]
Adding property PAP_IO_LOC, value "A10", to port tmds_data_n[2]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_n[2]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_n[2]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_n[2]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_n[2]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_n[2]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_n[2]
Adding property PAP_IO_DIRECTION, value "Output", to port led[0]
Adding property PAP_IO_LOC, value "U10", to port led[0]
Adding property PAP_IO_VCCIO, value 3.3, to port led[0]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[0]
Adding property PAP_IO_DRIVE, value 4, to port led[0]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[0]
Adding property PAP_IO_SLEW, value "FAST", to port led[0]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[0]
Adding property PAP_IO_DIRECTION, value "Output", to port led[1]
Adding property PAP_IO_LOC, value "V10", to port led[1]
Adding property PAP_IO_VCCIO, value 3.3, to port led[1]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[1]
Adding property PAP_IO_DRIVE, value 4, to port led[1]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[1]
Adding property PAP_IO_SLEW, value "FAST", to port led[1]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[1]
Adding property PAP_IO_DIRECTION, value "Output", to port led[2]
Adding property PAP_IO_LOC, value "U11", to port led[2]
Adding property PAP_IO_VCCIO, value 3.3, to port led[2]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[2]
Adding property PAP_IO_DRIVE, value 4, to port led[2]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[2]
Adding property PAP_IO_SLEW, value "FAST", to port led[2]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[2]
Adding property PAP_IO_DIRECTION, value "Output", to port led[3]
Adding property PAP_IO_LOC, value "V11", to port led[3]
Adding property PAP_IO_VCCIO, value 3.3, to port led[3]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[3]
Adding property PAP_IO_DRIVE, value 4, to port led[3]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[3]
Adding property PAP_IO_SLEW, value "FAST", to port led[3]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[3]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[0]
Adding property PAP_IO_LOC, value "M4", to port pad_addr_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[10]
Adding property PAP_IO_LOC, value "M6", to port pad_addr_ch0[10]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[10]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[10]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[10]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[10]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[10]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[11]
Adding property PAP_IO_LOC, value "L1", to port pad_addr_ch0[11]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[11]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[11]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[11]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[11]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[11]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[12]
Adding property PAP_IO_LOC, value "K2", to port pad_addr_ch0[12]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[12]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[12]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[12]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[12]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[12]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[13]
Adding property PAP_IO_LOC, value "K1", to port pad_addr_ch0[13]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[13]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[13]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[13]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[13]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[13]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[14]
Adding property PAP_IO_LOC, value "J2", to port pad_addr_ch0[14]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[14]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[14]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[14]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[14]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[14]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[15]
Adding property PAP_IO_LOC, value "J1", to port pad_addr_ch0[15]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[15]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[15]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[15]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[15]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[15]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[1]
Adding property PAP_IO_LOC, value "M3", to port pad_addr_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[2]
Adding property PAP_IO_LOC, value "P2", to port pad_addr_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[2]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[3]
Adding property PAP_IO_LOC, value "P1", to port pad_addr_ch0[3]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[3]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[3]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[3]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[3]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[3]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[4]
Adding property PAP_IO_LOC, value "L5", to port pad_addr_ch0[4]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[4]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[4]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[4]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[4]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[4]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[5]
Adding property PAP_IO_LOC, value "M5", to port pad_addr_ch0[5]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[5]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[5]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[5]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[5]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[5]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[6]
Adding property PAP_IO_LOC, value "N2", to port pad_addr_ch0[6]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[6]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[6]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[6]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[6]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[6]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[7]
Adding property PAP_IO_LOC, value "N1", to port pad_addr_ch0[7]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[7]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[7]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[7]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[7]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[7]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[8]
Adding property PAP_IO_LOC, value "K4", to port pad_addr_ch0[8]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[8]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[8]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[8]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[8]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[8]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[9]
Adding property PAP_IO_LOC, value "M1", to port pad_addr_ch0[9]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[9]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[9]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[9]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[9]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[9]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[0]
Adding property PAP_IO_LOC, value "T8", to port pad_dq_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[0]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[0]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[10]
Adding property PAP_IO_LOC, value "U9", to port pad_dq_ch0[10]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[10]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[10]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[10]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[10]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[10]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[10]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[10]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[10]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[11]
Adding property PAP_IO_LOC, value "V7", to port pad_dq_ch0[11]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[11]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[11]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[11]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[11]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[11]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[11]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[11]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[11]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[12]
Adding property PAP_IO_LOC, value "U7", to port pad_dq_ch0[12]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[12]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[12]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[12]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[12]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[12]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[12]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[12]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[12]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[13]
Adding property PAP_IO_LOC, value "V6", to port pad_dq_ch0[13]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[13]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[13]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[13]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[13]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[13]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[13]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[13]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[13]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[14]
Adding property PAP_IO_LOC, value "U6", to port pad_dq_ch0[14]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[14]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[14]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[14]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[14]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[14]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[14]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[14]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[14]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[15]
Adding property PAP_IO_LOC, value "V5", to port pad_dq_ch0[15]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[15]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[15]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[15]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[15]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[15]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[15]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[15]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[15]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[1]
Adding property PAP_IO_LOC, value "T6", to port pad_dq_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[1]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[1]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[1]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[2]
Adding property PAP_IO_LOC, value "R6", to port pad_dq_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[2]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[2]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[2]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[2]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[3]
Adding property PAP_IO_LOC, value "R9", to port pad_dq_ch0[3]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[3]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[3]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[3]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[3]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[3]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[3]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[3]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[3]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[4]
Adding property PAP_IO_LOC, value "T9", to port pad_dq_ch0[4]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[4]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[4]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[4]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[4]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[4]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[4]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[4]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[4]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[5]
Adding property PAP_IO_LOC, value "N4", to port pad_dq_ch0[5]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[5]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[5]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[5]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[5]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[5]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[5]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[5]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[5]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[6]
Adding property PAP_IO_LOC, value "N5", to port pad_dq_ch0[6]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[6]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[6]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[6]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[6]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[6]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[6]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[6]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[6]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[7]
Adding property PAP_IO_LOC, value "P6", to port pad_dq_ch0[7]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[7]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[7]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[7]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[7]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[7]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[7]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[7]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[7]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[8]
Adding property PAP_IO_LOC, value "T4", to port pad_dq_ch0[8]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[8]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[8]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[8]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[8]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[8]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[8]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[8]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[8]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[9]
Adding property PAP_IO_LOC, value "V9", to port pad_dq_ch0[9]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[9]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[9]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[9]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[9]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[9]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[9]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[9]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[9]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqs_ch0[0]
Adding property PAP_IO_LOC, value "N6", to port pad_dqs_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqs_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqs_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqs_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqs_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqs_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqs_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqs_ch0[1]
Adding property PAP_IO_LOC, value "U8", to port pad_dqs_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqs_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqs_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqs_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqs_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqs_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqs_ch0[1]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqsn_ch0[0]
Adding property PAP_IO_LOC, value "N7", to port pad_dqsn_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqsn_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqsn_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqsn_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqsn_ch0[1]
Adding property PAP_IO_LOC, value "V8", to port pad_dqsn_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqsn_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqsn_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqsn_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_LOC, value "R8", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_LOC, value "U5", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[0]
Adding property PAP_IO_LOC, value "U2", to port pad_ba_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[1]
Adding property PAP_IO_LOC, value "U1", to port pad_ba_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[2]
Adding property PAP_IO_LOC, value "T2", to port pad_ba_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[2]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_p[0]
Adding property PAP_IO_LOC, value "B14", to port tmds_data_p[0]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_p[0]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_p[0]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_p[0]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_p[0]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_p[0]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_p[0]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_p[1]
Adding property PAP_IO_LOC, value "B11", to port tmds_data_p[1]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_p[1]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_p[1]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_p[1]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_p[1]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_p[1]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_p[1]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_p[2]
Adding property PAP_IO_LOC, value "B10", to port tmds_data_p[2]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_p[2]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_p[2]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_p[2]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_p[2]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_p[2]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_p[2]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_n[0]
Adding property PAP_IO_LOC, value "A14", to port tmds_data_n[0]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_n[0]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_n[0]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_n[0]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_n[0]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_n[0]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_n[0]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_n[1]
Adding property PAP_IO_LOC, value "A11", to port tmds_data_n[1]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_n[1]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_n[1]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_n[1]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_n[1]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_n[1]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_n[1]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_n[2]
Adding property PAP_IO_LOC, value "A10", to port tmds_data_n[2]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_n[2]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_n[2]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_n[2]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_n[2]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_n[2]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_n[2]
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\ax_debounce.v":100:0:100:5|Removing sequential instance button_posedge (in view: work.ax_debounce(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\color_bar.v":286:0:286:5|Removing sequential instance rgb_r_reg[0] (in view: work.color_bar(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\color_bar.v":286:0:286:5|Removing sequential instance rgb_g_reg[0] (in view: work.color_bar(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\color_bar.v":286:0:286:5|Removing sequential instance rgb_b_reg[0] (in view: work.color_bar(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":349:0:349:5|Removing sequential instance wr_water_level[9:0] (in view: work.ipml_fifo_ctrl_v1_3_9s_8s_ASYN_508s_4s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":370:0:370:5|Removing sequential instance rd_water_level[9:0] (in view: work.ipml_fifo_ctrl_v1_3_8s_9s_ASYN_252s_4s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\color_bar.v":215:0:215:5|Removing sequential instance active_x[11:0] (in view: work.color_bar(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
Adding property PAP_IO_DIRECTION, value "Output", to port led[0]
Adding property PAP_IO_LOC, value "U10", to port led[0]
Adding property PAP_IO_VCCIO, value 3.3, to port led[0]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[0]
Adding property PAP_IO_DRIVE, value 4, to port led[0]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[0]
Adding property PAP_IO_SLEW, value "FAST", to port led[0]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[0]
Adding property PAP_IO_DIRECTION, value "Output", to port led[1]
Adding property PAP_IO_LOC, value "V10", to port led[1]
Adding property PAP_IO_VCCIO, value 3.3, to port led[1]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[1]
Adding property PAP_IO_DRIVE, value 4, to port led[1]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[1]
Adding property PAP_IO_SLEW, value "FAST", to port led[1]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[1]
Adding property PAP_IO_DIRECTION, value "Output", to port led[2]
Adding property PAP_IO_LOC, value "U11", to port led[2]
Adding property PAP_IO_VCCIO, value 3.3, to port led[2]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[2]
Adding property PAP_IO_DRIVE, value 4, to port led[2]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[2]
Adding property PAP_IO_SLEW, value "FAST", to port led[2]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[2]
Adding property PAP_IO_DIRECTION, value "Output", to port led[3]
Adding property PAP_IO_LOC, value "V11", to port led[3]
Adding property PAP_IO_VCCIO, value 3.3, to port led[3]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[3]
Adding property PAP_IO_DRIVE, value 4, to port led[3]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[3]
Adding property PAP_IO_SLEW, value "FAST", to port led[3]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[3]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[0]
Adding property PAP_IO_LOC, value "M4", to port pad_addr_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[10]
Adding property PAP_IO_LOC, value "M6", to port pad_addr_ch0[10]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[10]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[10]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[10]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[10]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[10]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[11]
Adding property PAP_IO_LOC, value "L1", to port pad_addr_ch0[11]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[11]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[11]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[11]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[11]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[11]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[12]
Adding property PAP_IO_LOC, value "K2", to port pad_addr_ch0[12]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[12]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[12]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[12]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[12]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[12]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[13]
Adding property PAP_IO_LOC, value "K1", to port pad_addr_ch0[13]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[13]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[13]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[13]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[13]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[13]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[14]
Adding property PAP_IO_LOC, value "J2", to port pad_addr_ch0[14]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[14]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[14]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[14]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[14]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[14]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[15]
Adding property PAP_IO_LOC, value "J1", to port pad_addr_ch0[15]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[15]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[15]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[15]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[15]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[15]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[1]
Adding property PAP_IO_LOC, value "M3", to port pad_addr_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[2]
Adding property PAP_IO_LOC, value "P2", to port pad_addr_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[2]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[3]
Adding property PAP_IO_LOC, value "P1", to port pad_addr_ch0[3]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[3]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[3]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[3]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[3]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[3]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[4]
Adding property PAP_IO_LOC, value "L5", to port pad_addr_ch0[4]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[4]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[4]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[4]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[4]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[4]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[5]
Adding property PAP_IO_LOC, value "M5", to port pad_addr_ch0[5]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[5]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[5]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[5]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[5]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[5]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[6]
Adding property PAP_IO_LOC, value "N2", to port pad_addr_ch0[6]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[6]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[6]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[6]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[6]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[6]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[7]
Adding property PAP_IO_LOC, value "N1", to port pad_addr_ch0[7]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[7]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[7]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[7]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[7]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[7]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[8]
Adding property PAP_IO_LOC, value "K4", to port pad_addr_ch0[8]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[8]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[8]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[8]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[8]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[8]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[9]
Adding property PAP_IO_LOC, value "M1", to port pad_addr_ch0[9]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[9]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[9]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[9]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[9]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[9]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[0]
Adding property PAP_IO_LOC, value "T8", to port pad_dq_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[0]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[0]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[10]
Adding property PAP_IO_LOC, value "U9", to port pad_dq_ch0[10]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[10]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[10]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[10]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[10]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[10]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[10]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[10]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[10]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[11]
Adding property PAP_IO_LOC, value "V7", to port pad_dq_ch0[11]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[11]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[11]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[11]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[11]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[11]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[11]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[11]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[11]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[12]
Adding property PAP_IO_LOC, value "U7", to port pad_dq_ch0[12]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[12]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[12]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[12]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[12]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[12]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[12]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[12]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[12]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[13]
Adding property PAP_IO_LOC, value "V6", to port pad_dq_ch0[13]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[13]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[13]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[13]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[13]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[13]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[13]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[13]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[13]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[14]
Adding property PAP_IO_LOC, value "U6", to port pad_dq_ch0[14]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[14]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[14]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[14]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[14]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[14]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[14]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[14]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[14]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[15]
Adding property PAP_IO_LOC, value "V5", to port pad_dq_ch0[15]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[15]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[15]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[15]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[15]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[15]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[15]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[15]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[15]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[1]
Adding property PAP_IO_LOC, value "T6", to port pad_dq_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[1]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[1]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[1]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[2]
Adding property PAP_IO_LOC, value "R6", to port pad_dq_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[2]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[2]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[2]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[2]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[3]
Adding property PAP_IO_LOC, value "R9", to port pad_dq_ch0[3]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[3]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[3]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[3]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[3]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[3]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[3]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[3]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[3]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[4]
Adding property PAP_IO_LOC, value "T9", to port pad_dq_ch0[4]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[4]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[4]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[4]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[4]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[4]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[4]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[4]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[4]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[5]
Adding property PAP_IO_LOC, value "N4", to port pad_dq_ch0[5]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[5]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[5]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[5]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[5]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[5]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[5]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[5]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[5]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[6]
Adding property PAP_IO_LOC, value "N5", to port pad_dq_ch0[6]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[6]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[6]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[6]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[6]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[6]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[6]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[6]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[6]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[7]
Adding property PAP_IO_LOC, value "P6", to port pad_dq_ch0[7]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[7]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[7]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[7]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[7]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[7]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[7]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[7]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[7]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[8]
Adding property PAP_IO_LOC, value "T4", to port pad_dq_ch0[8]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[8]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[8]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[8]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[8]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[8]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[8]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[8]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[8]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[9]
Adding property PAP_IO_LOC, value "V9", to port pad_dq_ch0[9]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[9]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[9]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[9]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[9]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[9]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[9]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[9]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[9]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqs_ch0[0]
Adding property PAP_IO_LOC, value "N6", to port pad_dqs_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqs_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqs_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqs_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqs_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqs_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqs_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqs_ch0[1]
Adding property PAP_IO_LOC, value "U8", to port pad_dqs_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqs_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqs_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqs_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqs_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqs_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqs_ch0[1]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqsn_ch0[0]
Adding property PAP_IO_LOC, value "N7", to port pad_dqsn_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqsn_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqsn_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqsn_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqsn_ch0[1]
Adding property PAP_IO_LOC, value "V8", to port pad_dqsn_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqsn_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqsn_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqsn_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_LOC, value "R8", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_LOC, value "U5", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[0]
Adding property PAP_IO_LOC, value "U2", to port pad_ba_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[1]
Adding property PAP_IO_LOC, value "U1", to port pad_ba_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[2]
Adding property PAP_IO_LOC, value "T2", to port pad_ba_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[2]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_p[0]
Adding property PAP_IO_LOC, value "B14", to port tmds_data_p[0]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_p[0]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_p[0]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_p[0]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_p[0]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_p[0]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_p[0]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_p[1]
Adding property PAP_IO_LOC, value "B11", to port tmds_data_p[1]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_p[1]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_p[1]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_p[1]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_p[1]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_p[1]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_p[1]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_p[2]
Adding property PAP_IO_LOC, value "B10", to port tmds_data_p[2]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_p[2]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_p[2]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_p[2]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_p[2]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_p[2]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_p[2]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_n[0]
Adding property PAP_IO_LOC, value "A14", to port tmds_data_n[0]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_n[0]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_n[0]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_n[0]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_n[0]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_n[0]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_n[0]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_n[1]
Adding property PAP_IO_LOC, value "A11", to port tmds_data_n[1]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_n[1]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_n[1]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_n[1]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_n[1]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_n[1]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_n[1]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_n[2]
Adding property PAP_IO_LOC, value "A10", to port tmds_data_n[2]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_n[2]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_n[2]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_n[2]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_n[2]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_n[2]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_n[2]

Encoding state machine state[4:0] (in view: work.bmp_read(verilog))
original code -> new code
   0000 -> 00001
   0001 -> 00010
   0010 -> 00100
   0011 -> 01000
   0100 -> 10000
Encoding state machine state[12:0] (in view: work.sd_card_sec_read_write_Z1(verilog))
original code -> new code
   00000 -> 0000000000001
   00001 -> 0000000000010
   00010 -> 0000000000100
   00011 -> 0000000001000
   00100 -> 0000000010000
   00101 -> 0000000100000
   00110 -> 0000001000000
   00111 -> 0000010000000
   01000 -> 0000100000000
   01111 -> 0001000000000
   10000 -> 0010000000000
   10001 -> 0100000000000
   10010 -> 1000000000000
Encoding state machine state[5:0] (in view: work.spi_master(verilog))
original code -> new code
   000 -> 000001
   001 -> 000010
   010 -> 000100
   011 -> 001000
   100 -> 010000
   101 -> 100000
Encoding state machine state[5:0] (in view: work.frame_fifo_write_Z4(verilog))
original code -> new code
   0000 -> 000001
   0001 -> 000010
   0010 -> 000100
   0011 -> 001000
   0100 -> 010000
   0101 -> 100000
Encoding state machine state[5:0] (in view: work.frame_fifo_read_Z7(verilog))
original code -> new code
   0000 -> 000001
   0001 -> 000010
   0010 -> 000100
   0011 -> 001000
   0100 -> 010000
   0101 -> 100000
Encoding state machine state[10:0] (in view: work.ipsl_ddrphy_reset_ctrl(verilog))
original code -> new code
   0000 -> 00000000001
   0001 -> 00000000010
   0010 -> 00000000100
   0011 -> 00000001000
   0100 -> 00000010000
   0101 -> 00000100000
   0110 -> 00001000000
   0111 -> 00010000000
   1000 -> 00100000000
   1001 -> 01000000000
   1010 -> 10000000000
Encoding state machine state[3:0] (in view: work.ipsl_ddrphy_dll_update_ctrl(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N: MO225 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_dll_update_ctrl.v":36:0:36:5|There are no possible illegal states for state machine state[3:0] (in view: work.ipsl_ddrphy_dll_update_ctrl(verilog)); safe FSM implementation is not required.
Encoding state machine state[1:0] (in view: work.ipsl_ddrphy_update_ctrl_16BIT_2s_0s_1s_2s_3s_1(verilog))
original code -> new code
   00 -> 0
   10 -> 1
@N: MO225 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":293:0:293:5|There are no possible illegal states for state machine state[1:0] (in view: work.ipsl_ddrphy_update_ctrl_16BIT_2s_0s_1s_2s_3s_1(verilog)); safe FSM implementation is not required.
Encoding state machine wr_state[6:0] (in view: work.aq_axi_master(verilog))
original code -> new code
   000 -> 0000001
   001 -> 0000010
   010 -> 0000100
   011 -> 0001000
   100 -> 0010000
   101 -> 0100000
   110 -> 1000000
Encoding state machine rd_state[5:0] (in view: work.aq_axi_master(verilog))
original code -> new code
   000 -> 000001
   001 -> 000010
   010 -> 000100
   011 -> 001000
   100 -> 010000
   101 -> 100000

Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 229MB peak: 229MB)

@N: MF578 |Incompatible asynchronous control logic preventing generated clock conversion.

Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 230MB peak: 230MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 230MB peak: 230MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 231MB peak: 231MB)


Finished netlist restructuring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 231MB peak: 231MB)



Clock Summary
******************

          Start                                                        Requested     Requested     Clock        Clock                    Clock
Level     Clock                                                        Frequency     Period        Type         Group                    Load 
----------------------------------------------------------------------------------------------------------------------------------------------
0 -       sys_clk                                                      50.0 MHz      20.000        declared     default_clkgroup         470  
                                                                                                                                              
0 -       System                                                       1.0 MHz       1000.000      system       system_clkgroup          2    
                                                                                                                                              
0 -       pll_50_400|clkout3_inferred_clock                            1.0 MHz       1000.000      inferred     Inferred_clkgroup_0      549  
                                                                                                                                              
0 -       video_pll|clkout0_inferred_clock                             1.0 MHz       1000.000      inferred     Inferred_clkgroup_71     245  
                                                                                                                                              
0 -       pll_50_400|clkout1_inferred_clock                            1.0 MHz       1000.000      inferred     Inferred_clkgroup_1      148  
                                                                                                                                              
0 -       video_pll|clkout1_inferred_clock                             1.0 MHz       1000.000      inferred     Inferred_clkgroup_72     59   
                                                                                                                                              
0 -       ipsl_phy_io_Z8|ioclk_01_inferred_clock                       1.0 MHz       1000.000      inferred     Inferred_clkgroup_4      19   
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_ca_clk_r_03_inferred_clock                1.0 MHz       1000.000      inferred     Inferred_clkgroup_49     12   
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_clkw_ca_03_inferred_clock                 1.0 MHz       1000.000      inferred     Inferred_clkgroup_51     12   
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs0_clk_r_inferred_clock                     1.0 MHz       1000.000      inferred     Inferred_clkgroup_10     10   
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs1_clk_r_inferred_clock                     1.0 MHz       1000.000      inferred     Inferred_clkgroup_37     10   
                                                                                                                                              
0 -       ipsl_ddrphy_dll_update_ctrl|dll_update_n_inferred_clock      1.0 MHz       1000.000      inferred     Inferred_clkgroup_70     9    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_ca_clk_r_01_inferred_clock                1.0 MHz       1000.000      inferred     Inferred_clkgroup_24     9    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_clkw290_0_inferred_clock                  1.0 MHz       1000.000      inferred     Inferred_clkgroup_12     9    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_clkw290_1_inferred_clock                  1.0 MHz       1000.000      inferred     Inferred_clkgroup_38     9    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_clkw_ca_01_inferred_clock                 1.0 MHz       1000.000      inferred     Inferred_clkgroup_26     9    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_90_0_inferred_clock                       1.0 MHz       1000.000      inferred     Inferred_clkgroup_14     8    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_90_1_inferred_clock                       1.0 MHz       1000.000      inferred     Inferred_clkgroup_36     8    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_ca_clk_r_04_inferred_clock                1.0 MHz       1000.000      inferred     Inferred_clkgroup_63     5    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_clkw_ca_04_inferred_clock                 1.0 MHz       1000.000      inferred     Inferred_clkgroup_65     5    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|IOCLK_DIV_inferred_clock                      1.0 MHz       1000.000      inferred     Inferred_clkgroup_2      2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[3]              1.0 MHz       1000.000      inferred     Inferred_clkgroup_13     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[4]              1.0 MHz       1000.000      inferred     Inferred_clkgroup_15     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[5]              1.0 MHz       1000.000      inferred     Inferred_clkgroup_16     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[6]              1.0 MHz       1000.000      inferred     Inferred_clkgroup_17     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[7]              1.0 MHz       1000.000      inferred     Inferred_clkgroup_18     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[10]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_21     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[11]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_22     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[12]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_23     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[27]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_35     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[28]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_39     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[29]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_40     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[32]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_43     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[33]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_44     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[34]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_45     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[35]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_46     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[36]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_47     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|ioclk_02_inferred_clock                       1.0 MHz       1000.000      inferred     Inferred_clkgroup_8      2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[2]              1.0 MHz       1000.000      inferred     Inferred_clkgroup_11     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[9]              1.0 MHz       1000.000      inferred     Inferred_clkgroup_19     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[17]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_25     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[18]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_27     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[19]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_28     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[20]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_29     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[21]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_30     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[22]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_31     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[23]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_32     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[24]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_33     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[25]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_34     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[31]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_41     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[37]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_48     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[40]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_50     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[41]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_52     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[42]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_53     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[43]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_54     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[44]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_55     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[45]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_56     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[46]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_57     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[47]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_58     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[48]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_59     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[49]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_60     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[51]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_61     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[52]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_62     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[55]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_64     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[56]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_66     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[57]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_67     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[58]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_68     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[59]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_69     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[0]     1.0 MHz       1000.000      inferred     Inferred_clkgroup_3      1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[1]     1.0 MHz       1000.000      inferred     Inferred_clkgroup_5      1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[2]     1.0 MHz       1000.000      inferred     Inferred_clkgroup_6      1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[3]     1.0 MHz       1000.000      inferred     Inferred_clkgroup_7      1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[4]     1.0 MHz       1000.000      inferred     Inferred_clkgroup_9      1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_clkw_0_inferred_clock                     1.0 MHz       1000.000      inferred     Inferred_clkgroup_20     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_clkw_1_inferred_clock                     1.0 MHz       1000.000      inferred     Inferred_clkgroup_42     1    
==============================================================================================================================================



Clock Load Summary
***********************

                                                             Clock     Source                                                                                             Clock Pin                                                                                                 Non-clock Pin                                                                   Non-clock Pin
Clock                                                        Load      Pin                                                                                                Seq Example                                                                                               Seq Example                                                                     Comb Example 
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
sys_clk                                                      470       sys_clk(port)                                                                                      frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wrptr2[8:0].C     -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
System                                                       2         -                                                                                                  u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc.ACLK_2                                                      -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
pll_50_400|clkout3_inferred_clock                            549       u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1.CLKOUT3(GTP_PLL_E1)                                         u_aq_axi_master.reg_r_last.C                                                                              -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
video_pll|clkout0_inferred_clock                             245       video_pll_m0.u_pll_e1.CLKOUT0(GTP_PLL_E1)                                                          frame_read_write_m0.read_buf.U_ipml_fifo_afifo_64i_32o_128.U_ipml_fifo_ctrl.ASYN_CTRL\.rwptr1[8:0].C      -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
pll_50_400|clkout1_inferred_clock                            148       u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1.CLKOUT1(GTP_PLL_E1)                                         u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc.PCLK                                                        -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
video_pll|clkout1_inferred_clock                             59        video_pll_m0.u_pll_e1.CLKOUT1(GTP_PLL_E1)                                                          dvi_encoder_m0.serdes_4b_10to1_m0.gtp_ogddr0.SERCLK                                                       -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|ioclk_01_inferred_clock                       19        u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclkbuf01_dut.CLKOUT(GTP_IOCLKBUF)            u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.CLKA                                         -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_ca_clk_r_03_inferred_clock                12        u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut.RCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr40_dut.SERCLK                                 -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_clkw_ca_03_inferred_clock                 12        u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut.WCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr40_dut.OCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs0_clk_r_inferred_clock                     10        u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.RCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr2_dut.SERCLK                                  -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs1_clk_r_inferred_clock                     10        u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.RCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr27_dut.SERCLK                                 -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_ddrphy_dll_update_ctrl|dll_update_n_inferred_clock      9         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_dll_update_ctrl.dll_update_n.Q[0](dffr)             u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.last_dll_step[7:0].C                           u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DLL_UPDATE_N     -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_ca_clk_r_01_inferred_clock                9         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut.RCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr17_dut.SERCLK                                 -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_clkw290_0_inferred_clock                  9         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.WCLK_DELAY(GTP_DDC_E1)                u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr2_dut.OCLK                                    -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_clkw290_1_inferred_clock                  9         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.WCLK_DELAY(GTP_DDC_E1)                u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr27_dut.OCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_clkw_ca_01_inferred_clock                 9         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut.WCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr17_dut.OCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_90_0_inferred_clock                       8         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.DQSI_DELAY(GTP_DDC_E1)                u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut.ICLK                                    -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_90_1_inferred_clock                       8         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.DQSI_DELAY(GTP_DDC_E1)                u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr27_dut.ICLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_ca_clk_r_04_inferred_clock                5         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut.RCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr55_dut.SERCLK                                 -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_clkw_ca_04_inferred_clock                 5         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut.WCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr55_dut.OCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|IOCLK_DIV_inferred_clock                      2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclkdiv_dut.CLKDIVOUT(GTP_IOCLKDIV)           u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc.CORE_DDRC_CORE_CLK                                          -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[3]              2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[3](GTP_DDRPHY)          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut.RCLK                                    -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[4]              2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[4](GTP_DDRPHY)          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr4_dut.RCLK                                    -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[5]              2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[5](GTP_DDRPHY)          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr5_dut.RCLK                                    -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[6]              2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[6](GTP_DDRPHY)          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr6_dut.RCLK                                    -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[7]              2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[7](GTP_DDRPHY)          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr7_dut.RCLK                                    -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[10]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[10](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr10_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[11]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[11](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr11_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[12]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[12](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr12_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[27]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[27](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr27_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[28]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[28](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr28_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[29]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[29](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr29_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[32]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[32](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr32_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[33]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[33](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr33_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[34]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[34](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr34_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[35]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[35](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr35_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[36]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[36](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr36_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|ioclk_02_inferred_clock                       2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclkbuf02_dut.CLKOUT(GTP_IOCLKBUF)            u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut.CLKA                                         -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[2]              1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[2](GTP_DDRPHY)          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr2_dut.RCLK                                    -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[9]              1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[9](GTP_DDRPHY)          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr9_dut.RCLK                                    -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[17]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[17](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr17_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[18]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[18](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr18_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[19]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[19](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr19_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[20]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[20](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr20_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[21]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[21](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr21_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[22]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[22](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr22_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[23]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[23](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr23_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[24]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[24](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr24_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[25]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[25](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[31]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[31](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr31_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[37]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[37](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[40]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[40](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr40_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[41]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[41](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr41_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[42]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[42](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr42_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[43]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[43](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr43_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[44]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[44](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr44_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[45]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[45](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr45_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[46]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[46](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr46_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[47]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[47](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr47_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[48]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[48](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr48_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[49]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[49](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr49_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[51]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[51](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr51_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[52]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[52](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[55]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[55](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr55_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[56]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[56](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr56_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[57]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[57](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr57_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[58]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[58](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr58_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[59]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[59](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[0]     1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[0](GTP_DDRPHY)     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.CLKB                                         -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[1]     1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[1](GTP_DDRPHY)     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut.CLKB                                         -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[2]     1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[2](GTP_DDRPHY)     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.CLKB                                         -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[3]     1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[3](GTP_DDRPHY)     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut.CLKB                                         -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[4]     1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[4](GTP_DDRPHY)     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut.CLKB                                         -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_clkw_0_inferred_clock                     1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.WCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr9_dut.OCLK                                    -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_clkw_1_inferred_clock                     1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.WCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr31_dut.OCLK                                   -                                                                               -            
=================================================================================================================================================================================================================================================================================================================================================================================

@W: MT531 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_hmemc_ddrc_top.v":337:9:337:14|Found signal identified as System clock which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc.  Using this clock, which has no specified timing constraint, can prevent conversion of gated or generated clocks and can adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_32i_64o_256\rtl\ipml_sdpram_v1_3_afifo_32i_64o_256.v":825:10:825:21|Found inferred clock pll_50_400|clkout3_inferred_clock which controls 549 sequential elements including frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_sdpram.ADDR_LOOP\[0\]\.DATA_LOOP\[1\]\.U_GTP_DRM18K. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_reset_ctrl.v":52:0:52:5|Found inferred clock pll_50_400|clkout1_inferred_clock which controls 148 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_ddrphy_reset_ctrl.state[10]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":960:6:960:15|Found inferred clock ipsl_phy_io_Z8|IOCLK_DIV_inferred_clock which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1134:5:1134:12|Found inferred clock ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[0] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1956:12:1956:25|Found inferred clock ipsl_phy_io_Z8|ioclk_01_inferred_clock which controls 19 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr36_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1171:13:1171:20|Found inferred clock ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[1] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1211:6:1211:13|Found inferred clock ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[2] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1248:13:1248:20|Found inferred clock ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[3] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1285:13:1285:20|Found inferred clock ipsl_phy_io_Z8|ioclk_02_inferred_clock which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1285:13:1285:20|Found inferred clock ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[4] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1597:12:1597:25|Found inferred clock ipsl_phy_io_Z8|dqs0_clk_r_inferred_clock which controls 10 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr12_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1332:12:1332:24|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[2] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr2_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1597:12:1597:25|Found inferred clock ipsl_phy_io_Z8|dqs_clkw290_0_inferred_clock which controls 9 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr12_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1363:12:1363:24|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[3] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr3_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1586:12:1586:25|Found inferred clock ipsl_phy_io_Z8|dqs_90_0_inferred_clock which controls 8 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr12_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1395:12:1395:24|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[4] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr4_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1426:12:1426:24|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[5] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr5_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1458:12:1458:24|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[6] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr6_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1489:12:1489:24|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[7] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr7_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1502:12:1502:24|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[9] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr9_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1502:12:1502:24|Found inferred clock ipsl_phy_io_Z8|dqs_clkw_0_inferred_clock which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr9_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1534:12:1534:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[10] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr10_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1565:12:1565:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[11] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr11_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1597:12:1597:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[12] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr12_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1700:12:1700:25|Found inferred clock ipsl_phy_io_Z8|dqs_ca_clk_r_01_inferred_clock which controls 9 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1609:12:1609:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[17] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr17_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1700:12:1700:25|Found inferred clock ipsl_phy_io_Z8|dqs_clkw_ca_01_inferred_clock which controls 9 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1621:12:1621:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[18] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr18_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1632:12:1632:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[19] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr19_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1644:12:1644:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[20] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr20_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1655:12:1655:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[21] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr21_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1666:12:1666:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[22] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr22_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1677:12:1677:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[23] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr23_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1689:12:1689:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[24] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr24_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1700:12:1700:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[25] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1733:12:1733:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[27] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr27_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1956:12:1956:25|Found inferred clock ipsl_phy_io_Z8|dqs_90_1_inferred_clock which controls 8 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr36_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1978:12:1978:25|Found inferred clock ipsl_phy_io_Z8|dqs1_clk_r_inferred_clock which controls 10 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1978:12:1978:25|Found inferred clock ipsl_phy_io_Z8|dqs_clkw290_1_inferred_clock which controls 9 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1765:12:1765:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[28] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr28_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1796:12:1796:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[29] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr29_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1809:12:1809:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[31] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr31_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1809:12:1809:25|Found inferred clock ipsl_phy_io_Z8|dqs_clkw_1_inferred_clock which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr31_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1841:12:1841:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[32] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr32_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1872:12:1872:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[33] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr33_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1904:12:1904:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[34] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr34_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1935:12:1935:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[35] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr35_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1967:12:1967:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[36] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr36_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1978:12:1978:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[37] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2126:12:2126:25|Found inferred clock ipsl_phy_io_Z8|dqs_ca_clk_r_03_inferred_clock which controls 12 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1993:12:1993:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[40] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr40_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2126:12:2126:25|Found inferred clock ipsl_phy_io_Z8|dqs_clkw_ca_03_inferred_clock which controls 12 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2006:12:2006:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[41] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr41_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2020:12:2020:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[42] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr42_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2031:12:2031:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[43] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr43_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2045:12:2045:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[44] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr44_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2056:12:2056:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[45] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr45_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2068:12:2068:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[46] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr46_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2078:12:2078:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[47] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr47_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2090:12:2090:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[48] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr48_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2101:12:2101:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[49] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr49_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2114:12:2114:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[51] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr51_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2126:12:2126:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[52] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2187:12:2187:25|Found inferred clock ipsl_phy_io_Z8|dqs_ca_clk_r_04_inferred_clock which controls 5 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2140:12:2140:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[55] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr55_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2187:12:2187:25|Found inferred clock ipsl_phy_io_Z8|dqs_clkw_ca_04_inferred_clock which controls 5 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2152:12:2152:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[56] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr56_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2162:12:2162:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[57] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr57_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2174:12:2174:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[58] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr58_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2187:12:2187:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[59] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":54:0:54:5|Found inferred clock ipsl_ddrphy_dll_update_ctrl|dll_update_n_inferred_clock which controls 9 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.last_dll_step[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\encode.v":108:2:108:7|Found inferred clock video_pll|clkout0_inferred_clock which controls 245 sequential elements including dvi_encoder_m0.encb.n0q_m[3:1]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\serdes_4b_10to1.v":48:0:48:5|Found inferred clock video_pll|clkout1_inferred_clock which controls 59 sequential elements including dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[2:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 470 clock pin(s) of sequential element(s)
75 gated/generated clock tree(s) driving 1209 clock pin(s) of sequential element(s)
0 instances converted, 1209 sequential instances remain driven by gated/generated clocks

===================================== Non-Gated/Non-Generated Clocks ======================================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                    
-----------------------------------------------------------------------------------------------------------
@KP:ckid0_143     sys_clk             port                   470        sd_card_bmp_m0.bmp_read_m0.state[4]
===========================================================================================================
======================================================================================================================== Gated/Generated Clocks ========================================================================================================================
Clock Tree ID     Driving Element                                                                        Drive Element Type     Unconverted Fanout     Sample Instance                                                                   Explanation                    
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
@KP:ckid0_0       u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1.CLKOUT3                                         GTP_PLL_E1             549                    u_aq_axi_master.rd_state[5]                                                       Black box on clock path        
@KP:ckid0_2       u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1.CLKOUT1                                         GTP_PLL_E1             148                    u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                                     Black box on clock path        
@KP:ckid0_3       u_ipsl_hmemc_top.aclk_0.O[0]                                                           variable               1                      u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                                     Black box on clock path        
@KP:ckid0_4       u_ipsl_hmemc_top.aclk_2.O[0]                                                           variable               1                      u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                                     Black box on clock path        
@KP:ckid0_6       u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclkdiv_dut.CLKDIVOUT             GTP_IOCLKDIV           2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut                    Black box on clock path        
@KP:ckid0_7       u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut.WCLK                      GTP_DDC_E1             5                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut                Clock source is invalid for GCC
@KP:ckid0_9       u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[59]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut                Clock source is invalid for GCC
@KP:ckid0_11      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut.RCLK                      GTP_DDC_E1             5                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut                Clock source is invalid for GCC
@KP:ckid0_13      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[58]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr58_dut                Clock source is invalid for GCC
@KP:ckid0_15      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[57]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr57_dut                Clock source is invalid for GCC
@KP:ckid0_17      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[56]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr56_dut                Clock source is invalid for GCC
@KP:ckid0_19      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[55]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr55_dut                Clock source is invalid for GCC
@KP:ckid0_21      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut.WCLK                      GTP_DDC_E1             12                     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut                Clock source is invalid for GCC
@KP:ckid0_23      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[52]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut                Clock source is invalid for GCC
@KP:ckid0_25      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut.RCLK                      GTP_DDC_E1             12                     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut                Clock source is invalid for GCC
@KP:ckid0_27      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[51]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr51_dut                Clock source is invalid for GCC
@KP:ckid0_29      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[49]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr49_dut                Clock source is invalid for GCC
@KP:ckid0_31      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[48]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr48_dut                Clock source is invalid for GCC
@KP:ckid0_33      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[47]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr47_dut                Clock source is invalid for GCC
@KP:ckid0_35      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[46]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr46_dut                Clock source is invalid for GCC
@KP:ckid0_37      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[45]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr45_dut                Clock source is invalid for GCC
@KP:ckid0_39      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[44]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr44_dut                Clock source is invalid for GCC
@KP:ckid0_41      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[43]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr43_dut                Clock source is invalid for GCC
@KP:ckid0_43      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[42]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr42_dut                Clock source is invalid for GCC
@KP:ckid0_45      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[41]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr41_dut                Clock source is invalid for GCC
@KP:ckid0_47      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[40]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr40_dut                Clock source is invalid for GCC
@KP:ckid0_49      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.WCLK_DELAY                GTP_DDC_E1             9                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut                Clock source is invalid for GCC
@KP:ckid0_51      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[37]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut                Clock source is invalid for GCC
@KP:ckid0_53      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.RCLK                      GTP_DDC_E1             10                     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut                Clock source is invalid for GCC
@KP:ckid0_55      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[36]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr36_dut                Clock source is invalid for GCC
@KP:ckid0_57      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclkbuf01_dut.CLKOUT              GTP_IOCLKBUF           19                     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr36_dut                Black box on clock path        
@KP:ckid0_58      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.DQSI_DELAY                GTP_DDC_E1             8                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr36_dut                Black box on clock path        
@KP:ckid0_60      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[35]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr35_dut                Clock source is invalid for GCC
@KP:ckid0_62      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[34]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr34_dut                Clock source is invalid for GCC
@KP:ckid0_64      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[33]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr33_dut                Clock source is invalid for GCC
@KP:ckid0_66      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[32]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr32_dut                Clock source is invalid for GCC
@KP:ckid0_68      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.WCLK                      GTP_DDC_E1             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr31_dut                Clock source is invalid for GCC
@KP:ckid0_70      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[31]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr31_dut                Clock source is invalid for GCC
@KP:ckid0_72      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[29]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr29_dut                Clock source is invalid for GCC
@KP:ckid0_74      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[28]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr28_dut                Clock source is invalid for GCC
@KP:ckid0_76      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[27]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr27_dut                Clock source is invalid for GCC
@KP:ckid0_78      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut.WCLK                      GTP_DDC_E1             9                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut                Clock source is invalid for GCC
@KP:ckid0_80      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[25]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut                Clock source is invalid for GCC
@KP:ckid0_82      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut.RCLK                      GTP_DDC_E1             9                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut                Clock source is invalid for GCC
@KP:ckid0_84      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[24]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr24_dut                Clock source is invalid for GCC
@KP:ckid0_86      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[23]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr23_dut                Clock source is invalid for GCC
@KP:ckid0_88      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[22]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr22_dut                Clock source is invalid for GCC
@KP:ckid0_90      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[21]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr21_dut                Clock source is invalid for GCC
@KP:ckid0_92      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[20]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr20_dut                Clock source is invalid for GCC
@KP:ckid0_94      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[19]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr19_dut                Clock source is invalid for GCC
@KP:ckid0_96      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[18]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr18_dut                Clock source is invalid for GCC
@KP:ckid0_98      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[17]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr17_dut                Clock source is invalid for GCC
@KP:ckid0_100     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.WCLK_DELAY                GTP_DDC_E1             9                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr12_dut                Clock source is invalid for GCC
@KP:ckid0_102     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[12]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr12_dut                Clock source is invalid for GCC
@KP:ckid0_104     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.RCLK                      GTP_DDC_E1             10                     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr12_dut                Clock source is invalid for GCC
@KP:ckid0_106     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.DQSI_DELAY                GTP_DDC_E1             8                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr12_dut                Black box on clock path        
@KP:ckid0_108     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[11]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr11_dut                Clock source is invalid for GCC
@KP:ckid0_110     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[10]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr10_dut                Clock source is invalid for GCC
@KP:ckid0_112     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.WCLK                      GTP_DDC_E1             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr9_dut                 Clock source is invalid for GCC
@KP:ckid0_114     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[9]          GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr9_dut                 Clock source is invalid for GCC
@KP:ckid0_116     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[7]          GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr7_dut                 Clock source is invalid for GCC
@KP:ckid0_118     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[6]          GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr6_dut                 Clock source is invalid for GCC
@KP:ckid0_120     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[5]          GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr5_dut                 Clock source is invalid for GCC
@KP:ckid0_122     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[4]          GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr4_dut                 Clock source is invalid for GCC
@KP:ckid0_124     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[3]          GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr3_dut                 Clock source is invalid for GCC
@KP:ckid0_126     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[2]          GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr2_dut                 Clock source is invalid for GCC
@KP:ckid0_128     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclkbuf02_dut.CLKOUT              GTP_IOCLKBUF           2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut                      Black box on clock path        
@KP:ckid0_129     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[4]     GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut                      Black box on clock path        
@KP:ckid0_131     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[3]     GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut                      Black box on clock path        
@KP:ckid0_133     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[2]     GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut                      Black box on clock path        
@KP:ckid0_135     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[1]     GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut                      Black box on clock path        
@KP:ckid0_137     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[0]     GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut                      Black box on clock path        
@KP:ckid0_139     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_dll_update_ctrl.dll_update_n.Q[0]       dffr                   8                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.last_dll_step[7:0]     Clock source is invalid for GCC
@KP:ckid0_142     video_pll_m0.u_pll_e1.CLKOUT0                                                          GTP_PLL_E1             245                    video_timing_data_m0.read_req                                                     Black box on clock path        
@KP:ckid0_144     video_pll_m0.u_pll_e1.CLKOUT1                                                          GTP_PLL_E1             59                     dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[2:0]                                  Black box on clock path        
========================================================================================================================================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
@N: MO111 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\ipsl_hmemc_top_test.v":42:41:42:48|Tristate driver err_flag (in view: work.ipsl_hmemc_top_test(verilog)) on net err_flag (in view: work.ipsl_hmemc_top_test(verilog)) has its enable tied to GND.
@N: BN225 |Writing default property annotation file D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\synthesize\synplify_impl\synplify.sap.

Starting constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 232MB peak: 232MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 232MB peak: 232MB)


Finished constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 232MB peak: 232MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 152MB peak: 232MB)

Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Tue May  7 16:40:53 2019

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