@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N: MO111 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\ipsl_hmemc_top_test.v":42:41:42:48|Tristate driver err_flag (in view: work.ipsl_hmemc_top_test(verilog)) on net err_flag (in view: work.ipsl_hmemc_top_test(verilog)) has its enable tied to GND.
@N: MO111 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":175:41:175:51|Tristate driver DQS_DRIFT_H_1 (in view: work.ipsl_phy_io_Z8(verilog)) on net DQS_DRIFT_H_1 (in view: work.ipsl_phy_io_Z8(verilog)) has its enable tied to GND.
@N: MO111 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":175:41:175:51|Tristate driver DQS_DRIFT_H_2 (in view: work.ipsl_phy_io_Z8(verilog)) on net DQS_DRIFT_H_2 (in view: work.ipsl_phy_io_Z8(verilog)) has its enable tied to GND.
@N: MO111 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":174:41:174:51|Tristate driver DQS_DRIFT_L_1 (in view: work.ipsl_phy_io_Z8(verilog)) on net DQS_DRIFT_L_1 (in view: work.ipsl_phy_io_Z8(verilog)) has its enable tied to GND.
@N: MO111 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":174:41:174:51|Tristate driver DQS_DRIFT_L_2 (in view: work.ipsl_phy_io_Z8(verilog)) on net DQS_DRIFT_L_2 (in view: work.ipsl_phy_io_Z8(verilog)) has its enable tied to GND.
@N: MO111 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":100:41:100:47|Tristate driver PSLVERR (in view: work.ipsl_phy_io_Z8(verilog)) on net PSLVERR (in view: work.ipsl_phy_io_Z8(verilog)) has its enable tied to GND.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\ax_debounce.v":100:0:100:5|Removing sequential instance button_posedge (in view: work.ax_debounce(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\color_bar.v":286:0:286:5|Removing sequential instance rgb_r_reg[0] (in view: work.color_bar(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\color_bar.v":286:0:286:5|Removing sequential instance rgb_g_reg[0] (in view: work.color_bar(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\color_bar.v":286:0:286:5|Removing sequential instance rgb_b_reg[0] (in view: work.color_bar(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":349:0:349:5|Removing sequential instance wr_water_level[9:0] (in view: work.ipml_fifo_ctrl_v1_3_9s_8s_ASYN_508s_4s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":370:0:370:5|Removing sequential instance rd_water_level[9:0] (in view: work.ipml_fifo_ctrl_v1_3_8s_9s_ASYN_252s_4s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\color_bar.v":215:0:215:5|Removing sequential instance active_x[11:0] (in view: work.color_bar(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: MO225 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_dll_update_ctrl.v":36:0:36:5|There are no possible illegal states for state machine state[3:0] (in view: work.ipsl_ddrphy_dll_update_ctrl(verilog)); safe FSM implementation is not required.
@N: MO225 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":293:0:293:5|There are no possible illegal states for state machine state[1:0] (in view: work.ipsl_ddrphy_update_ctrl_16BIT_2s_0s_1s_2s_3s_1(verilog)); safe FSM implementation is not required.
@N: MF578 |Incompatible asynchronous control logic preventing generated clock conversion.
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
@N: MO111 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\ipsl_hmemc_top_test.v":42:41:42:48|Tristate driver err_flag (in view: work.ipsl_hmemc_top_test(verilog)) on net err_flag (in view: work.ipsl_hmemc_top_test(verilog)) has its enable tied to GND.
@N: BN225 |Writing default property annotation file D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\synthesize\synplify_impl\synplify.sap.
