// Generated by IP Generator (Version 2019.1-patch2 build 42169)
// Module Instantiation Template
// Insert the following codes into your Verilog file.
//   * Change <InstanceName> to your own instance name.
//   * Fill in your own signal names in the port connections.

ddr3 <InstanceName> (
    .pll_refclk_in(),
    .ddr_rstn_key(),
    .ddrc_rst(),
    .csysreq_ddrc(),
    .csysack_ddrc(),
    .cactive_ddrc(),
    .pll_lock(),
    .pll_aclk_0(),
    .pll_aclk_1(),
    .pll_aclk_2(),
    .pll_pclk(),
    .ddrphy_rst_done(),
    .ddrc_init_done(),
    .pad_loop_in(),
    .pad_loop_in_h(),
    .pad_rstn_ch0(),
    .pad_ddr_clk_w(),
    .pad_ddr_clkn_w(),
    .pad_csn_ch0(),
    .pad_addr_ch0(),
    .pad_dq_ch0(),
    .pad_dqs_ch0(),
    .pad_dqsn_ch0(),
    .pad_dm_rdqs_ch0(),
    .pad_cke_ch0(),
    .pad_odt_ch0(),
    .pad_rasn_ch0(),
    .pad_casn_ch0(),
    .pad_wen_ch0(),
    .pad_ba_ch0(),
    .pad_loop_out(),
    .pad_loop_out_h(),
    .areset_1(),
    .aclk_1(),
    .awid_1(),
    .awaddr_1(),
    .awlen_1(),
    .awsize_1(),
    .awburst_1(),
    .awlock_1(),
    .awvalid_1(),
    .awready_1(),
    .awurgent_1(),
    .awpoison_1(),
    .wdata_1(),
    .wstrb_1(),
    .wlast_1(),
    .wvalid_1(),
    .wready_1(),
    .bid_1(),
    .bresp_1(),
    .bvalid_1(),
    .bready_1(),
    .arid_1(),
    .araddr_1(),
    .arlen_1(),
    .arsize_1(),
    .arburst_1(),
    .arlock_1(),
    .arvalid_1(),
    .arready_1(),
    .arpoison_1(),
    .rid_1(),
    .rdata_1(),
    .rresp_1(),
    .rlast_1(),
    .rvalid_1(),
    .rready_1(),
    .arurgent_1(),
    .csysreq_1(),
    .csysack_1(),
    .cactive_1());
