// Generated by IP Generator (Version 2019.1-patch2 build 42169)
// Module Instantiation Template
// Insert the following codes into your Verilog file.
//   * Change <InstanceName> to your own instance name.
//   * Fill in your own signal names in the port connections.

video_pll <InstanceName> (
    .pll_rst(),
    .clkin1(),
    .pll_lock(),
    .clkout0(),
    .clkout1());
