<?xml version="1.0" encoding="UTF-8"?>
<ip_inst>
    <header>
        <vendor>Pango</vendor>
        <name>Logos HMEMC</name>
        <version>1.0</version>
        <instance>ddr3</instance>
        <family>Logos</family>
        <device>PGL22G</device>
        <package>BG324</package>
        <speedgrade>-7</speedgrade>
        <generator version="2019.1-patch2" build="42169">IP Compiler</generator>
    </header>
    <param_list>
        <param>
            <name>ACTUAL_RATE</name>
            <value>800</value>
        </param>
        <param>
            <name>DDR2_TRCD</name>
            <value>12.5</value>
        </param>
        <param>
            <name>STATIC_RATIO4</name>
            <value>8</value>
        </param>
        <param>
            <name>DDR3_INIT_WR</name>
            <value>6</value>
        </param>
        <param>
            <name>AXI1_DIRECTION</name>
            <value>Bi-directional</value>
        </param>
        <param>
            <name>DDR2_TRP</name>
            <value>13.5</value>
        </param>
        <param>
            <name>PHY_TRP</name>
            <value>3</value>
        </param>
        <param>
            <name>DDR2_INIT_AL</name>
            <value>3</value>
        </param>
        <param>
            <name>GUI_DDR3_TRCD</name>
            <value>13.5</value>
        </param>
        <param>
            <name>STATIC_RATIO2</name>
            <value>8</value>
        </param>
        <param>
            <name>LPDDR_TWTR</name>
            <value>2</value>
        </param>
        <param>
            <name>DDR3_IOSTANDARD</name>
            <value>SSTL15_I</value>
        </param>
        <param>
            <name>DDR_TYPE</name>
            <value>MT41J256M16XX-15E</value>
        </param>
        <param>
            <name>CLKIN_FREQ</name>
            <value>50</value>
        </param>
        <param>
            <name>GUI_DDR3_TRAS</name>
            <value>36</value>
        </param>
        <param>
            <name>DDR3_INIT_CL</name>
            <value>6</value>
        </param>
        <param>
            <name>DDR_IO_DRIVE</name>
            <value>7.5</value>
        </param>
        <param>
            <name>AXI0_WMASK</name>
            <value>0</value>
        </param>
        <param>
            <name>AXI0_ENABLE</name>
            <value>false</value>
        </param>
        <param>
            <name>DDRC_RD2PRE</name>
            <value>4</value>
        </param>
        <param>
            <name>DDR3_TRAS</name>
            <value>37.5</value>
        </param>
        <param>
            <name>APB_CLK_FREQ</name>
            <value>50</value>
        </param>
        <param>
            <name>DDR2_INIT_CL</name>
            <value>5</value>
        </param>
        <param>
            <name>PHY_TRFC</name>
            <value>60</value>
        </param>
        <param>
            <name>AXI2_RMASK</name>
            <value>0</value>
        </param>
        <param>
            <name>DDRC_RD2WR</name>
            <value>4</value>
        </param>
        <param>
            <name>DESIRED_DDR3_RATE</name>
            <value>800</value>
        </param>
        <param>
            <name>DDR_IOSTANDARD</name>
            <value>SSTL15_I</value>
        </param>
        <param>
            <name>GUI_DDR2_TRTP</name>
            <value>7.5</value>
        </param>
        <param>
            <name>DDR3_TRFC</name>
            <value>300</value>
        </param>
        <param>
            <name>GUI_DDR2_TREFI</name>
            <value>7.8</value>
        </param>
        <param>
            <name>LPDDR_BASE_TYPE</name>
            <value>MT46H128M16XXXX-5L-IT</value>
        </param>
        <param>
            <name>AXI2_DIRECTION</name>
            <value>Bi-directional</value>
        </param>
        <param>
            <name>DDR2_TRAS</name>
            <value>45</value>
        </param>
        <param>
            <name>DESIRED_RATE</name>
            <value>800</value>
        </param>
        <param>
            <name>DDRC_WR2RD</name>
            <value>6</value>
        </param>
        <param>
            <name>DDR3_ODT_VALUE</name>
            <value>001</value>
        </param>
        <param>
            <name>GUI_LPDDR_TREFI</name>
            <value>7.8</value>
        </param>
        <param>
            <name>CUSTOMIZE_MEM</name>
            <value>false</value>
        </param>
        <param>
            <name>LPDDR_TRP</name>
            <value>22.5</value>
        </param>
        <param>
            <name>tREFI</name>
            <value>7800</value>
        </param>
        <param>
            <name>DDR3_BASE_TYPE</name>
            <value>MT41J128M16XX-15E</value>
        </param>
        <param>
            <name>STATIC_RATIO0</name>
            <value>2</value>
        </param>
        <param>
            <name>GUI_DDR3_TRTP</name>
            <value>7.5</value>
        </param>
        <param>
            <name>DDRC_T_RAS_MAX</name>
            <value>127</value>
        </param>
        <param>
            <name>DDRC_DFI_T_RDDATA_EN</name>
            <value>4</value>
        </param>
        <param>
            <name>DDRC_T_FAW</name>
            <value>9</value>
        </param>
        <param>
            <name>OPERATING_MODE</name>
            <value>Controller + PHY</value>
        </param>
        <param>
            <name>AXI2_WMASK</name>
            <value>0</value>
        </param>
        <param>
            <name>DDRC_TREFI</name>
            <value>48</value>
        </param>
        <param>
            <name>DDR3_TREFI</name>
            <value>7.8</value>
        </param>
        <param>
            <name>DDR3_TRCD</name>
            <value>13.5</value>
        </param>
        <param>
            <name>GUI_DDR2_TWTR</name>
            <value>7.5</value>
        </param>
        <param>
            <name>GUI_DDR2_TRFC</name>
            <value>197.5</value>
        </param>
        <param>
            <name>GUI_DDR2_TWR</name>
            <value>15</value>
        </param>
        <param>
            <name>GUI_DDR3_TWTR</name>
            <value>7.5</value>
        </param>
        <param>
            <name>DESIRED_LPDDR_RATE</name>
            <value>200</value>
        </param>
        <param>
            <name>GUI_DDR3_TRP</name>
            <value>13.5</value>
        </param>
        <param>
            <name>DDRC_T_XP</name>
            <value>2</value>
        </param>
        <param>
            <name>TOTAL_DQ_WIDTH</name>
            <value>16</value>
        </param>
        <param>
            <name>MEM_ROW_ADDRESS</name>
            <value>15</value>
        </param>
        <param>
            <name>AXI0_CLK_FREQ</name>
            <value>100</value>
        </param>
        <param>
            <name>DDRC_RL</name>
            <value>5</value>
        </param>
        <param>
            <name>DDR2_TYPE</name>
            <value>MT47H128M16XX-25E</value>
        </param>
        <param>
            <name>DDR2_ODT_VALUE</name>
            <value>01</value>
        </param>
        <param>
            <name>GUI_DDR3_TREFI</name>
            <value>7.8</value>
        </param>
        <param>
            <name>PHY_TXPR</name>
            <value>62</value>
        </param>
        <param>
            <name>DDR3_TWTR</name>
            <value>7.5</value>
        </param>
        <param>
            <name>DDRC_T_RP</name>
            <value>3</value>
        </param>
        <param>
            <name>GUI_DDR2_TRP</name>
            <value>12.5</value>
        </param>
        <param>
            <name>DDR3_TRP</name>
            <value>13.5</value>
        </param>
        <param>
            <name>LPDDR_TRCD</name>
            <value>22.5</value>
        </param>
        <param>
            <name>DDRC_T_RRD</name>
            <value>2</value>
        </param>
        <param>
            <name>APB_ENABLE</name>
            <value>false</value>
        </param>
        <param>
            <name>DDR2_INIT_WR</name>
            <value>6</value>
        </param>
        <param>
            <name>DDRC_WR2PRE</name>
            <value>10</value>
        </param>
        <param>
            <name>PHY_PLACE</name>
            <value>left</value>
        </param>
        <param>
            <name>GUI_DDR2_TRCD</name>
            <value>12.5</value>
        </param>
        <param>
            <name>AXI2_CLK_FREQ</name>
            <value>100</value>
        </param>
        <param>
            <name>DDRC_TRFC_MIN</name>
            <value>60</value>
        </param>
        <param>
            <name>DDR2_TRTP</name>
            <value>7.5</value>
        </param>
        <param>
            <name>LPDDR_TYPE</name>
            <value>MT46H128M16XXXX-5L-IT</value>
        </param>
        <param>
            <name>DDR2_TRFC</name>
            <value>197.5</value>
        </param>
        <param>
            <name>ADDRESS_MAPPING_SEL</name>
            <value>0</value>
        </param>
        <param>
            <name>STATIC_RATIO3</name>
            <value>8</value>
        </param>
        <param>
            <name>DDR2_TWTR</name>
            <value>7.5</value>
        </param>
        <param>
            <name>DDRC_WL</name>
            <value>5</value>
        </param>
        <param>
            <name>GUI_DDR2_TRAS</name>
            <value>40</value>
        </param>
        <param>
            <name>LPDDR_TRAS</name>
            <value>45</value>
        </param>
        <param>
            <name>DDR2_TREFI</name>
            <value>7.8</value>
        </param>
        <param>
            <name>GUI_DDR3_TRFC</name>
            <value>160</value>
        </param>
        <param>
            <name>MEM_BANK_ADDRESS</name>
            <value>3</value>
        </param>
        <param>
            <name>LPDDR_INIT_CL</name>
            <value>3</value>
        </param>
        <param>
            <name>LPDDR_TWR</name>
            <value>15</value>
        </param>
        <param>
            <name>DDR3_TYPE</name>
            <value>MT41J256M16XX-15E</value>
        </param>
        <param>
            <name>MEM_COLUMN_ADDRESS</name>
            <value>10</value>
        </param>
        <param>
            <name>DDRC_T_RAS_MIN</name>
            <value>8</value>
        </param>
        <param>
            <name>AXI0_RMASK</name>
            <value>0</value>
        </param>
        <param>
            <name>LPDDR_DRIVER_STRENGTH</name>
            <value>000</value>
        </param>
        <param>
            <name>AXI1_ENABLE</name>
            <value>true</value>
        </param>
        <param>
            <name>DDR3_INIT_CWL</name>
            <value>5</value>
        </param>
        <param>
            <name>GUI_DDR3_TWR</name>
            <value>15</value>
        </param>
        <param>
            <name>GUI_LPDDR_TRCD</name>
            <value>14.4</value>
        </param>
        <param>
            <name>PHY_TMRD</name>
            <value>4</value>
        </param>
        <param>
            <name>GUI_LPDDR_TWR</name>
            <value>14.4</value>
        </param>
        <param>
            <name>PHY_TMOD</name>
            <value>12</value>
        </param>
        <param>
            <name>MEM_TYPE</name>
            <value>DDR3</value>
        </param>
        <param>
            <name>DDR2_IOSTANDARD</name>
            <value>SSTL18_I</value>
        </param>
        <param>
            <name>LPDDR_TRFC</name>
            <value>72</value>
        </param>
        <param>
            <name>DESIRED_DDR2_RATE</name>
            <value>600</value>
        </param>
        <param>
            <name>DDR2_OUTPUT_DRIVER</name>
            <value>0</value>
        </param>
        <param>
            <name>DDRC_DATA_BUS_WIDTH</name>
            <value>0</value>
        </param>
        <param>
            <name>DDR3_TRTP</name>
            <value>7.5</value>
        </param>
        <param>
            <name>STATIC_RATIOF</name>
            <value>32</value>
        </param>
        <param>
            <name>tRFC_MIN</name>
            <value>300000</value>
        </param>
        <param>
            <name>DDR2_TWR</name>
            <value>15</value>
        </param>
        <param>
            <name>AXI0_DIRECTION</name>
            <value>Bi-directional</value>
        </param>
        <param>
            <name>DDR3_TWR</name>
            <value>15</value>
        </param>
        <param>
            <name>AXI1_WMASK</name>
            <value>0</value>
        </param>
        <param>
            <name>GUI_LPDDR_TRFC</name>
            <value>72</value>
        </param>
        <param>
            <name>DDRC_DFI_TPHY_WRLAT</name>
            <value>9</value>
        </param>
        <param>
            <name>AXI1_CLK_FREQ</name>
            <value>100</value>
        </param>
        <param>
            <name>GUI_LPDDR_TWTR</name>
            <value>2</value>
        </param>
        <param>
            <name>DDRC_T_RC</name>
            <value>10</value>
        </param>
        <param>
            <name>AXI2_ENABLE</name>
            <value>false</value>
        </param>
        <param>
            <name>LPDDR_TREFI</name>
            <value>7.8</value>
        </param>
        <param>
            <name>GUI_LPDDR_TRAS</name>
            <value>38.4</value>
        </param>
        <param>
            <name>DDR2_BASE_TYPE</name>
            <value>MT47H128M16XX-25E</value>
        </param>
        <param>
            <name>GUI_LPDDR_TRP</name>
            <value>14.4</value>
        </param>
        <param>
            <name>AXI1_RMASK</name>
            <value>0</value>
        </param>
        <param>
            <name>STATIC_RATIO1</name>
            <value>16</value>
        </param>
        <param>
            <name>DDR3_OUTPUT_DRIVER</name>
            <value>00</value>
        </param>
        <param>
            <name>STATIC_RATIOI</name>
            <value>2</value>
        </param>
    </param_list>
    <pin_list>
        <pin>
            <name>pll_refclk_in</name>
            <text>pll_refclk_in</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>ddr_rstn_key</name>
            <text>ddr_rstn_key</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>ddrc_rst</name>
            <text>ddrc_rst</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>csysreq_ddrc</name>
            <text>csysreq_ddrc</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>csysack_ddrc</name>
            <text>csysack_ddrc</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>cactive_ddrc</name>
            <text>cactive_ddrc</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>pll_lock</name>
            <text>pll_lock</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>pll_aclk_0</name>
            <text>pll_aclk_0</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>pll_aclk_1</name>
            <text>pll_aclk_1</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>pll_aclk_2</name>
            <text>pll_aclk_2</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>pll_pclk</name>
            <text>pll_pclk</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>ddrphy_rst_done</name>
            <text>ddrphy_rst_done</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>ddrc_init_done</name>
            <text>ddrc_init_done</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>pad_loop_in</name>
            <text>pad_loop_in</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>pad_loop_in_h</name>
            <text>pad_loop_in_h</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>pad_rstn_ch0</name>
            <text>pad_rstn_ch0</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>pad_ddr_clk_w</name>
            <text>pad_ddr_clk_w</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>pad_ddr_clkn_w</name>
            <text>pad_ddr_clkn_w</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>pad_csn_ch0</name>
            <text>pad_csn_ch0</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>pad_addr_ch0</name>
            <text>pad_addr_ch0</text>
            <dir>output</dir>
            <pos>right</pos>
            <msb>15</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>pad_dq_ch0</name>
            <text>pad_dq_ch0</text>
            <dir>inout</dir>
            <pos>left</pos>
            <msb>15</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>pad_dqs_ch0</name>
            <text>pad_dqs_ch0</text>
            <dir>inout</dir>
            <pos>left</pos>
            <msb>1</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>pad_dqsn_ch0</name>
            <text>pad_dqsn_ch0</text>
            <dir>inout</dir>
            <pos>left</pos>
            <msb>1</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>pad_dm_rdqs_ch0</name>
            <text>pad_dm_rdqs_ch0</text>
            <dir>output</dir>
            <pos>right</pos>
            <msb>1</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>pad_cke_ch0</name>
            <text>pad_cke_ch0</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>pad_odt_ch0</name>
            <text>pad_odt_ch0</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>pad_rasn_ch0</name>
            <text>pad_rasn_ch0</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>pad_casn_ch0</name>
            <text>pad_casn_ch0</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>pad_wen_ch0</name>
            <text>pad_wen_ch0</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>pad_ba_ch0</name>
            <text>pad_ba_ch0</text>
            <dir>output</dir>
            <pos>right</pos>
            <msb>2</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>pad_loop_out</name>
            <text>pad_loop_out</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>pad_loop_out_h</name>
            <text>pad_loop_out_h</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>areset_1</name>
            <text>areset_1</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>aclk_1</name>
            <text>aclk_1</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>awid_1</name>
            <text>awid_1</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>8</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>awaddr_1</name>
            <text>awaddr_1</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>32</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>awlen_1</name>
            <text>awlen_1</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>8</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>awsize_1</name>
            <text>awsize_1</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>3</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>awburst_1</name>
            <text>awburst_1</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>2</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>awlock_1</name>
            <text>awlock_1</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>awvalid_1</name>
            <text>awvalid_1</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>awready_1</name>
            <text>awready_1</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>awurgent_1</name>
            <text>awurgent_1</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>awpoison_1</name>
            <text>awpoison_1</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>wdata_1</name>
            <text>wdata_1</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>64</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>wstrb_1</name>
            <text>wstrb_1</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>8</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>wlast_1</name>
            <text>wlast_1</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>wvalid_1</name>
            <text>wvalid_1</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>wready_1</name>
            <text>wready_1</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>bid_1</name>
            <text>bid_1</text>
            <dir>output</dir>
            <pos>right</pos>
            <msb>8</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>bresp_1</name>
            <text>bresp_1</text>
            <dir>output</dir>
            <pos>right</pos>
            <msb>2</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>bvalid_1</name>
            <text>bvalid_1</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>bready_1</name>
            <text>bready_1</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>arid_1</name>
            <text>arid_1</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>8</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>araddr_1</name>
            <text>araddr_1</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>32</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>arlen_1</name>
            <text>arlen_1</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>8</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>arsize_1</name>
            <text>arsize_1</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>3</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>arburst_1</name>
            <text>arburst_1</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>2</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>arlock_1</name>
            <text>arlock_1</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>arvalid_1</name>
            <text>arvalid_1</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>arready_1</name>
            <text>arready_1</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>arpoison_1</name>
            <text>arpoison_1</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>rid_1</name>
            <text>rid_1</text>
            <dir>output</dir>
            <pos>right</pos>
            <msb>8</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>rdata_1</name>
            <text>rdata_1</text>
            <dir>output</dir>
            <pos>right</pos>
            <msb>64</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>rresp_1</name>
            <text>rresp_1</text>
            <dir>output</dir>
            <pos>right</pos>
            <msb>2</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>rlast_1</name>
            <text>rlast_1</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>rvalid_1</name>
            <text>rvalid_1</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>rready_1</name>
            <text>rready_1</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>arurgent_1</name>
            <text>arurgent_1</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>csysreq_1</name>
            <text>csysreq_1</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>csysack_1</name>
            <text>csysack_1</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>cactive_1</name>
            <text>cactive_1</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
    </pin_list>
    <synthesis>
        <script><![CDATA[set_option -vlog_std v2001]]></script>
        <script><![CDATA[set_option -disable_io_insertion 1]]></script>
    </synthesis>
    <file_list>
        <output>
            <file pathname="generate.log" format="log" description="Generate Log"/>
            <file pathname="ddr3_tmpl.v" format="verilog" description="Instantiation Template"/>
        </output>
        <source>
            <file pathname="rtl/pll/pll_50_400.v"/>
            <file pathname="rtl/ipsl_ddrc_apb_reset.v"/>
            <file pathname="rtl/ipsl_ddrc_reset_ctrl.v"/>
            <file pathname="rtl/ipsl_ddrphy_dll_update_ctrl.v"/>
            <file pathname="rtl/ipsl_ddrphy_reset_ctrl.v"/>
            <file pathname="rtl/ipsl_ddrphy_training_ctrl.v"/>
            <file pathname="rtl/ipsl_ddrphy_update_ctrl.v"/>
            <file pathname="rtl/ipsl_hmemc_ddrc_top.v"/>
            <file pathname="rtl/ipsl_hmemc_phy_top.v"/>
            <file pathname="rtl/ipsl_phy_io.v"/>
            <file pathname="ddr3.v"/>
        </source>
    </file_list>
</ip_inst>
