/*-----------------------------------------------------------------------
								 \\\|///
							   \\  - -  //
								(  @ @  )
+-----------------------------oOOo-(_)-oOOo-----------------------------+
CONFIDENTIAL IN CONFIDENCE
This confidential and proprietary software may be only used as authorized
by a licensing agreement from CrazyBingo (Thereturnofbingo).
In the event of publication, the following notice is applicable:
Copyright (C) 2011-20xx CrazyBingo Corporation
The entire notice above must be reproduced on all authorized copies.
Author				:		CrazyBingo
Technology blogs 	: 		www.crazyfpga.com
Email Address 		: 		crazyfpga@vip.qq.com
Filename			:		VIP_Bit_Erosion_Detector.v
Date				:		2013-05-26
Description			:		Bit Image Process with Erosion before Dilation Detector.
							Give up the 1th and 2th row edge data caculate for simple process
							Give up the 1th and 2th point of 1 line for simple process
Modification History	:
Date			By			Version			Change Description
=========================================================================
13/05/26		CrazyBingo	1.0				Original
14/03/20		CrazyBingo	2.0				Modification
-------------------------------------------------------------------------
|                                     Oooo								|
+-------------------------------oooO--(   )-----------------------------+
                               (   )   ) /
                                \ (   (_/
                                 \_)
-----------------------------------------------------------------------*/ 

`timescale 1ns/1ns
module VIP_Bit_Erosion_Detector
#(
    	parameter		P_LOG_ENABLE   = 0   ,
        parameter	[1:8*4]	  P_LOG_NAME2	 = "BIN_"
)
//#(
//	parameter	[9:0]	IMG_HDISP = 10'd640,	//1024*768
//	parameter	[9:0]	IMG_VDISP = 10'd480
//)
(
	//global clock
	input				clk,  				//cmos video pixel clock
	input				rst_n,				//global reset

	//Image data prepred to be processd
	input				per_frame_vsync,	//Prepared Image data vsync valid signal
	input				per_frame_href,		//Prepared Image data href vaild  signal
	input				per_frame_clken,	//Prepared Image data output/capture enable clock
	input	[7:0]		per_img_Bit,		//Prepared Image Bit flag outout(1: Value, 0:inValid)
	
	//Image data has been processd
	output				post_frame_vsync,	//Processed Image data vsync valid signal
	output				post_frame_href,	//Processed Image data href vaild  signal
	output				post_frame_clken,	//Processed Image data output/capture enable clock
	output	[7:0]		post_img_Bit		//Processed Image Bit flag outout(1: Value, 0:inValid)
);

//----------------------------------------------------
//Generate 1Bit 3X3 Matrix for Video Image Processor.
//Image data has been processd
wire		matrix_frame_vsync;	//Prepared Image data vsync valid signal
wire		matrix_frame_href;	//Prepared Image data href vaild  signal
wire		matrix_frame_clken;	//Prepared Image data output/capture enable clock	
wire	[7:0]	matrix_p11;
wire	[7:0]	matrix_p12;
wire	[7:0]	matrix_p13;	//3X3 Matrix output
wire	[7:0]	matrix_p21;
wire	[7:0]	matrix_p22;
wire	[7:0]	matrix_p23;
wire	[7:0]	matrix_p31;
wire	[7:0]	matrix_p32;
wire	[7:0]	matrix_p33;

Matrix_3X3  Matrixe_3X3_m0 (
    .clk(clk),                // input
    .matrix_de(matrix_frame_clken),    // output
    .matrix_hs(matrix_frame_href),    // output
    .matrix_vs(matrix_frame_vsync),    // output
    .rst_n(rst_n),            // input
    .ycbcr_de(per_frame_clken),      // input
    .ycbcr_hs(per_frame_href),      // input
    .ycbcr_vs(per_frame_vsync),      // input
    .matrix_p11(matrix_p11),  // output[7:0] 
    .matrix_p12(matrix_p12),  // output[7:0] 
    .matrix_p13(matrix_p13),  // output[7:0] 
    .matrix_p21(matrix_p21),  // output[7:0] 
    .matrix_p22(matrix_p22),  // output[7:0] 
    .matrix_p23(matrix_p23),  // output[7:0] 
    .matrix_p31(matrix_p31),  // output[7:0] 
    .matrix_p32(matrix_p32),  // output[7:0] 
    .matrix_p33(matrix_p33),  // output[7:0] 
    .ycbcr_y(per_img_Bit)        // input[7:0]
);


//Add you arithmetic here
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
//-------------------------------------------
//-------------------------------------------
//Eronsion Parameter
//      Original         Dilation			  Pixel
// [   0  0   0  ]   [   1	1   1 ]     [   P1  P2   P3 ]
// [   0  1   0  ]   [   1  1   1 ]     [   P4  P5   P6 ]
// [   0  0   0  ]   [   1  1	1 ]     [   P7  P8   P9 ]
//P = P1 & P2 & P3 & P4 & P5 & P6 & P7 & 8 & 9;
//---------------------------------------
//Eonsion with or operation
//Step1
reg	[7:0] post_img_Bit1;
reg	[7:0] post_img_Bit2;
reg	[7:0] post_img_Bit3;
always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		begin
		post_img_Bit1 <= 8'd0;
		post_img_Bit2 <= 8'd0;
		post_img_Bit3 <= 8'd0;
		end
	else
		begin
		post_img_Bit1 <= {8{(&matrix_p11) | (&matrix_p12) | (&matrix_p13)}};
		post_img_Bit2 <= {8{(&matrix_p21) | (&matrix_p22) | (&matrix_p23)}};
		post_img_Bit3 <= {8{(&matrix_p21) | (&matrix_p32) | (&matrix_p33)}};
		end
end

//Step 2
reg	[7:0] post_img_Bit4;
always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		post_img_Bit4 <= 8'd0;
	else
		post_img_Bit4 <= {8{(&post_img_Bit1) | (&post_img_Bit2) | (&post_img_Bit3)}};
end

//------------------------------------------
//lag 2 clocks signal sync  
reg	[1:0]	per_frame_vsync_r;
reg	[1:0]	per_frame_href_r;	
reg	[1:0]	per_frame_clken_r;
always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		begin
		per_frame_vsync_r <= 0;
		per_frame_href_r <= 0;
		per_frame_clken_r <= 0;
		end
	else
		begin
		per_frame_vsync_r 	<= 	{per_frame_vsync_r[0], 	matrix_frame_vsync};
		per_frame_href_r 	<= 	{per_frame_href_r[0], 	matrix_frame_href};
		per_frame_clken_r 	<= 	{per_frame_clken_r[0], 	matrix_frame_clken};
		end
end
assign	post_frame_vsync 	= 	per_frame_vsync_r[1];
assign	post_frame_href 	= 	per_frame_href_r[1];
assign	post_frame_clken 	= 	per_frame_clken_r[1];
assign	post_img_Bit		=	post_frame_href ? post_img_Bit4 : 8'd0;

	generate
	if (P_LOG_ENABLE == 32'd1) begin: log
		integer Erosion_file   	;
		
		initial begin
//		    BINARIZATION_file  = $fopen ({"D:/FPGA_CODE/Other_work/fruit/Sim/ISP_sim/Data/BINARIZATION.txt"}   , "w" ) ;
		    Erosion_file  = $fopen ({P_LOG_NAME2,"Erosion.txt"}   , "w" ) ;
		end
		
		always @ ( posedge clk ) begin
			if ( post_frame_clken ) begin
		    	$fdisplay (Erosion_file , "%b", post_img_Bit) ;
			end
		end		
	end 
	endgenerate
endmodule
