

@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 470 clock pin(s) of sequential element(s)
75 gated/generated clock tree(s) driving 1209 clock pin(s) of sequential element(s)
0 instances converted, 1209 sequential instances remain driven by gated/generated clocks

===================================== Non-Gated/Non-Generated Clocks ======================================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                    
-----------------------------------------------------------------------------------------------------------
@KP:ckid0_143     sys_clk             port                   470        sd_card_bmp_m0.bmp_read_m0.state[4]
===========================================================================================================
======================================================================================================================== Gated/Generated Clocks ========================================================================================================================
Clock Tree ID     Driving Element                                                                        Drive Element Type     Unconverted Fanout     Sample Instance                                                                   Explanation                    
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
@KP:ckid0_0       u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1.CLKOUT3                                         GTP_PLL_E1             549                    u_aq_axi_master.rd_state[5]                                                       Black box on clock path        
@KP:ckid0_2       u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1.CLKOUT1                                         GTP_PLL_E1             148                    u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                                     Black box on clock path        
@KP:ckid0_3       u_ipsl_hmemc_top.aclk_0.O[0]                                                           variable               1                      u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                                     Black box on clock path        
@KP:ckid0_4       u_ipsl_hmemc_top.aclk_2.O[0]                                                           variable               1                      u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                                     Black box on clock path        
@KP:ckid0_6       u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclkdiv_dut.CLKDIVOUT             GTP_IOCLKDIV           2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut                    Black box on clock path        
@KP:ckid0_7       u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut.WCLK                      GTP_DDC_E1             5                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut                Clock source is invalid for GCC
@KP:ckid0_9       u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[59]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut                Clock source is invalid for GCC
@KP:ckid0_11      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut.RCLK                      GTP_DDC_E1             5                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut                Clock source is invalid for GCC
@KP:ckid0_13      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[58]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr58_dut                Clock source is invalid for GCC
@KP:ckid0_15      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[57]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr57_dut                Clock source is invalid for GCC
@KP:ckid0_17      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[56]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr56_dut                Clock source is invalid for GCC
@KP:ckid0_19      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[55]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr55_dut                Clock source is invalid for GCC
@KP:ckid0_21      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut.WCLK                      GTP_DDC_E1             12                     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut                Clock source is invalid for GCC
@KP:ckid0_23      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[52]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut                Clock source is invalid for GCC
@KP:ckid0_25      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut.RCLK                      GTP_DDC_E1             12                     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut                Clock source is invalid for GCC
@KP:ckid0_27      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[51]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr51_dut                Clock source is invalid for GCC
@KP:ckid0_29      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[49]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr49_dut                Clock source is invalid for GCC
@KP:ckid0_31      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[48]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr48_dut                Clock source is invalid for GCC
@KP:ckid0_33      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[47]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr47_dut                Clock source is invalid for GCC
@KP:ckid0_35      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[46]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr46_dut                Clock source is invalid for GCC
@KP:ckid0_37      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[45]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr45_dut                Clock source is invalid for GCC
@KP:ckid0_39      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[44]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr44_dut                Clock source is invalid for GCC
@KP:ckid0_41      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[43]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr43_dut                Clock source is invalid for GCC
@KP:ckid0_43      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[42]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr42_dut                Clock source is invalid for GCC
@KP:ckid0_45      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[41]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr41_dut                Clock source is invalid for GCC
@KP:ckid0_47      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[40]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr40_dut                Clock source is invalid for GCC
@KP:ckid0_49      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.WCLK_DELAY                GTP_DDC_E1             9                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut                Clock source is invalid for GCC
@KP:ckid0_51      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[37]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut                Clock source is invalid for GCC
@KP:ckid0_53      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.RCLK                      GTP_DDC_E1             10                     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut                Clock source is invalid for GCC
@KP:ckid0_55      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[36]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr36_dut                Clock source is invalid for GCC
@KP:ckid0_57      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclkbuf01_dut.CLKOUT              GTP_IOCLKBUF           19                     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr36_dut                Black box on clock path        
@KP:ckid0_58      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.DQSI_DELAY                GTP_DDC_E1             8                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr36_dut                Black box on clock path        
@KP:ckid0_60      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[35]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr35_dut                Clock source is invalid for GCC
@KP:ckid0_62      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[34]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr34_dut                Clock source is invalid for GCC
@KP:ckid0_64      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[33]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr33_dut                Clock source is invalid for GCC
@KP:ckid0_66      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[32]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr32_dut                Clock source is invalid for GCC
@KP:ckid0_68      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.WCLK                      GTP_DDC_E1             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr31_dut                Clock source is invalid for GCC
@KP:ckid0_70      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[31]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr31_dut                Clock source is invalid for GCC
@KP:ckid0_72      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[29]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr29_dut                Clock source is invalid for GCC
@KP:ckid0_74      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[28]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr28_dut                Clock source is invalid for GCC
@KP:ckid0_76      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[27]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr27_dut                Clock source is invalid for GCC
@KP:ckid0_78      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut.WCLK                      GTP_DDC_E1             9                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut                Clock source is invalid for GCC
@KP:ckid0_80      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[25]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut                Clock source is invalid for GCC
@KP:ckid0_82      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut.RCLK                      GTP_DDC_E1             9                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut                Clock source is invalid for GCC
@KP:ckid0_84      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[24]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr24_dut                Clock source is invalid for GCC
@KP:ckid0_86      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[23]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr23_dut                Clock source is invalid for GCC
@KP:ckid0_88      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[22]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr22_dut                Clock source is invalid for GCC
@KP:ckid0_90      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[21]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr21_dut                Clock source is invalid for GCC
@KP:ckid0_92      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[20]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr20_dut                Clock source is invalid for GCC
@KP:ckid0_94      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[19]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr19_dut                Clock source is invalid for GCC
@KP:ckid0_96      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[18]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr18_dut                Clock source is invalid for GCC
@KP:ckid0_98      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[17]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr17_dut                Clock source is invalid for GCC
@KP:ckid0_100     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.WCLK_DELAY                GTP_DDC_E1             9                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr12_dut                Clock source is invalid for GCC
@KP:ckid0_102     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[12]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr12_dut                Clock source is invalid for GCC
@KP:ckid0_104     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.RCLK                      GTP_DDC_E1             10                     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr12_dut                Clock source is invalid for GCC
@KP:ckid0_106     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.DQSI_DELAY                GTP_DDC_E1             8                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr12_dut                Black box on clock path        
@KP:ckid0_108     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[11]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr11_dut                Clock source is invalid for GCC
@KP:ckid0_110     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[10]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr10_dut                Clock source is invalid for GCC
@KP:ckid0_112     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.WCLK                      GTP_DDC_E1             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr9_dut                 Clock source is invalid for GCC
@KP:ckid0_114     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[9]          GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr9_dut                 Clock source is invalid for GCC
@KP:ckid0_116     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[7]          GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr7_dut                 Clock source is invalid for GCC
@KP:ckid0_118     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[6]          GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr6_dut                 Clock source is invalid for GCC
@KP:ckid0_120     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[5]          GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr5_dut                 Clock source is invalid for GCC
@KP:ckid0_122     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[4]          GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr4_dut                 Clock source is invalid for GCC
@KP:ckid0_124     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[3]          GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr3_dut                 Clock source is invalid for GCC
@KP:ckid0_126     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[2]          GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr2_dut                 Clock source is invalid for GCC
@KP:ckid0_128     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclkbuf02_dut.CLKOUT              GTP_IOCLKBUF           2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut                      Black box on clock path        
@KP:ckid0_129     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[4]     GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut                      Black box on clock path        
@KP:ckid0_131     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[3]     GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut                      Black box on clock path        
@KP:ckid0_133     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[2]     GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut                      Black box on clock path        
@KP:ckid0_135     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[1]     GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut                      Black box on clock path        
@KP:ckid0_137     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[0]     GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut                      Black box on clock path        
@KP:ckid0_139     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_dll_update_ctrl.dll_update_n.Q[0]       dffr                   8                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.last_dll_step[7:0]     Clock source is invalid for GCC
@KP:ckid0_142     video_pll_m0.u_pll_e1.CLKOUT0                                                          GTP_PLL_E1             245                    video_timing_data_m0.read_req                                                     Black box on clock path        
@KP:ckid0_144     video_pll_m0.u_pll_e1.CLKOUT1                                                          GTP_PLL_E1             59                     dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[2:0]                                  Black box on clock path        
========================================================================================================================================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

