/*-------------------------------------------------------------------------------------
The image data is first subjected to grayscale processing, that is, RGB data is converted
into ycbcr data. Next, binarization and projection processing are performed to calculate
circularity. At the same time, the threshold_binary module determines whether the 
corresponding color is detected according to the set color ranges. After binarization, 
the dilation erosion algorithm is used to remove noise(can remove). Normal binarization 
cannot process bright colors such as yellow-green, so add color binarization operations.
-------------------------------------------------------------------------------------*/

module ISP#(
  parameter		P_LOG_ENABLE   = 0  
)(
    input            pixelclk,
    input            rstin   ,
    input    [23:0]  i_rgb   ,
    input            i_hsync ,
    input            i_vsync ,
    input            i_de    ,

    input            red_en  ,
    input            grenn_en,
    input            blue_en ,
    input  [3:1]     key_in  /* synthesis syn_keep=1 */,
    output   [23:0]  VGA_rgb ,
    output           VGA_hsync,
    output           VGA_vsync,
    output           VGA_de,
    output   [2:0]   frame_cnt    ,
    output   [3:0]   fruit_num    ,
    output           frame_vaild  ,
    output           apple_type_en,
    output           pear_type_en ,
    output           banan_type_en,
    output           mango_type_en,
    output           orang_type_en,
    output           grape_type_en,
    output           pitay_type_en,
    output           kiwi_type_en ,
    output           enable_r     , //color instruct signal output to uart 
    output           enable_g     ,
    output           enable_y     ,
    output           enable_p     ,
    output           enable_n     ,
    output           enable_py    , //pure yellow
    output           enable_o     , //orange
    output           enable_pk     //pink 
   );



wire   [23:0]    o_rgb;
wire   [23:0]    o_ycbcr;
wire             o_hsync;
wire             o_vsync;
wire             o_de;
reg       [7:0]       THRESHOLD   ;
reg        red_en_r;
reg        grenn_en_r;
reg        blue_en_r;

  wire             [2:0]        s_frame_cnt    /*synthesis syn_keep=1*/;
  wire             [17:0]       scircul        /*synthesis syn_keep=1*/; //Circularity integer
  wire                          sc_done        /*synthesis syn_keep=1*/;
  wire                          no_use         /*synthesis syn_keep=1*/;
/*  wire             [4:0]        fruit_num      ;
  wire                          apple_type_en  ;
  wire                          pear_type_en   ;
  wire                          banan_type_en  ;
  wire                          mango_type_en  ;
  wire                          orang_type_en  ;
  wire                          grape_type_en  ;
  wire                          pitay_type_en  ;
  wire                          kiwi_type_en   ;*/   
  wire             [3:0]        total_num      ;
  wire             [7:0]        o_y          ;
  wire                          afbin_vsync  ;
  wire                          afbin_hsync  ;
  wire                          afbin_de     ;
  wire             [7:0]        afbin_color  ;
  wire                          monoc        ;
  wire                          monoc_fall   ;
  wire                          aftd_hsync     ;
  wire                          aftd_vsync     ;
  wire                          aftd_de        ; 

reg        r_frame_vaild /* synthesis syn_preserve = 1 */;
reg [11:0] hcount_l;
reg [11:0] hcount_r;
reg [11:0] vcount_l;
reg [11:0] vcount_r;


wire [11:0] hcount_l_r;
wire [11:0] hcount_r_r;
wire [11:0] vcount_l_r;
wire [11:0] vcount_r_r;


reg    [23:0]HV_dout_r;
reg    [23:0]HV_dout_g;
reg    [23:0]HV_dout_b;
wire [11:0] hcount;
wire [11:0] vcount;

wire HV_o_hsync;
wire HV_o_vsync;
wire HV_o_de;
wire [23:0] HV_dout;
wire [23:0] HV_o_rgb;
wire [23:0] orign_color;

assign   frame_vaild = r_frame_vaild ;
assign   frame_cnt   = s_frame_cnt   ;

always@(posedge pixelclk or negedge rstin)
    if(!rstin) 
      r_frame_vaild  <=  0;    
    else if(aftd_vsync == 1'b1 && aftd_de == 1'b1) 
      r_frame_vaild  <=  1;      
    else if (aftd_vsync == 1'b0) begin
      r_frame_vaild  <=  0;     
end

always@(posedge pixelclk or negedge rstin)
    if(!rstin) begin
      red_en_r<=0;  
    grenn_en_r<=0;
     blue_en_r<=0;   
       end
    else if(grenn_en) begin
      red_en_r<=0;  
    grenn_en_r<=1;
     blue_en_r<=0;        
        end
    else if(1'd1) begin
      red_en_r<=1;  
    grenn_en_r<=0;
     blue_en_r<=0;        
        end        
    else if(blue_en) begin
      red_en_r<=0;  
    grenn_en_r<=0;
     blue_en_r<=1;        
        end
    else begin
      red_en_r<=red_en_r;  
    grenn_en_r<=grenn_en_r;
     blue_en_r<=blue_en_r; 
end


rgb2ycbcr#(
       .P_LOG_ENABLE(P_LOG_ENABLE)
)rgb2ycbcr(
    .pixelclk   (pixelclk),
    .rst_n      (rstin) ,
    .i_rgb      (i_rgb),
    .i_hsync    (i_hsync),
    .i_vsync    (i_vsync),
    .i_de       (i_de),
    .i_de0      (),
  
    .o_rgb      (o_rgb),
    .o_ycbcr    (o_ycbcr),
    .o_hsync    (o_hsync),
    .o_vsync    (o_vsync),    
    .o_de0      (),                          
    .o_de       (o_de)                                                                                        
);



assign    o_y = o_ycbcr[23:16]   ;

binarization #(
     .P_LOG_ENABLE(P_LOG_ENABLE)  
//     .THRESHOLD   (THRESHOLD)   //70(apple,grape,kiwi) 88(pear) 95(orange)
) bin(
    //module clock
    .clk             (pixelclk        ),   // 时钟信号
    .rst_n           (rstin           ),   // 复位信号（低有效??
    .pre_frame_vsync (o_vsync         ),   // vsync信号
    .pre_frame_hsync (o_hsync         ),   // hsync信号
    .pre_frame_de    (o_de            ),   // data enable信号
    .color           (o_y             ),
    .post_frame_vsync(afbin_vsync     ),   // vsync信号
    .post_frame_hsync(afbin_hsync     ),   // hsync信号
    .post_frame_de   (afbin_de        ),   // data enable信号
    .bin_color       (afbin_color     ),
    .orign_color     (orign_color     ),
    .monoc           (monoc           ),   // monochrome??=白，0=黑）
    .monoc_fall      (monoc_fall      ),
    .THRESHOLD       (THRESHOLD       )   //70(apple,grape,kiwi) 88(pear) 95(orange)
);

wire           dilation_vs  ;
wire           dilation_hs  ;
wire           dilation_de  ;
wire  [7:0]    dilation_data;
wire           erosion_vs   ;
wire           erosion_hs   ;
wire           erosion_de   ;
wire  [7:0]    erosion_data ; 


VIP_Bit_Dilation_Detector #(
     .P_LOG_ENABLE(P_LOG_ENABLE)  ,
     .P_LOG_NAME2("BIN_")
)BDD(
//global clock
.clk            (pixelclk    ),  	              //cmos video pixel clock
.rst_n          (rstin       ),	              //global reset

//Image data prepred to be processd
.per_frame_vsync(afbin_vsync),	//Prepared Image data vsync valid signal
.per_frame_href (afbin_hsync),	//Prepared Image data href vaild  signal
.per_frame_clken(afbin_de   ),	//Prepared Image data output/capture enable clock
.per_img_Bit    (afbin_color),	//Prepared Image Bit flag outout(1: Value, 0:inValid)
	
//Image data has been processd
.post_frame_vsync(dilation_vs  ),	//Processed Image data vsync valid signal
.post_frame_href (dilation_hs  ),	//Processed Image data href vaild  signal
.post_frame_clken(dilation_de  ),	//Processed Image data output/capture enable clock
.post_img_Bit    (dilation_data)   	//Processed Image Bit flag outout(1: Value, 0:inValid)
);

VIP_Bit_Erosion_Detector#(
     .P_LOG_ENABLE(P_LOG_ENABLE) ,
     .P_LOG_NAME2("BIN_")
)BED(
	//global clock
     .clk            (pixelclk    ),  	//cmos video pixel clock
     .rst_n          (rstin       ),	//global reset

	//Image data prepred to be processd
     .per_frame_vsync(dilation_vs  ),	//Prepared Image data vsync valid signal
     .per_frame_href (dilation_hs  ),	//Prepared Image data href vaild  signal
     .per_frame_clken(dilation_de  ),	//Prepared Image data output/capture enable clock
     .per_img_Bit    (dilation_data),	//Prepared Image Bit flag outout(1: Value, 0:inValid)
	
	//Image data has been processd
     .post_frame_vsync(erosion_vs  ),	//Processed Image data vsync valid signal
     .post_frame_href (erosion_hs  ),	//Processed Image data href vaild  signal
     .post_frame_clken(erosion_de  ),	//Processed Image data output/capture enable clock
     .post_img_Bit    (erosion_data)	//Processed Image Bit flag outout(1: Value, 0:inValid)
);

Vertical_Projection_sum#(
     .IMG_WIDTH_LINE( 1024 )  ,
     .DIV_REVERSE(0),
     .THRED_BINARY  (24'hffffff)   
)VPS(
     .pixelclk   (pixelclk       ),
     .reset_n    (rstin          ), 
     .en         (1'b1           ),   
//     .i_binary   ({afbin_color,afbin_color,afbin_color}),
//     .i_hs       (afbin_hsync),
//     .i_vs       (afbin_vsync),
//     .i_de       (afbin_de   ),       
     .i_binary   ({erosion_data,erosion_data,erosion_data}),
     .i_hs       (erosion_hs     ),
     .i_vs       (erosion_vs     ),
     .i_de       (erosion_de     ),

     .i_hcount   (hcount     ),
     .i_vcount   (vcount     ),

     .hcount_l   (hcount_l_r ),
     .hcount_r   (hcount_r_r ),
     .vcount_l   (vcount_l_r ),
     .vcount_r   (vcount_r_r ),
     .s_frame_cnt(s_frame_cnt),
     .scircul    (scircul    ), //Circularity integer
     .sc_done    (sc_done    ),
     .total_num  (total_num  ),
     .no_use     (no_use     )
 );


  
wire [23:0] o_binary_1 ;
wire [23:0] binary_g ;
wire [23:0] binary_o ;
wire [23:0] binary_y ;
wire [23:0] binary_py; 
wire [23:0] o_rgb_1    ;
wire        o_hsync_1  ;
wire        o_vsync_1  ;
wire        o_de_1     ;
wire        y_large_g  /*synthesis syn_keep=1*/;
wire        p_large_o  /*synthesis syn_keep=1*/;
wire        p_large_g  /*synthesis syn_keep=1*/;
wire        r_large_g  /*synthesis syn_keep=1*/;
wire        n_large_g  /*synthesis syn_keep=1*/;
wire        pk_large_o /*synthesis syn_keep=1*/;
wire        r_large_py /*synthesis syn_keep=1*/;
wire        pk_large_py/*synthesis syn_keep=1*/;
wire        y_large_py/*synthesis syn_keep=1*/;
wire        py_large_g/*synthesis syn_keep=1*/;

threshold_binary#(
        .DW          (24 ) ,
        .P_LOG_ENABLE(P_LOG_ENABLE),
//        .Y_TH        (182) ,
//        .Y_TL        (179 ) ,
//        .CB_TH       (128) ,
//        .CB_TL       (125) ,
//        .CR_TH       (130) ,
//        .CR_TL       (129) , //deep red apple

        .Y_TH        (29 ) ,
        .Y_TL        (22 ) ,
        .CB_TH       (126) ,
        .CB_TL       (124) ,
        .CR_TH       (138) ,
        .CR_TL       (131) , //deep red apple change new

        .Y_TH_G      (106) ,
        .Y_TL_G      (66 ) ,
        .CB_TH_G     (100) ,
        .CB_TL_G     (78) ,
        .CR_TH_G     (111) ,
        .CR_TL_G     (101) , //FPGA_MATLAB green pear expand
//        .Y_TH_G      (142) ,
//        .Y_TL_G      (46 ) ,
//        .CB_TH_G     (111) ,
//        .CB_TL_G     (69) ,
//        .CR_TH_G     (139) ,
//        .CR_TL_G     (126) , //FPGA_MATLAB green pear expand2

//        .Y_TH_Y_B    (187) ,
//        .Y_TL_Y_B    (122) ,
//        .CB_TH_Y_B   (70) ,
//        .CB_TL_Y_B   (34) ,
//        .CR_TH_Y_B   (148) ,
//        .CR_TL_Y_B   (133) ,  //FPGA_MATLAB light yellow banana expand dusk light
        .Y_TH_Y_B    (140) ,
        .Y_TL_Y_B    (123) ,
        .CB_TH_Y_B   (69) ,
        .CB_TL_Y_B   (60) ,
        .CR_TH_Y_B   (123) ,
        .CR_TL_Y_B   (114) ,  //FPGA_MATLAB light yellow banana expand2

//        .Y_TH_Y_M    (142) ,
//        .Y_TL_Y_M    (46) ,
//        .CB_TH_Y_M   (111) ,
//        .CB_TL_Y_M   (69) ,
//        .CR_TH_Y_M   (139) ,
//        .CR_TL_Y_M   (126) ,  //FPGA_MATLAB pure yellow mango use green good
        .Y_TH_Y_M    (129) ,
        .Y_TL_Y_M    (102) ,
        .CB_TH_Y_M   (80) ,
        .CB_TL_Y_M   (71) ,
        .CR_TH_Y_M   (138) ,
        .CR_TL_Y_M   (129) ,  //FPGA_MATLAB pure yellow mango expand2

        .Y_TH_Y_O    (150) ,
        .Y_TL_Y_O    (38 ) ,
        .CB_TH_Y_O   (115) ,
        .CB_TL_Y_O   (82) ,
        .CR_TH_Y_O   (191) ,
        .CR_TL_Y_O   (162) ,  //FPGA_MATLAB orange orange expand 
//        .Y_TH_Y_O    (150) ,
//        .Y_TL_Y_O    (38 ) ,
//        .CB_TH_Y_O   (130) ,
//        .CB_TL_Y_O   (82) ,
//        .CR_TH_Y_O   (191) ,
//        .CR_TL_Y_O   (126) ,  //FPGA_MATLAB orange orange expand2
//        .Y_TH_P      (53 ) ,
//        .Y_TL_P      (29 ) ,
//        .CB_TH_P     (137) ,
//        .CB_TL_P     (128) ,
//        .CR_TH_P     (169) ,
//        .CR_TL_P     (155) ,   //purple grape change new
//        .Y_TH_P      (101 ) ,
//        .Y_TL_P      (32 ) ,
//        .CB_TH_P     (122) ,
//        .CB_TL_P     (111) ,
//        .CR_TH_P     (163) ,
//        .CR_TL_P     (149) ,   //FPGA_MATLAB purple grape row line
        .Y_TH_P      (60 ) ,
        .Y_TL_P      (23) ,
        .CB_TH_P     (127) ,
        .CB_TL_P     (110) ,
        .CR_TH_P     (140) ,
        .CR_TL_P     (127) ,   //FPGA_MATLAB purple grape row line

        .Y_TH_PK     (56) ,
        .Y_TL_PK     (41 ) ,
        .CB_TH_PK    (132) ,
        .CB_TL_PK    (80) ,
        .CR_TH_PK    (205) ,
        .CR_TL_PK    (100) ,   //FPGA_MATLAB pink pitaya row line

        .Y_TH_N      (49 ) ,
        .Y_TL_N      (40 ) ,
        .CB_TH_N     (118) ,
        .CB_TL_N     (111) ,
        .CR_TH_N     (129) ,
        .CR_TL_N     (120)     //FPGA_MATLAB brown kiwi row line
)threshold_binary(
        .pixelclk   (pixelclk  ),
        .reset_n    (rstin     ),
        .i_ycbcr    (o_ycbcr   ),
        .i_rgb      (o_rgb     ),
        .i_hsync    (o_hsync   ),
        .i_vsync    (o_vsync   ),
        .i_de       (o_de      ),
        .p_large_o  (p_large_o ),
        .p_large_g  (p_large_g ),     
        .y_large_g  (y_large_g ),
        .r_large_g  (r_large_g ),
        .n_large_g  (n_large_g ),
        .pk_large_o (pk_large_o),
        .r_large_py (r_large_py),
        .pk_large_py(pk_large_py),
        .y_large_py (y_large_py),
        .py_large_g (py_large_g),
        .enable_r   (enable_r  ), //color instruct signal output to uart 
        .enable_g   (enable_g  ),
        .enable_y   (enable_y  ),
        .enable_p   (enable_p  ),
        .enable_n   (enable_n  ),
        .enable_py  (enable_py ), //pure yellow
        .enable_o   (enable_o  ), //orange
        .enable_pk  (enable_pk ), //pink        
        .binary_g   (binary_g  ),
        .binary_o   (binary_o  ),
        .binary_y   (binary_y  ),
        .binary_py  (binary_py ),
        .o_rgb      (o_rgb_1   ),
        .o_hsync    (o_hsync_1 ),
        .o_vsync    (o_vsync_1 ),   
        .o_de       (o_de_1    )                                                                                         
);
wire           tb_dilation_vs_g  ;
wire           tb_dilation_hs_g  ;
wire           tb_dilation_de_g  ;
wire  [7:0]    tb_dilation_data_g;
wire           tb_erosion_vs_g   ;
wire           tb_erosion_hs_g   ;
wire           tb_erosion_de_g   ;
wire  [7:0]    tb_erosion_data_g ;

wire           tb_dilation_vs_y  ;
wire           tb_dilation_hs_y  ;
wire           tb_dilation_de_y  ;
wire  [7:0]    tb_dilation_data_y;
wire           tb_erosion_vs_y   ;
wire           tb_erosion_hs_y   ;
wire           tb_erosion_de_y   ;
wire  [7:0]    tb_erosion_data_y ; 

wire           tb_dilation_vs_o  ;
wire           tb_dilation_hs_o  ;
wire           tb_dilation_de_o  ;
wire  [7:0]    tb_dilation_data_o;
wire           tb_erosion_vs_o   ;
wire           tb_erosion_hs_o   ;
wire           tb_erosion_de_o   ;
wire  [7:0]    tb_erosion_data_o ;

wire           tb_dilation_vs_py  ;
wire           tb_dilation_hs_py  ;
wire           tb_dilation_de_py  ;
wire  [7:0]    tb_dilation_data_py;
wire           tb_erosion_vs_py   ;
wire           tb_erosion_hs_py   ;
wire           tb_erosion_de_py   ;
wire  [7:0]    tb_erosion_data_py ; 

wire           temp_vs  ;
wire           temp_hs  ;
wire           temp_de  ;
wire  [7:0]    temp_data_g;
wire  [7:0]    temp_data_y;
wire  [7:0]    temp_data_o;
wire  [7:0]    temp_data_py;
//
assign    temp_vs    =  o_vsync_1;
assign    temp_hs    =  o_hsync_1;
assign    temp_de    =  o_de_1   ;
assign    temp_data_g  =  ((o_de_1==1'b1)&&(binary_g==24'h111111))?8'hff:8'h00;
assign    temp_data_y  =  ((o_de_1==1'b1)&&(binary_y==24'h222222))?8'hff:8'h00;
assign    temp_data_o  =  ((o_de_1==1'b1)&&(binary_o==24'h333333))?8'hff:8'h00;
assign    temp_data_py =  ((o_de_1==1'b1)&&(binary_py==24'h444444))?8'hff:8'h00;

VIP_Bit_Dilation_Detector #(
     .P_LOG_ENABLE(P_LOG_ENABLE) ,
     .P_LOG_NAME2("TBIG") 
)th_BDD_g(
//global clock
.clk            (pixelclk    ),  	              //cmos video pixel clock
.rst_n          (rstin       ),	              //global reset
//Image data prepred to be processd
.per_frame_vsync(temp_vs     ),	//Prepared Image data vsync valid signal
.per_frame_href (temp_hs     ),	//Prepared Image data href vaild  signal
.per_frame_clken(temp_de     ),	//Prepared Image data output/capture enable clock
.per_img_Bit    (temp_data_g ),	//Prepared Image Bit flag outout(1: Value, 0:inValid)
//Image data has been processd
.post_frame_vsync(tb_dilation_vs_g  ),	//Processed Image data vsync valid signal
.post_frame_href (tb_dilation_hs_g  ),	//Processed Image data href vaild  signal
.post_frame_clken(tb_dilation_de_g  ),	//Processed Image data output/capture enable clock
.post_img_Bit    (tb_dilation_data_g)   	//Processed Image Bit flag outout(1: Value, 0:inValid)
);

VIP_Bit_Erosion_Detector#(
     .P_LOG_ENABLE(P_LOG_ENABLE) ,
     .P_LOG_NAME2("TBIG") 
)th_BED_g(
	//global clock
     .clk            (pixelclk    ),  	//cmos video pixel clock
     .rst_n          (rstin       ),	//global reset
	//Image data prepred to be processd
     .per_frame_vsync(tb_dilation_vs_g  ),	//Prepared Image data vsync valid signal
     .per_frame_href (tb_dilation_hs_g  ),	//Prepared Image data href vaild  signal
     .per_frame_clken(tb_dilation_de_g  ),	//Prepared Image data output/capture enable clock
     .per_img_Bit    (tb_dilation_data_g),	//Prepared Image Bit flag outout(1: Value, 0:inValid)
	
	//Image data has been processd
     .post_frame_vsync(tb_erosion_vs_g  ),	//Processed Image data vsync valid signal
     .post_frame_href (tb_erosion_hs_g  ),	//Processed Image data href vaild  signal
     .post_frame_clken(tb_erosion_de_g  ),	//Processed Image data output/capture enable clock
     .post_img_Bit    (tb_erosion_data_g)	//Processed Image Bit flag outout(1: Value, 0:inValid)
);

VIP_Bit_Dilation_Detector #(
     .P_LOG_ENABLE(P_LOG_ENABLE) ,
     .P_LOG_NAME2("TBIY") 
)th_BDD_y(
//global clock
.clk            (pixelclk    ),  	              //cmos video pixel clock
.rst_n          (rstin       ),	              //global reset
//Image data prepred to be processd
.per_frame_vsync(temp_vs     ),	//Prepared Image data vsync valid signal
.per_frame_href (temp_hs     ),	//Prepared Image data href vaild  signal
.per_frame_clken(temp_de     ),	//Prepared Image data output/capture enable clock
.per_img_Bit    (temp_data_y ),	//Prepared Image Bit flag outout(1: Value, 0:inValid)
//Image data has been processd
.post_frame_vsync(tb_dilation_vs_y  ),	//Processed Image data vsync valid signal
.post_frame_href (tb_dilation_hs_y  ),	//Processed Image data href vaild  signal
.post_frame_clken(tb_dilation_de_y  ),	//Processed Image data output/capture enable clock
.post_img_Bit    (tb_dilation_data_y)   	//Processed Image Bit flag outout(1: Value, 0:inValid)
);

VIP_Bit_Erosion_Detector#(
     .P_LOG_ENABLE(P_LOG_ENABLE) ,
     .P_LOG_NAME2("TBIY") 
)th_BED_y(
	//global clock
     .clk            (pixelclk    ),  	//cmos video pixel clock
     .rst_n          (rstin       ),	//global reset
	//Image data prepred to be processd
     .per_frame_vsync(tb_dilation_vs_y  ),	//Prepared Image data vsync valid signal
     .per_frame_href (tb_dilation_hs_y  ),	//Prepared Image data href vaild  signal
     .per_frame_clken(tb_dilation_de_y  ),	//Prepared Image data output/capture enable clock
     .per_img_Bit    (tb_dilation_data_y),	//Prepared Image Bit flag outout(1: Value, 0:inValid)
	
	//Image data has been processdy
     .post_frame_vsync(tb_erosion_vs_y  ),	//Processed Image data vsync valid signal
     .post_frame_href (tb_erosion_hs_y  ),	//Processed Image data href vaild  signal
     .post_frame_clken(tb_erosion_de_y  ),	//Processed Image data output/capture enable clock
     .post_img_Bit    (tb_erosion_data_y)	//Processed Image Bit flag outout(1: Value, 0:inValid)
);

VIP_Bit_Dilation_Detector #(
     .P_LOG_ENABLE(P_LOG_ENABLE) ,
     .P_LOG_NAME2("TBIO") 
)th_BDD_o(
//global clock
.clk            (pixelclk    ),  	              //cmos video pixel clock
.rst_n          (rstin       ),	              //global reset
//Image data prepred to be processd
.per_frame_vsync(temp_vs     ),	//Prepared Image data vsync valid signal
.per_frame_href (temp_hs     ),	//Prepared Image data href vaild  signal
.per_frame_clken(temp_de     ),	//Prepared Image data output/capture enable clock
.per_img_Bit    (temp_data_o ),	//Prepared Image Bit flag outout(1: Value, 0:inValid)
//Image data has been processd
.post_frame_vsync(tb_dilation_vs_o  ),	//Processed Image data vsync valid signal
.post_frame_href (tb_dilation_hs_o  ),	//Processed Image data href vaild  signal
.post_frame_clken(tb_dilation_de_o  ),	//Processed Image data output/capture enable clock
.post_img_Bit    (tb_dilation_data_o)   	//Processed Image Bit flag outout(1: Value, 0:inValid)
);

VIP_Bit_Erosion_Detector#(
     .P_LOG_ENABLE(P_LOG_ENABLE) ,
     .P_LOG_NAME2("TBIO") 
)th_BED_o(
	//global clock
     .clk            (pixelclk    ),  	//cmos video pixel clock
     .rst_n          (rstin       ),	//global reset
	//Image data prepred to be processd
     .per_frame_vsync(tb_dilation_vs_o  ),	//Prepared Image data vsync valid signal
     .per_frame_href (tb_dilation_hs_o  ),	//Prepared Image data href vaild  signal
     .per_frame_clken(tb_dilation_de_o  ),	//Prepared Image data output/capture enable clock
     .per_img_Bit    (tb_dilation_data_o),	//Prepared Image Bit flag outout(1: Value, 0:inValid)
	
	//Image data has been processdy
     .post_frame_vsync(tb_erosion_vs_o  ),	//Processed Image data vsync valid signal
     .post_frame_href (tb_erosion_hs_o  ),	//Processed Image data href vaild  signal
     .post_frame_clken(tb_erosion_de_o  ),	//Processed Image data output/capture enable clock
     .post_img_Bit    (tb_erosion_data_o)	//Processed Image Bit flag outout(1: Value, 0:inValid)
);

VIP_Bit_Dilation_Detector #(
     .P_LOG_ENABLE(P_LOG_ENABLE) ,
     .P_LOG_NAME2("TBIP") 
)th_BDD_py(
//global clock
.clk            (pixelclk    ),  	              //cmos video pixel clock
.rst_n          (rstin       ),	              //global reset
//Image data prepred to be processd
.per_frame_vsync(temp_vs     ),	//Prepared Image data vsync valid signal
.per_frame_href (temp_hs     ),	//Prepared Image data href vaild  signal
.per_frame_clken(temp_de     ),	//Prepared Image data output/capture enable clock
.per_img_Bit    (temp_data_py),	//Prepared Image Bit flag outout(1: Value, 0:inValid)
//Image data has been processd
.post_frame_vsync(tb_dilation_vs_py ),	//Processed Image data vsync valid signal
.post_frame_href (tb_dilation_hs_py ),	//Processed Image data href vaild  signal
.post_frame_clken(tb_dilation_de_py ),	//Processed Image data output/capture enable clock
.post_img_Bit    (tb_dilation_data_py)   	//Processed Image Bit flag outout(1: Value, 0:inValid)
);

VIP_Bit_Erosion_Detector#(
     .P_LOG_ENABLE(P_LOG_ENABLE) ,
     .P_LOG_NAME2("TBIP") 
)th_BED_py(
	//global clock
     .clk            (pixelclk    ),  	//cmos video pixel clock
     .rst_n          (rstin       ),	//global reset
	//Image data prepred to be processd
     .per_frame_vsync(tb_dilation_vs_py ),	//Prepared Image data vsync valid signal
     .per_frame_href (tb_dilation_hs_py ),	//Prepared Image data href vaild  signal
     .per_frame_clken(tb_dilation_de_py ),	//Prepared Image data output/capture enable clock
     .per_img_Bit    (tb_dilation_data_py),	//Prepared Image Bit flag outout(1: Value, 0:inValid)
	
	//Image data has been processdy
     .post_frame_vsync(tb_erosion_vs_py),	//Processed Image data vsync valid signal
     .post_frame_href (tb_erosion_hs_py),	//Processed Image data href vaild  signal
     .post_frame_clken(tb_erosion_de_py),	//Processed Image data output/capture enable clock
     .post_img_Bit    (tb_erosion_data_py)	//Processed Image Bit flag outout(1: Value, 0:inValid)
);
/*------------------------------------------------------------
  green orange pure_yellow yellow projection
------------------------------------------------------------*/
  wire             [2:0]        g_s_frame_cnt    ;
  wire             [17:0]       g_scircul        ; //Circularity integer
  wire                          g_sc_done        ;
  wire                          g_no_use         ;
  wire             [3:0]        g_total_num      ;
  wire             [2:0]        o_s_frame_cnt    ;
  wire             [17:0]       o_scircul        ; //Circularity integer
  wire                          o_sc_done        ;
  wire                          o_no_use         ;
  wire             [3:0]        o_total_num      ;
  wire             [2:0]        py_s_frame_cnt   ;
  wire             [17:0]       py_scircul       ; //Circularity integer
  wire                          py_sc_done       ;
  wire                          py_no_use        ;
  wire             [3:0]        py_total_num     ;
  wire             [2:0]        y_s_frame_cnt    ;
  wire             [17:0]       y_scircul        ; //Circularity integer
  wire                          y_sc_done        ;
  wire                          y_no_use         ;
  wire             [3:0]        y_total_num      ;

  wire             [11:0]       hcount_l_g        ;
  wire             [11:0]       hcount_r_g        ;
  wire             [11:0]       vcount_l_g        ;
  wire             [11:0]       vcount_r_g        ;                                                    
  wire             [11:0]       hcount_l_o        ;
  wire             [11:0]       hcount_r_o        ;
  wire             [11:0]       vcount_l_o        ;
  wire             [11:0]       vcount_r_o        ;
  wire             [11:0]       hcount_l_py       ;
  wire             [11:0]       hcount_r_py       ;
  wire             [11:0]       vcount_l_py       ;
  wire             [11:0]       vcount_r_py       ;  
  wire             [11:0]       hcount_l_y        ;
  wire             [11:0]       hcount_r_y        ;
  wire             [11:0]       vcount_l_y        ;
  wire             [11:0]       vcount_r_y        ; 

Vertical_Projection_sum#(
     .IMG_WIDTH_LINE( 1024 )  ,
     .DIV_REVERSE(0),
     .THRED_BINARY  (24'hffffff)   //green
)VPS_g(
     .pixelclk   (pixelclk       ),
     .reset_n    (rstin          ), 
     .en         (1'b1           ),   
//     .i_binary   ({afbin_color,afbin_color,afbin_color}),
//     .i_hs       (afbin_hsync),
//     .i_vs       (afbin_vsync),
//     .i_de       (afbin_de   ),       
     .i_binary   ({tb_erosion_data_g,tb_erosion_data_g,tb_erosion_data_g}),
     .i_hs       (tb_erosion_hs_g),
     .i_vs       (tb_erosion_vs_g),
     .i_de       (tb_erosion_de_g),

     .i_hcount   (hcount         ),
     .i_vcount   (vcount         ),
    
     .hcount_l   (hcount_l_g     ),
     .hcount_r   (hcount_r_g     ),
     .vcount_l   (vcount_l_g     ),
     .vcount_r   (vcount_r_g     ),
     .s_frame_cnt(g_s_frame_cnt  ),
     .scircul    (g_scircul      ), //Circularity integer
     .sc_done    (g_sc_done      ),
     .total_num  (g_total_num    ),
     .no_use     (g_no_use       )
 );

 Vertical_Projection_sum#(
     .IMG_WIDTH_LINE( 1024 )  ,
     .DIV_REVERSE(1),
     .THRED_BINARY  (24'hffffff)   
 )VPS_y(
     .pixelclk   (pixelclk       ),
     .reset_n    (rstin          ), 
     .en         (1'b1           ),   
//     .i_binary   ({afbin_color,afbin_color,afbin_color}),
//     .i_hs       (afbin_hsync),
//     .i_vs       (afbin_vsync),
//     .i_de       (afbin_de   ),       
     .i_binary   ({tb_erosion_data_y,tb_erosion_data_y,tb_erosion_data_y}),
     .i_hs       (tb_erosion_hs_y),
     .i_vs       (tb_erosion_vs_y),
     .i_de       (tb_erosion_de_y),

     .i_hcount   (hcount        ),
     .i_vcount   (vcount        ),
   
     .hcount_l   (hcount_l_y    ),
     .hcount_r   (hcount_r_y    ),
     .vcount_l   (vcount_l_y    ),
     .vcount_r   (vcount_r_y    ),
     .s_frame_cnt(y_s_frame_cnt ),
     .scircul    (y_scircul     ), //Circularity integer
     .sc_done    (y_sc_done     ),
     .total_num  (y_total_num   ),
     .no_use     (y_no_use      )
 );

 Vertical_Projection_sum#(
     .IMG_WIDTH_LINE( 1024 )  ,
     .DIV_REVERSE(0),
     .THRED_BINARY  (24'hffffff)   
)VPS_o(
     .pixelclk   (pixelclk       ),
     .reset_n    (rstin          ), 
     .en         (1'b1           ),   
//     .i_binary   ({afbin_color,afbin_color,afbin_color}),
//     .i_hs       (afbin_hsync),
//     .i_vs       (afbin_vsync),
//     .i_de       (afbin_de   ),       
     .i_binary   ({tb_erosion_data_o,tb_erosion_data_o,tb_erosion_data_o}),
     .i_hs       (tb_erosion_hs_o),
     .i_vs       (tb_erosion_vs_o),
     .i_de       (tb_erosion_de_o),

     .i_hcount   (hcount     ),
     .i_vcount   (vcount     ),

     .hcount_l   (hcount_l_o ),
     .hcount_r   (hcount_r_o ),
     .vcount_l   (vcount_l_o ),
     .vcount_r   (vcount_r_o ),
     .s_frame_cnt(o_s_frame_cnt),
     .scircul    (o_scircul    ), //Circularity integer
     .sc_done    (o_sc_done    ),
     .total_num  (o_total_num  ),
     .no_use     (o_no_use     )
 );

 Vertical_Projection_sum#(
     .IMG_WIDTH_LINE( 1024 )  ,
     .DIV_REVERSE(0),
     .THRED_BINARY  (24'hffffff)   
 )VPS_py(
     .pixelclk   (pixelclk       ),
     .reset_n    (rstin          ), 
     .en         (1'b1           ),   
//     .i_binary   ({afbin_color,afbin_color,afbin_color}),
//     .i_hs       (afbin_hsync),
//     .i_vs       (afbin_vsync),
//     .i_de       (afbin_de   ),       
     .i_binary   ({tb_erosion_data_py,tb_erosion_data_py,tb_erosion_data_py}),
     .i_hs       (tb_erosion_hs_py),
     .i_vs       (tb_erosion_vs_py),
     .i_de       (tb_erosion_de_py),

     .i_hcount   (hcount         ),
     .i_vcount   (vcount         ),

     .hcount_l   (hcount_l_py    ),
     .hcount_r   (hcount_r_py    ),
     .vcount_l   (vcount_l_py    ),
     .vcount_r   (vcount_r_py    ),
     .s_frame_cnt(py_s_frame_cnt ),
     .scircul    (py_scircul     ), //Circularity integer
     .sc_done    (py_sc_done     ),
     .total_num  (py_total_num   ),
     .no_use     (py_no_use      )
 );
/*------------------------------------------------------------
 end
------------------------------------------------------------*/

wire             tds_i_hs              ;
wire             tds_i_vs              ;
wire             tds_i_de              ;
wire     [ 2:0]  tds_s_frame_cnt       ;
wire     [17:0]  tds_scircul_1         ;
wire             tds_sc_done_1         ;
wire     [3:0]   tds_total_num_1       ;

reg              r_tds_i_hs            ;
reg              r_tds_i_vs            ;
reg              r_tds_i_de            ;
reg      [ 2:0]  r_tds_s_frame_cnt     ;
reg      [17:0]  r_tds_scircul_1       ;
reg              r_tds_sc_done_1       ;
reg      [3:0]   r_tds_total_num_1     ;

assign     tds_i_hs         =  r_tds_i_hs;
assign     tds_i_vs         =  r_tds_i_vs;
assign     tds_i_de         =  r_tds_i_de;
assign     tds_s_frame_cnt  =  r_tds_s_frame_cnt;
assign     tds_scircul_1    =  r_tds_scircul_1;
assign     tds_sc_done_1    =  r_tds_sc_done_1;
assign     tds_total_num_1  =  r_tds_total_num_1;    
  

always@(posedge pixelclk or negedge rstin) begin
    if(!rstin) begin
      r_tds_i_hs  <=  1'b0;    
      r_tds_i_vs  <=  1'b0;
      r_tds_i_de  <=  1'b0;
      r_tds_s_frame_cnt <= 3'd0;
      r_tds_scircul_1 <= 18'd0;
      r_tds_sc_done_1 <= 1'b0;   
      r_tds_total_num_1 <= 4'd0;
    end
    else if(g_s_frame_cnt == 3'd1 && g_no_use == 1'b1 && y_large_g == 1'b0 && p_large_g == 1'b0 && r_large_g == 1'b0 && n_large_g == 1'b0 && py_large_g == 1'b0) begin
      r_tds_i_hs  <=  tb_erosion_hs_g;    
      r_tds_i_vs  <=  tb_erosion_vs_g;
      r_tds_i_de  <=  tb_erosion_de_g;
      r_tds_s_frame_cnt <= g_s_frame_cnt;
      r_tds_scircul_1 <= g_scircul;
      r_tds_sc_done_1 <= g_sc_done;   
      r_tds_total_num_1 <= g_total_num;   
    end    
//    else if(py_s_frame_cnt == 3'd1 && py_no_use == 1'b1 && y_large_g == 1'b0 && p_large_g == 1'b0 && r_large_g == 1'b0 && n_large_g == 1'b0) begin
    else if(py_s_frame_cnt == 3'd1 && py_no_use == 1'b1 && r_large_py == 1'b0 && pk_large_py == 1'b0 && y_large_py == 1'b0) begin
      r_tds_i_hs  <=  tb_erosion_hs_py;    
      r_tds_i_vs  <=  tb_erosion_vs_py;
      r_tds_i_de  <=  tb_erosion_de_py;
      r_tds_s_frame_cnt <= py_s_frame_cnt;
      r_tds_scircul_1 <= py_scircul;
      r_tds_sc_done_1 <= py_sc_done;   
      r_tds_total_num_1 <= py_total_num;   
    end 
    else if(y_s_frame_cnt == 3'd1 && y_no_use == 1'b1 && y_large_g == 1'b1) begin
      r_tds_i_hs  <=  tb_erosion_hs_y;    
      r_tds_i_vs  <=  tb_erosion_vs_y;
      r_tds_i_de  <=  tb_erosion_de_y;
      r_tds_s_frame_cnt <= y_s_frame_cnt;
      r_tds_scircul_1 <= y_scircul;
      r_tds_sc_done_1 <= y_sc_done;   
      r_tds_total_num_1 <= y_total_num;   
    end  
    else if(o_s_frame_cnt == 3'd1 && o_no_use == 1'b1 && p_large_o == 1'b0 && pk_large_o == 1'b0) begin
      r_tds_i_hs  <=  tb_erosion_hs_o;    
      r_tds_i_vs  <=  tb_erosion_vs_o;
      r_tds_i_de  <=  tb_erosion_de_o;
      r_tds_s_frame_cnt <= o_s_frame_cnt;
      r_tds_scircul_1 <= o_scircul;
      r_tds_sc_done_1 <= o_sc_done;   
      r_tds_total_num_1 <= o_total_num;   
    end  
    else if(s_frame_cnt == 3'd1 && no_use == 1'b1) begin
      r_tds_i_hs  <=  erosion_hs;    
      r_tds_i_vs  <=  erosion_vs;
      r_tds_i_de  <=  erosion_de;
      r_tds_s_frame_cnt <= s_frame_cnt;
      r_tds_scircul_1 <= scircul;
      r_tds_sc_done_1 <= sc_done;   
      r_tds_total_num_1 <= total_num;   
    end
    else begin
      r_tds_i_hs  <=  1'b0;    
      r_tds_i_vs  <=  1'b0;
      r_tds_i_de  <=  1'b0;
      r_tds_s_frame_cnt <= 3'd0;
      r_tds_scircul_1 <= 18'd0;
      r_tds_sc_done_1 <= 1'b0;   
      r_tds_total_num_1 <= 4'd0;
    end
end

Type_Distgsh_single #(
    .sub_threshold   (18'd40  ) ,
    .apple_std_value (18'd289 ) ,
    .pear_std_value  (18'd280 ) , //modify
    .banan_std_value (18'd115 ) ,
    .mango_std_value (18'd450 ) , //modify
    .orang_std_value (18'd253 ) ,
    .grape_std_value (18'd529 ) , //modify
    .pitay_std_value (18'd445 ) ,
    .kiwi_std_value  (18'd360 )   //modify
)TDs(
       .pixelclk      (pixelclk      ),
       .reset_n       (rstin         ),
       .i_hs          (r_tds_i_hs    ),
       .i_vs          (r_tds_i_vs    ),
       .i_de          (r_tds_i_de    ),        
       .s_frame_cnt   (r_tds_s_frame_cnt),
       .scircul_1     (r_tds_scircul_1),  //single fruit recongnation
       .sc_done_1     (r_tds_sc_done_1),
       .total_num_1   (r_tds_total_num_1),
       .fruit_num     (fruit_num     ),
       .o_hs          (aftd_hsync    ),
       .o_vs          (aftd_vsync    ),
       .o_de          (aftd_de       ),
       .apple_type_en (apple_type_en ),
       .pear_type_en  (pear_type_en  ),
       .banan_type_en (banan_type_en ),
       .mango_type_en (mango_type_en ),
       .orang_type_en (orang_type_en ),
       .grape_type_en (grape_type_en ),
       .pitay_type_en (pitay_type_en ),
       .kiwi_type_en  (kiwi_type_en  )    
);
/*------------------------------------------------------------

------------------------------------------------------------*/
HVcount#(
     .DW(24),
	 .IW(1024)
      )HVcount(
    .pixelclk(pixelclk),
    .reset_n(rstin),
    .i_data(orign_color),
    .i_binary({afbin_color,afbin_color,afbin_color}),
    .i_hsync(afbin_hsync),
    .i_vsync(afbin_vsync),
    .i_de(afbin_de),
    
    .hcount(hcount),
    .vcount(vcount),
    .o_data(HV_o_rgb),
    .o_binary(HV_dout),
    .o_hsync(HV_o_hsync),
    .o_vsync(HV_o_vsync),
    .o_de(HV_o_de)
    );    

reg     [3:0]    led_r;           //define the first stage register , generate four D Flip-flop 
reg     [3:0]    led_r1;          //define the second stage register ,generate four D Flip-flop
wire    [3:0]    stage_cnt/* synthesis syn_keep=1 */;

key_debounce kk
(
  .sys_clk   (pixelclk    ),
  .rst_n     (rstin       ),
  .key       (key_in[1]   ),
  .led       (stage_cnt   ),
  .button_negedge(),
  .button_posedge()
);

reg    [5:0]    stage   /* synthesis syn_preserve = 1 */;

localparam      s1 = 6'b000001;
localparam      s2 = 6'b000010;
localparam      s3 = 6'b000100;
localparam      s4 = 6'b001000;
localparam      s5 = 6'b010000;
localparam      s6 = 6'b100000;

wire                           dis_hs;
wire                           dis_vs;
wire                           dis_de;
wire[7:0]                      dis_r;
wire[7:0]                      dis_g;
wire[7:0]                      dis_b;

reg                            r_dis_hs/* synthesis syn_preserve = 1 */;
reg                            r_dis_vs/* synthesis syn_preserve = 1 */;
reg                            r_dis_de/* synthesis syn_preserve = 1 */;
reg[7:0]                       r_dis_r/* synthesis syn_preserve = 1 */;
reg[7:0]                       r_dis_g/* synthesis syn_preserve = 1 */;
reg[7:0]                       r_dis_b/* synthesis syn_preserve = 1 */;

assign    dis_hs = r_dis_hs   ;
assign    dis_vs = r_dis_vs   ;
assign    dis_de = r_dis_de   ;
assign    dis_r  = r_dis_r    ;
assign    dis_g  = r_dis_g    ;
assign    dis_b  = r_dis_b    ;

//always @(posedge pixelclk or negedge rstin ) begin
//    if (!rstin)
//        stage_cnt   <=    3'd0   ;
//    else if (led_r1[1] == 1'b1) begin
//        if (stage_cnt == 3'd5)
//           stage_cnt   <=    3'd0   ;
//        else 
//           stage_cnt   <=  stage_cnt + 3'd1;
//    end 
//    else 
//        stage_cnt   <=  stage_cnt ;
//end

always @(posedge pixelclk or negedge rstin ) begin
    if (!rstin) begin
        r_dis_hs   <=    afbin_hsync  ;
        r_dis_vs   <=    afbin_vsync  ;
        r_dis_de   <=    afbin_de     ;
        r_dis_r    <=    afbin_color  ; 
        r_dis_g    <=    afbin_color  ; 
        r_dis_b    <=    afbin_color  ;         
    end
    else if (stage == s1) begin
        r_dis_hs   <=    erosion_hs   ;
        r_dis_vs   <=    erosion_vs   ;
        r_dis_de   <=    erosion_de   ;
        r_dis_r    <=    erosion_data ; 
        r_dis_g    <=    erosion_data ; 
        r_dis_b    <=    erosion_data ;   
    end
    else if (stage == s2) begin
//        r_dis_hs   <=    tb_erosion_hs_g   ;
//        r_dis_vs   <=    tb_erosion_vs_g   ;
//        r_dis_de   <=    tb_erosion_de_g   ;
//        r_dis_r    <=    tb_erosion_data_g ; 
//        r_dis_g    <=    tb_erosion_data_g ; 
//        r_dis_b    <=    tb_erosion_data_g ; 
        r_dis_hs   <=    temp_hs     ;
        r_dis_vs   <=    temp_vs     ;
        r_dis_de   <=    temp_de     ;
        r_dis_r    <=    temp_data_g ; 
        r_dis_g    <=    temp_data_g ; 
        r_dis_b    <=    temp_data_g ; 
    end
    else if (stage == s3) begin
        r_dis_hs   <=    tb_erosion_hs_y   ;
        r_dis_vs   <=    tb_erosion_vs_y   ;
        r_dis_de   <=    tb_erosion_de_y   ;
        r_dis_r    <=    tb_erosion_data_y ; 
        r_dis_g    <=    tb_erosion_data_y ; 
        r_dis_b    <=    tb_erosion_data_y ; 
    end
    else if (stage == s4) begin
        r_dis_hs   <=    tb_erosion_hs_o   ;
        r_dis_vs   <=    tb_erosion_vs_o   ;
        r_dis_de   <=    tb_erosion_de_o   ;
        r_dis_r    <=    tb_erosion_data_o ; 
        r_dis_g    <=    tb_erosion_data_o ; 
        r_dis_b    <=    tb_erosion_data_o ; 
    end
    else if (stage == s5) begin
        r_dis_hs   <=    tb_erosion_hs_py  ;
        r_dis_vs   <=    tb_erosion_vs_py  ;
        r_dis_de   <=    tb_erosion_de_py  ;
        r_dis_r    <=    tb_erosion_data_py; 
        r_dis_g    <=    tb_erosion_data_py; 
        r_dis_b    <=    tb_erosion_data_py; 
    end
end



always @(posedge pixelclk or negedge rstin ) begin
    if (!rstin) 
	   stage <= s1 ;
	else begin
		case (stage)
		   s1 : begin
		       if (stage_cnt == 4'd1)
			      stage <= s2 ;
			   else  
			      stage <= stage ;
		   end
		   s2 : begin
		      if (stage_cnt == 4'd2)
			      stage <= s3 ;
			  else  
			      stage <= stage ;
		   end
		   s3 : begin
		      if (stage_cnt == 4'd3)
			      stage <= s4 ;
			  else  
			      stage <= stage ;		      
		   end
		   s4 : begin
		      if (stage_cnt == 4'd4)
			      stage <= s5 ;
			  else  
			      stage <= stage ;		      
		   end
		   s5 : begin
		      if (stage_cnt == 4'd5)
			      stage <= s6 ;
			  else  
			      stage <= stage ;		      
		   end
		   s6 : begin
			      stage <= s1 ;	      
		   end
		   default : stage <= s1;
	endcase
	end
end

always @(posedge pixelclk or negedge rstin ) begin
    if (!rstin) 
	    THRESHOLD <= 8'd70 ;
	  else if (led_r1[3] == 1'b1)
      THRESHOLD <= THRESHOLD + 8'd5 ;
    else 
      THRESHOLD <= THRESHOLD ;     
end

always@(posedge pixelclk or negedge rstin)
    if(!rstin) begin
      hcount_l<=0;
      hcount_r<=0;
      vcount_l<=0;
      vcount_r<=0;  
  end
  else begin
      hcount_l<=hcount_l_r;
      hcount_r<=hcount_r_r;
      vcount_l<=vcount_l_r;
      vcount_r<=vcount_r_r;
end   
      
display disp(       
      .pixelclk   (pixelclk   ) ,
      .reset_n    (rstin      ) ,             
      .i_rgb      ({dis_r,dis_g,dis_b}) ,
      .i_hsync    (dis_hs     ) ,
      .i_vsync    (dis_vs     ) ,
      .i_de       (dis_de     ) ,                 
      .hcount     (hcount     ) ,
      .vcount     (vcount     ) ,               
      .hcount_l   (hcount_l   ) ,
      .hcount_r   (hcount_r   ) ,
      .vcount_l   (vcount_l   ) ,
      .vcount_r   (vcount_r   ) ,
      .o_rgb      (VGA_rgb    ) ,
      .o_hsync    (VGA_hsync  ) ,
      .o_vsync    (VGA_vsync  ) ,                                                                                                  
      .o_de       (VGA_de     )
 );





endmodule