# Tue May  7 16:40:54 2019


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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03P-Beta2
Install: C:\pango\PDS_2019.1-patch2\syn
OS: Windows 6.1

Hostname: ALINX000007-PC

Implementation : synplify_impl
Synopsys Generic Technology Mapper, Version map2019q1p1, Build 1238R, Built Mar 15 2019 09:38:46


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 119MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 119MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 119MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 123MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 213MB peak: 213MB)

@N: MO111 :|Tristate driver dqs_drift_l_t[0] (in view: work.ipsl_hmemc_phy_top_Z9(verilog)) on net dqs_drift_l[0] (in view: work.ipsl_hmemc_phy_top_Z9(verilog)) has its enable tied to GND.
@N: MO111 :|Tristate driver dqs_drift_l_t[1] (in view: work.ipsl_hmemc_phy_top_Z9(verilog)) on net dqs_drift_l[1] (in view: work.ipsl_hmemc_phy_top_Z9(verilog)) has its enable tied to GND.
@N: MO111 :|Tristate driver dqs_drift_h_t[0] (in view: work.ipsl_hmemc_phy_top_Z9(verilog)) on net dqs_drift_h[0] (in view: work.ipsl_hmemc_phy_top_Z9(verilog)) has its enable tied to GND.
@N: MO111 :|Tristate driver dqs_drift_h_t[1] (in view: work.ipsl_hmemc_phy_top_Z9(verilog)) on net dqs_drift_h[1] (in view: work.ipsl_hmemc_phy_top_Z9(verilog)) has its enable tied to GND.
@N: MO111 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\ipsl_hmemc_top_test.v":42:41:42:48|Tristate driver err_flag (in view: work.ipsl_hmemc_top_test(verilog)) on net err_flag (in view: work.ipsl_hmemc_top_test(verilog)) has its enable tied to GND.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":81:0:81:5|Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_d0[24:0] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.read_len_d0[24:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":81:0:81:5|Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_d1[24:0] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[24:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.

Available hyper_sources - for debug and ip models
	None Found

@N: MT204 |Auto Constrain mode is disabled because clocks are defined in the SDC file

            sys_clk


Finished RTL optimizations (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 222MB peak: 222MB)

@N: MO231 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\aq_axi_master.v":170:2:170:7|Found counter in view:work.ipsl_hmemc_top_test(verilog) instance u_aq_axi_master.reg_w_len[7:0] 
@N: MO231 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\aq_axi_master.v":342:2:342:7|Found counter in view:work.ipsl_hmemc_top_test(verilog) instance u_aq_axi_master.reg_r_len[7:0] 
@N: MO231 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\aq_axi_master.v":150:0:150:5|Found counter in view:work.ipsl_hmemc_top_test(verilog) instance u_aq_axi_master.rd_fifo_cnt[31:0] 
@N: MO231 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Found counter in view:work.ipsl_hmemc_top_test(verilog) instance frame_read_write_m0.frame_fifo_read_m0.read_cnt[24:6] 
@N: MO231 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Found counter in view:work.ipsl_hmemc_top_test(verilog) instance frame_read_write_m0.frame_fifo_write_m0.write_cnt[24:6] 
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\video_timing_data.v":83:0:83:5|Removing sequential instance video_timing_data_m0.vout_data_r[24] (in view: work.ipsl_hmemc_top_test(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\video_timing_data.v":83:0:83:5|Removing sequential instance video_timing_data_m0.vout_data_r[25] (in view: work.ipsl_hmemc_top_test(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\video_timing_data.v":83:0:83:5|Removing sequential instance video_timing_data_m0.vout_data_r[26] (in view: work.ipsl_hmemc_top_test(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\video_timing_data.v":83:0:83:5|Removing sequential instance video_timing_data_m0.vout_data_r[27] (in view: work.ipsl_hmemc_top_test(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\video_timing_data.v":83:0:83:5|Removing sequential instance video_timing_data_m0.vout_data_r[28] (in view: work.ipsl_hmemc_top_test(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\video_timing_data.v":83:0:83:5|Removing sequential instance video_timing_data_m0.vout_data_r[29] (in view: work.ipsl_hmemc_top_test(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\video_timing_data.v":83:0:83:5|Removing sequential instance video_timing_data_m0.vout_data_r[30] (in view: work.ipsl_hmemc_top_test(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\video_timing_data.v":83:0:83:5|Removing sequential instance video_timing_data_m0.vout_data_r[31] (in view: work.ipsl_hmemc_top_test(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@W: MO129 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":82:0:82:5|Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[0] is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":82:0:82:5|Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[1] is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":82:0:82:5|Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[2] is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":82:0:82:5|Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[3] is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":82:0:82:5|Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[4] is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":82:0:82:5|Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[5] is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":82:0:82:5|Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[6] is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":82:0:82:5|Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[7] is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":82:0:82:5|Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[8] is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":82:0:82:5|Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[9] is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":82:0:82:5|Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[10] is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":82:0:82:5|Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[11] is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":82:0:82:5|Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[12] is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":82:0:82:5|Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[13] is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":82:0:82:5|Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[14] is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":82:0:82:5|Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[15] is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":82:0:82:5|Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[16] is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":82:0:82:5|Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[19] is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":82:0:82:5|Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[20] is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":82:0:82:5|Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[21] is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":82:0:82:5|Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[22] is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":82:0:82:5|Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[23] is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":82:0:82:5|Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[24] is reduced to a combinational gate by constant propagation.
@N: MF179 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\aq_axi_master.v":166:24:166:59|Found 32 by 32 bit equality operator ('==') u_aq_axi_master.un1_rd_fifo_cnt_1 (in view: work.ipsl_hmemc_top_test(verilog))
@W: MO160 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Register bit frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[5] (in view view:work.ipsl_hmemc_top_test(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Register bit frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[4] (in view view:work.ipsl_hmemc_top_test(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Register bit frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[3] (in view view:work.ipsl_hmemc_top_test(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Register bit frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[2] (in view view:work.ipsl_hmemc_top_test(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Register bit frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[1] (in view view:work.ipsl_hmemc_top_test(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Register bit frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[0] (in view view:work.ipsl_hmemc_top_test(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Register bit frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[5] (in view view:work.ipsl_hmemc_top_test(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Register bit frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[4] (in view view:work.ipsl_hmemc_top_test(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Register bit frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[3] (in view view:work.ipsl_hmemc_top_test(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Register bit frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[2] (in view view:work.ipsl_hmemc_top_test(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Register bit frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[1] (in view view:work.ipsl_hmemc_top_test(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Register bit frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[0] (in view view:work.ipsl_hmemc_top_test(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[0] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[1] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[2] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[3] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[4] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[5] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[6] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[7] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[8] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[9] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[10] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[11] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[12] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[13] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[14] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[15] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[16] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[19] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[20] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[21] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[22] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[23] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[24] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[0] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[1] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[2] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[3] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[4] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[5] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[6] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[7] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[8] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[9] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[10] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[11] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[12] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[13] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[14] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[15] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[16] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[19] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[20] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[21] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[22] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[23] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[24] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":82:0:82:5|Removing instance frame_read_write_m0.frame_fifo_read_m0.read_len_d0[18] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.read_len_d0[17]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":82:0:82:5|Removing instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[18] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[17]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[18] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[17]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[18] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[17]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N: MO231 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\ax_debounce.v":73:0:73:5|Found counter in view:work.ax_debounce(verilog) instance q_reg[31:0] 
@N: MO231 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\bmp_read.v":143:0:143:5|Found counter in view:work.bmp_read(verilog) instance bmp_len_cnt[31:0] 
@N: MO231 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\bmp_read.v":85:0:85:5|Found counter in view:work.bmp_read(verilog) instance rd_cnt[9:0] 
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_sec_read_write.v":92:0:92:5|Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[15] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_sec_read_write.v":92:0:92:5|Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[14] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_sec_read_write.v":92:0:92:5|Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[13] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_sec_read_write.v":92:0:92:5|Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[12] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_sec_read_write.v":92:0:92:5|Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[11] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_sec_read_write.v":92:0:92:5|Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[9] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_sec_read_write.v":92:0:92:5|Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[8] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_sec_read_write.v":92:0:92:5|Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[2] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_sec_read_write.v":92:0:92:5|Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[1] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_sec_read_write.v":92:0:92:5|Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[10] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_sec_read_write.v":92:0:92:5|Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[7] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_sec_read_write.v":92:0:92:5|Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[6] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_sec_read_write.v":92:0:92:5|Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[5] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_sec_read_write.v":92:0:92:5|Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[4] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_sec_read_write.v":92:0:92:5|Removing sequential instance sd_card_sec_read_write_m0.spi_clk_div[0] (in view: work.sd_card_top(verilog)) because it does not drive other instances.
@N: MO231 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_cmd.v":90:0:90:5|Found counter in view:work.sd_card_cmd(verilog) instance byte_cnt[15:0] 
@N: MO231 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_cmd.v":90:0:90:5|Found counter in view:work.sd_card_cmd(verilog) instance wr_data_cnt[9:0] 
@N: MF179 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_cmd.v":212:8:212:40|Found 16 by 16 bit equality operator ('==') state56 (in view: work.sd_card_cmd(verilog))
@N: MO231 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\spi_master.v":119:0:119:5|Found counter in view:work.spi_master(verilog) instance clk_cnt[15:0] 
@N: MO231 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\spi_master.v":129:0:129:5|Found counter in view:work.spi_master(verilog) instance clk_edge_cnt[4:0] 
@N: MF179 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\spi_master.v":82:6:82:24|Found 16 by 16 bit equality operator ('==') next_state15 (in view: work.spi_master(verilog))
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\encode.v":151:2:151:7|Removing sequential instance dout[0] (in view: work.encode_0_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\encode.v":151:2:151:7|Removing sequential instance dout[1] (in view: work.encode_0_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\encode.v":135:2:135:7|Removing sequential instance q_m_reg[0] (in view: work.encode_0_0(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\encode.v":135:2:135:7|Removing sequential instance q_m_reg[1] (in view: work.encode_0_0(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\serdes_4b_10to1.v":48:0:48:5|Removing instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_3l[4] because it is equivalent to instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_3h[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\serdes_4b_10to1.v":48:0:48:5|Removing instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_3l[3] because it is equivalent to instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_3h[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N: MF179 :|Found 9 by 9 bit equality operator ('==') ASYN_CTRL\.asyn_rempty_2 (in view: work.ipml_fifo_ctrl_v1_3_9s_8s_ASYN_508s_4s(verilog))
@N: MF179 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":207:32:207:90|Found 9 by 9 bit equality operator ('==') ASYN_CTRL\.un8_asyn_wfull (in view: work.ipml_fifo_ctrl_v1_3_9s_8s_ASYN_508s_4s(verilog))
@N: MF179 :|Found 10 by 10 bit equality operator ('==') ASYN_CTRL\.asyn_rempty_5 (in view: work.ipml_fifo_ctrl_v1_3_8s_9s_ASYN_252s_4s(verilog))
@N: MO231 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_reset_ctrl.v":52:0:52:5|Found counter in view:work.ipsl_ddrphy_reset_ctrl(verilog) instance cnt[7:0] 
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":293:0:293:5|Removing instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.ddrphy_update_comp_val_l[1] because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.ddrphy_update_comp_val_h[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N: MO231 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":121:0:121:5|Found counter in view:work.ipsl_ddrphy_update_ctrl_16BIT_2s_0s_1s_2s_3s_1(verilog) instance dqs_drift_h_cnt[7:0] 
@N: MO231 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":102:0:102:5|Found counter in view:work.ipsl_ddrphy_update_ctrl_16BIT_2s_0s_1s_2s_3s_1(verilog) instance dqs_drift_l_cnt[7:0] 
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":293:0:293:5|Removing sequential instance ddrphy_update_comp_val_h[1] (in view: work.ipsl_ddrphy_update_ctrl_16BIT_2s_0s_1s_2s_3s_1(verilog)) because it does not drive other instances.
@N: MO231 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_reset_ctrl.v":113:0:113:5|Found counter in view:work.ipsl_hmemc_ddrc_top_Z12(verilog) instance u_ipsl_ddrc_reset_ctrl.ddrc_rst_cnt[4:0] 
@N: MO231 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_reset_ctrl.v":86:0:86:5|Found counter in view:work.ipsl_hmemc_ddrc_top_Z12(verilog) instance u_ipsl_ddrc_reset_ctrl.rst_cnt[4:0] 
@N: MO231 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_apb_reset.v":387:0:387:5|Found counter in view:work.ipsl_ddrc_apb_reset_Z10(verilog) instance cnt[6:0] 

Starting factoring (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:06s; Memory used current: 227MB peak: 227MB)

@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_cmd.v":90:0:90:5|Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[15] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_cmd.v":90:0:90:5|Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[14] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_cmd.v":90:0:90:5|Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[13] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_cmd.v":90:0:90:5|Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[12] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_cmd.v":90:0:90:5|Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[11] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_cmd.v":90:0:90:5|Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[9] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_cmd.v":90:0:90:5|Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[8] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_cmd.v":90:0:90:5|Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[2] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_cmd.v":90:0:90:5|Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[1] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_cmd.v":90:0:90:5|Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[10] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_cmd.v":90:0:90:5|Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[7] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_cmd.v":90:0:90:5|Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[6] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_cmd.v":90:0:90:5|Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[5] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_cmd.v":90:0:90:5|Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[4] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_cmd.v":90:0:90:5|Removing sequential instance sd_card_top_m0.sd_card_cmd_m0.clk_div[0] (in view: work.sd_card_bmp(verilog)) because it does not drive other instances.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":121:0:121:5|Removing instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_h_d1[1] because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_h_d1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":102:0:102:5|Removing instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_l_d1[1] because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_h_d1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":102:0:102:5|Removing instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_l_d1[0] because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_h_d1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":121:0:121:5|Removing instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_h_now[1] because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_h_now[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":102:0:102:5|Removing instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_l_now[1] because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_l_now[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":293:0:293:5|Removing instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_h_last[1] because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_h_last[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":293:0:293:5|Removing instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_l_last[1] because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_l_last[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":293:0:293:5|Removing instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.ddrphy_update_comp_dir_l because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.ddrphy_update_comp_dir_h. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":121:0:121:5|Removing sequential instance u_ddrphy_update_ctrl.dqs_drift_h_d1[0] (in view: work.ipsl_hmemc_phy_top_Z9(verilog)) because it does not drive other instances.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\encode.v":135:2:135:7|Removing instance dvi_encoder_m0.encr.de_q because it is equivalent to instance dvi_encoder_m0.encg.de_q. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\encode.v":135:2:135:7|Removing instance dvi_encoder_m0.encg.de_q because it is equivalent to instance dvi_encoder_m0.encb.de_q. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\encode.v":135:2:135:7|Removing instance dvi_encoder_m0.encr.de_reg because it is equivalent to instance dvi_encoder_m0.encg.de_reg. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\encode.v":135:2:135:7|Removing instance dvi_encoder_m0.encg.de_reg because it is equivalent to instance dvi_encoder_m0.encb.de_reg. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":370:0:370:5|Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rd_water_level[0] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":370:0:370:5|Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rd_water_level[1] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":370:0:370:5|Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rd_water_level[2] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":370:0:370:5|Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rd_water_level[3] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":370:0:370:5|Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rd_water_level[4] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":370:0:370:5|Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rd_water_level[5] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":349:0:349:5|Removing sequential instance frame_read_write_m0.read_buf.U_ipml_fifo_afifo_64i_32o_128.U_ipml_fifo_ctrl.wr_water_level[0] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":349:0:349:5|Removing sequential instance frame_read_write_m0.read_buf.U_ipml_fifo_afifo_64i_32o_128.U_ipml_fifo_ctrl.wr_water_level[1] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":349:0:349:5|Removing sequential instance frame_read_write_m0.read_buf.U_ipml_fifo_afifo_64i_32o_128.U_ipml_fifo_ctrl.wr_water_level[2] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":349:0:349:5|Removing sequential instance frame_read_write_m0.read_buf.U_ipml_fifo_afifo_64i_32o_128.U_ipml_fifo_ctrl.wr_water_level[3] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":349:0:349:5|Removing sequential instance frame_read_write_m0.read_buf.U_ipml_fifo_afifo_64i_32o_128.U_ipml_fifo_ctrl.wr_water_level[4] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":349:0:349:5|Removing sequential instance frame_read_write_m0.read_buf.U_ipml_fifo_afifo_64i_32o_128.U_ipml_fifo_ctrl.wr_water_level[5] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
Auto Dissolve of u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top (inst of view:work.ipsl_hmemc_phy_top_Z9(verilog))

Finished factoring (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:06s; Memory used current: 238MB peak: 238MB)

@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":106:8:106:13|Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0_0[1] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":106:8:106:13|Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0_0[2] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":106:8:106:13|Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0_0[3] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":106:8:106:13|Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0_0[4] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":106:8:106:13|Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0_0[5] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":106:8:106:13|Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0_0[6] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":106:8:106:13|Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0_0[7] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":106:8:106:13|Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0_0[8] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":106:8:106:13|Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0_0[9] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":106:8:106:13|Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0[1] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":106:8:106:13|Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0[2] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":106:8:106:13|Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0[3] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":106:8:106:13|Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0[4] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":106:8:106:13|Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0[5] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":106:8:106:13|Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0[6] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":106:8:106:13|Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0[7] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":106:8:106:13|Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0[8] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v":106:8:106:13|Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0[9] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\color_bar.v":205:0:205:5|Removing sequential instance video_timing_data_m0.color_bar_m0.h_cnt_0[6] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\color_bar.v":205:0:205:5|Removing sequential instance video_timing_data_m0.color_bar_m0.h_cnt_0[7] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\color_bar.v":205:0:205:5|Removing sequential instance video_timing_data_m0.color_bar_m0.h_cnt_0[8] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\color_bar.v":205:0:205:5|Removing sequential instance video_timing_data_m0.color_bar_m0.h_cnt_0[9] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\color_bar.v":205:0:205:5|Removing sequential instance video_timing_data_m0.color_bar_m0.h_cnt_0[10] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\color_bar.v":205:0:205:5|Removing sequential instance video_timing_data_m0.color_bar_m0.h_cnt_0[11] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\color_bar.v":205:0:205:5|Removing sequential instance video_timing_data_m0.color_bar_m0.h_cnt_1[6] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\color_bar.v":205:0:205:5|Removing sequential instance video_timing_data_m0.color_bar_m0.h_cnt_1[7] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.

Only the first 100 messages of id 'BN362' are reported. To see all messages use 'report_messages -log D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\synthesize\synplify_impl\synlog\synplify_fpga_mapper.srr -id BN362' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {BN362} -count unlimited' in the Tcl shell.

Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:10s; Memory used current: 373MB peak: 373MB)

@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[0] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[1] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[2] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[3] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[4] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[5] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[6] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[7] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[8] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[9] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[9]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[10] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[11] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[12] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[13] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[14] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[15] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[16] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[16]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[17] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[17]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v":107:0:107:5|Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[18] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[18]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[0] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[1] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[2] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[3] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[4] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[5] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[6] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[7] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[8] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[9] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[9]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[10] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[11] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[12] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[13] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[14] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[15] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[16] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[16]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[17] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[17]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v":106:0:106:5|Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[18] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[18]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\bmp_read.v":202:0:202:5|Removing instance sd_card_bmp_m0.bmp_read_m0.sd_sec_read_addr_0[0] because it is equivalent to instance sd_card_bmp_m0.bmp_read_m0.sd_sec_read_addr[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\bmp_read.v":202:0:202:5|Removing instance sd_card_bmp_m0.bmp_read_m0.sd_sec_read_addr_0[1] because it is equivalent to instance sd_card_bmp_m0.bmp_read_m0.sd_sec_read_addr[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\bmp_read.v":202:0:202:5|Removing instance sd_card_bmp_m0.bmp_read_m0.sd_sec_read_addr_0[2] because it is equivalent to instance sd_card_bmp_m0.bmp_read_m0.sd_sec_read_addr[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\color_bar.v":225:0:225:5|Removing instance video_timing_data_m0.color_bar_m0.v_cnt_0[1] because it is equivalent to instance video_timing_data_m0.color_bar_m0.v_cnt[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\color_bar.v":225:0:225:5|Removing instance video_timing_data_m0.color_bar_m0.v_cnt_0[2] because it is equivalent to instance video_timing_data_m0.color_bar_m0.v_cnt[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\color_bar.v":225:0:225:5|Removing instance video_timing_data_m0.color_bar_m0.v_cnt_0[5] because it is equivalent to instance video_timing_data_m0.color_bar_m0.v_cnt[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\color_bar.v":225:0:225:5|Removing instance video_timing_data_m0.color_bar_m0.v_cnt_0[8] because it is equivalent to instance video_timing_data_m0.color_bar_m0.v_cnt[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\color_bar.v":225:0:225:5|Removing instance video_timing_data_m0.color_bar_m0.v_cnt_0[9] because it is equivalent to instance video_timing_data_m0.color_bar_m0.v_cnt[9]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\aq_axi_master.v":342:2:342:7|Removing instance u_aq_axi_master.reg_rd_adrs_0[0] because it is equivalent to instance u_aq_axi_master.reg_rd_adrs[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\aq_axi_master.v":342:2:342:7|Removing instance u_aq_axi_master.reg_rd_adrs_0[1] because it is equivalent to instance u_aq_axi_master.reg_rd_adrs[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\aq_axi_master.v":342:2:342:7|Removing instance u_aq_axi_master.reg_rd_adrs_0[2] because it is equivalent to instance u_aq_axi_master.reg_rd_adrs[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\aq_axi_master.v":342:2:342:7|Removing instance u_aq_axi_master.reg_rd_adrs_0[3] because it is equivalent to instance u_aq_axi_master.reg_rd_adrs[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\aq_axi_master.v":342:2:342:7|Removing instance u_aq_axi_master.reg_rd_adrs_0[4] because it is equivalent to instance u_aq_axi_master.reg_rd_adrs[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.

Only the first 100 messages of id 'BN132' are reported. To see all messages use 'report_messages -log D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\synthesize\synplify_impl\synlog\synplify_fpga_mapper.srr -id BN132' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {BN132} -count unlimited' in the Tcl shell.

Starting Early Timing Optimization (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:11s; Memory used current: 373MB peak: 373MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:12s; Memory used current: 373MB peak: 374MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:13s; Memory used current: 373MB peak: 374MB)

@W: FX553 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_apb_reset.v":115:15:115:18|Could not implement Block ROM for u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.data_2[43:3].
@N: FX214 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_apb_reset.v":115:15:115:18|Generating ROM u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.data_2[43:3] (in view: work.ipsl_hmemc_ddrc_top_Z12(verilog)).

Finished preparing to map (Real Time elapsed 0h:00m:19s; CPU Time elapsed 0h:00m:15s; Memory used current: 374MB peak: 374MB)


Finished technology mapping (Real Time elapsed 0h:00m:20s; CPU Time elapsed 0h:00m:16s; Memory used current: 421MB peak: 421MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:16s		    13.14ns		1952 /      1168

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:21s; CPU Time elapsed 0h:00m:17s; Memory used current: 421MB peak: 421MB)

@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  

Finished restoring hierarchy (Real Time elapsed 0h:00m:30s; CPU Time elapsed 0h:00m:23s; Memory used current: 422MB peak: 422MB)


Start Writing Netlists (Real Time elapsed 0h:00m:31s; CPU Time elapsed 0h:00m:24s; Memory used current: 349MB peak: 423MB)

Writing Analyst data base D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\synthesize\synplify_impl\synwork\synplify_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:40s; CPU Time elapsed 0h:00m:31s; Memory used current: 436MB peak: 436MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:42s; CPU Time elapsed 0h:00m:33s; Memory used current: 460MB peak: 460MB)

@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:43s; CPU Time elapsed 0h:00m:33s; Memory used current: 460MB peak: 460MB)


Start final timing analysis (Real Time elapsed 0h:00m:43s; CPU Time elapsed 0h:00m:34s; Memory used current: 418MB peak: 460MB)

@N: MT615 |Found clock sys_clk with period 20.00ns 
@W: MT420 |Found inferred clock pll_50_400|clkout3_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_pll_50_400.ui_clk[0].
@W: MT420 |Found inferred clock pll_50_400|clkout1_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_pll_50_400.pll_pclk.
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|IOCLK_DIV_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrc_core_clk.
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[0] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_dqs_clk_regional[0].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|ioclk_01_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclk_01.
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[1] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_dqs_clk_regional[1].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[2] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_dqs_clk_regional[2].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[3] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_dqs_clk_regional[3].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|ioclk_02_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclk_02.
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[4] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_dqs_clk_regional[4].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|dqs0_clk_r_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_clk_r.
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[2] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[2].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|dqs_clkw290_0_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw290_0.
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[3] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[3].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|dqs_90_0_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_90_0.
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[4] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[4].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[5] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[5].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[6] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[6].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[7] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[7].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[9] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[9].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|dqs_clkw_0_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw_0.
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[10] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[10].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[11] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[11].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[12] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[12].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|dqs_ca_clk_r_01_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_ca_clk_r_01.
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[17] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[17].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|dqs_clkw_ca_01_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw_ca_01.
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[18] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[18].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[19] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[19].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[20] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[20].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[21] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[21].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[22] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[22].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[23] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[23].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[24] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[24].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[25] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[25].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[27] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[27].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|dqs_90_1_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_90_1.
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|dqs1_clk_r_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_clk_r.
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|dqs_clkw290_1_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw290_1.
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[28] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[28].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[29] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[29].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[31] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[31].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|dqs_clkw_1_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw_1.
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[32] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[32].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[33] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[33].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[34] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[34].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[35] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[35].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[36] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[36].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[37] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[37].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|dqs_ca_clk_r_03_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_ca_clk_r_03.
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[40] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[40].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|dqs_clkw_ca_03_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw_ca_03.
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[41] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[41].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[42] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[42].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[43] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[43].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[44] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[44].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[45] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[45].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[46] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[46].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[47] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[47].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[48] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[48].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[49] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[49].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[51] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[51].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[52] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[52].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|dqs_ca_clk_r_04_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_ca_clk_r_04.
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[55] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[55].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|dqs_clkw_ca_04_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw_ca_04.
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[56] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[56].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[57] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[57].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[58] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[58].
@W: MT420 |Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[59] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[59].
@W: MT420 |Found inferred clock ipsl_ddrphy_dll_update_ctrl|dll_update_n_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_dll_update_ctrl.dll_update_n[0].
@W: MT420 |Found inferred clock video_pll|clkout0_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net video_pll_m0.video_clk[0].
@W: MT420 |Found inferred clock video_pll|clkout1_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net video_pll_m0.video_clk5x.


##### START OF TIMING REPORT #####[
# Timing report written on Tue May  7 16:41:38 2019
#


Top view:               ipsl_hmemc_top_test
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        3
Constraint File(s):    D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\ddr_324_left.fdc
                       
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.



Performance Summary
*******************


Worst slack in design: 14.934

                                                             Requested     Estimated      Requested     Estimated                 Clock        Clock               
Starting Clock                                               Frequency     Frequency      Period        Period        Slack       Type         Group               
-------------------------------------------------------------------------------------------------------------------------------------------------------------------
ipsl_ddrphy_dll_update_ctrl|dll_update_n_inferred_clock      1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_70
ipsl_phy_io_Z8|IOCLK_DIV_inferred_clock                      1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_2 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[2]              1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_11
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[3]              1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_13
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[4]              1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_15
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[5]              1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_16
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[6]              1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_17
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[7]              1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_18
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[9]              1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_19
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[10]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_21
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[11]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_22
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[12]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_23
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[17]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_25
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[18]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_27
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[19]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_28
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[20]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_29
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[21]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_30
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[22]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_31
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[23]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_32
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[24]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_33
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[25]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_34
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[27]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_35
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[28]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_39
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[29]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_40
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[31]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_41
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[32]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_43
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[33]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_44
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[34]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_45
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[35]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_46
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[36]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_47
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[37]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_48
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[40]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_50
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[41]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_52
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[42]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_53
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[43]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_54
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[44]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_55
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[45]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_56
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[46]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_57
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[47]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_58
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[48]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_59
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[49]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_60
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[51]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_61
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[52]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_62
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[55]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_64
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[56]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_66
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[57]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_67
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[58]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_68
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[59]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_69
ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[0]     1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_3 
ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[1]     1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_5 
ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[2]     1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_6 
ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[3]     1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_7 
ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[4]     1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_9 
ipsl_phy_io_Z8|dqs0_clk_r_inferred_clock                     1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_10
ipsl_phy_io_Z8|dqs1_clk_r_inferred_clock                     1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_37
ipsl_phy_io_Z8|dqs_90_0_inferred_clock                       1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_14
ipsl_phy_io_Z8|dqs_90_1_inferred_clock                       1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_36
ipsl_phy_io_Z8|dqs_ca_clk_r_01_inferred_clock                1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_24
ipsl_phy_io_Z8|dqs_ca_clk_r_03_inferred_clock                1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_49
ipsl_phy_io_Z8|dqs_ca_clk_r_04_inferred_clock                1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_63
ipsl_phy_io_Z8|dqs_clkw290_0_inferred_clock                  1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_12
ipsl_phy_io_Z8|dqs_clkw290_1_inferred_clock                  1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_38
ipsl_phy_io_Z8|dqs_clkw_0_inferred_clock                     1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_20
ipsl_phy_io_Z8|dqs_clkw_1_inferred_clock                     1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_42
ipsl_phy_io_Z8|dqs_clkw_ca_01_inferred_clock                 1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_26
ipsl_phy_io_Z8|dqs_clkw_ca_03_inferred_clock                 1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_51
ipsl_phy_io_Z8|dqs_clkw_ca_04_inferred_clock                 1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_65
ipsl_phy_io_Z8|ioclk_01_inferred_clock                       1.0 MHz       1008.1 MHz     1000.000      0.992         999.008     inferred     Inferred_clkgroup_4 
ipsl_phy_io_Z8|ioclk_02_inferred_clock                       1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_8 
pll_50_400|clkout1_inferred_clock                            1.0 MHz       120.6 MHz      1000.000      8.294         991.706     inferred     Inferred_clkgroup_1 
pll_50_400|clkout3_inferred_clock                            1.0 MHz       150.7 MHz      1000.000      6.636         993.364     inferred     Inferred_clkgroup_0 
sys_clk                                                      50.0 MHz      197.4 MHz      20.000        5.066         14.934      declared     default_clkgroup    
video_pll|clkout0_inferred_clock                             1.0 MHz       179.2 MHz      1000.000      5.580         994.419     inferred     Inferred_clkgroup_71
video_pll|clkout1_inferred_clock                             1.0 MHz       734.4 MHz      1000.000      1.362         998.638     inferred     Inferred_clkgroup_72
System                                                       1.0 MHz       780.5 MHz      1000.000      1.281         998.719     system       system_clkgroup     
===================================================================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform





Clock Relationships
*******************

Clocks                                                                                                            |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                                 Ending                                                   |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                                   System                                                   |  1000.000    998.719  |  No paths    -      |  No paths    -      |  No paths    -    
System                                                   pll_50_400|clkout1_inferred_clock                        |  1000.000    999.731  |  No paths    -      |  No paths    -      |  No paths    -    
System                                                   ipsl_ddrphy_dll_update_ctrl|dll_update_n_inferred_clock  |  1000.000    999.731  |  No paths    -      |  No paths    -      |  No paths    -    
sys_clk                                                  sys_clk                                                  |  20.000      14.934   |  No paths    -      |  No paths    -      |  No paths    -    
sys_clk                                                  pll_50_400|clkout3_inferred_clock                        |  Diff grp    -        |  No paths    -      |  No paths    -      |  No paths    -    
pll_50_400|clkout3_inferred_clock                        sys_clk                                                  |  Diff grp    -        |  No paths    -      |  No paths    -      |  No paths    -    
pll_50_400|clkout3_inferred_clock                        pll_50_400|clkout3_inferred_clock                        |  1000.000    993.364  |  No paths    -      |  No paths    -      |  No paths    -    
pll_50_400|clkout3_inferred_clock                        video_pll|clkout0_inferred_clock                         |  Diff grp    -        |  No paths    -      |  No paths    -      |  No paths    -    
pll_50_400|clkout1_inferred_clock                        System                                                   |  1000.000    999.133  |  No paths    -      |  No paths    -      |  No paths    -    
pll_50_400|clkout1_inferred_clock                        pll_50_400|clkout1_inferred_clock                        |  1000.000    991.706  |  No paths    -      |  No paths    -      |  No paths    -    
pll_50_400|clkout1_inferred_clock                        ipsl_phy_io_Z8|IOCLK_DIV_inferred_clock                  |  Diff grp    -        |  No paths    -      |  No paths    -      |  No paths    -    
ipsl_phy_io_Z8|IOCLK_DIV_inferred_clock                  pll_50_400|clkout1_inferred_clock                        |  Diff grp    -        |  No paths    -      |  No paths    -      |  No paths    -    
ipsl_phy_io_Z8|ioclk_01_inferred_clock                   ipsl_phy_io_Z8|ioclk_01_inferred_clock                   |  1000.000    999.008  |  No paths    -      |  No paths    -      |  No paths    -    
ipsl_ddrphy_dll_update_ctrl|dll_update_n_inferred_clock  pll_50_400|clkout1_inferred_clock                        |  Diff grp    -        |  No paths    -      |  No paths    -      |  No paths    -    
video_pll|clkout0_inferred_clock                         pll_50_400|clkout3_inferred_clock                        |  Diff grp    -        |  No paths    -      |  No paths    -      |  No paths    -    
video_pll|clkout0_inferred_clock                         video_pll|clkout0_inferred_clock                         |  1000.000    994.420  |  No paths    -      |  No paths    -      |  No paths    -    
video_pll|clkout0_inferred_clock                         video_pll|clkout1_inferred_clock                         |  Diff grp    -        |  No paths    -      |  No paths    -      |  No paths    -    
video_pll|clkout1_inferred_clock                         video_pll|clkout1_inferred_clock                         |  1000.000    998.638  |  No paths    -      |  No paths    -      |  No paths    -    
==========================================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: ipsl_phy_io_Z8|ioclk_01_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                                 Starting                                                                                               Arrival            
Instance                                                         Reference                                  Type           Pin                Net                       Time        Slack  
                                                                 Clock                                                                                                                     
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut     ipsl_phy_io_Z8|ioclk_01_inferred_clock     GTP_DDC_E1     IFIFO_RADDR[0]     dqs_ififo_rpoint_0[0]     0.464       999.008
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut     ipsl_phy_io_Z8|ioclk_01_inferred_clock     GTP_DDC_E1     IFIFO_RADDR[1]     dqs_ififo_rpoint_0[1]     0.464       999.008
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut     ipsl_phy_io_Z8|ioclk_01_inferred_clock     GTP_DDC_E1     IFIFO_RADDR[2]     dqs_ififo_rpoint_0[2]     0.464       999.008
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut     ipsl_phy_io_Z8|ioclk_01_inferred_clock     GTP_DDC_E1     IFIFO_RADDR[0]     dqs_ififo_rpoint_1[0]     0.464       999.008
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut     ipsl_phy_io_Z8|ioclk_01_inferred_clock     GTP_DDC_E1     IFIFO_RADDR[1]     dqs_ififo_rpoint_1[1]     0.464       999.008
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut     ipsl_phy_io_Z8|ioclk_01_inferred_clock     GTP_DDC_E1     IFIFO_RADDR[2]     dqs_ififo_rpoint_1[2]     0.464       999.008
===========================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                      Starting                                                                                          Required            
Instance                                                              Reference                                  Type            Pin          Net                       Time         Slack  
                                                                      Clock                                                                                                                 
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut     ipsl_phy_io_Z8|ioclk_01_inferred_clock     GTP_ISERDES     RADDR[0]     dqs_ififo_rpoint_0[0]     999.880      999.008
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut     ipsl_phy_io_Z8|ioclk_01_inferred_clock     GTP_ISERDES     RADDR[1]     dqs_ififo_rpoint_0[1]     999.880      999.008
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut     ipsl_phy_io_Z8|ioclk_01_inferred_clock     GTP_ISERDES     RADDR[2]     dqs_ififo_rpoint_0[2]     999.880      999.008
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr4_dut     ipsl_phy_io_Z8|ioclk_01_inferred_clock     GTP_ISERDES     RADDR[0]     dqs_ififo_rpoint_0[0]     999.880      999.008
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr4_dut     ipsl_phy_io_Z8|ioclk_01_inferred_clock     GTP_ISERDES     RADDR[1]     dqs_ififo_rpoint_0[1]     999.880      999.008
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr4_dut     ipsl_phy_io_Z8|ioclk_01_inferred_clock     GTP_ISERDES     RADDR[2]     dqs_ififo_rpoint_0[2]     999.880      999.008
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr5_dut     ipsl_phy_io_Z8|ioclk_01_inferred_clock     GTP_ISERDES     RADDR[0]     dqs_ififo_rpoint_0[0]     999.880      999.008
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr5_dut     ipsl_phy_io_Z8|ioclk_01_inferred_clock     GTP_ISERDES     RADDR[1]     dqs_ififo_rpoint_0[1]     999.880      999.008
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr5_dut     ipsl_phy_io_Z8|ioclk_01_inferred_clock     GTP_ISERDES     RADDR[2]     dqs_ififo_rpoint_0[2]     999.880      999.008
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr6_dut     ipsl_phy_io_Z8|ioclk_01_inferred_clock     GTP_ISERDES     RADDR[0]     dqs_ififo_rpoint_0[0]     999.880      999.008
============================================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      1000.000
    - Setup time:                            0.120
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         999.880

    - Propagation time:                      0.872
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 999.008

    Number of logic level(s):                0
    Starting point:                          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut / IFIFO_RADDR[0]
    Ending point:                            u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut / RADDR[0]
    The start point is clocked by            ipsl_phy_io_Z8|ioclk_01_inferred_clock [rising] on pin CLKA
    The end   point is clocked by            ipsl_phy_io_Z8|ioclk_01_inferred_clock [rising] on pin DESCLK

Instance / Net                                                                        Pin                Pin               Arrival     No. of    
Name                                                                  Type            Name               Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut          GTP_DDC_E1      IFIFO_RADDR[0]     Out     0.464     0.464       -         
dqs_ififo_rpoint_0[0]                                                 Net             -                  -       0.408     -           8         
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut     GTP_ISERDES     RADDR[0]           In      -         0.872       -         
=================================================================================================================================================
Total path delay (propagation time + setup) of 0.992 is 0.584(58.9%) logic and 0.408(41.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      1000.000
    - Setup time:                            0.120
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         999.880

    - Propagation time:                      0.872
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 999.008

    Number of logic level(s):                0
    Starting point:                          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut / IFIFO_RADDR[1]
    Ending point:                            u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut / RADDR[1]
    The start point is clocked by            ipsl_phy_io_Z8|ioclk_01_inferred_clock [rising] on pin CLKA
    The end   point is clocked by            ipsl_phy_io_Z8|ioclk_01_inferred_clock [rising] on pin DESCLK

Instance / Net                                                                        Pin                Pin               Arrival     No. of    
Name                                                                  Type            Name               Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut          GTP_DDC_E1      IFIFO_RADDR[1]     Out     0.464     0.464       -         
dqs_ififo_rpoint_0[1]                                                 Net             -                  -       0.408     -           8         
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut     GTP_ISERDES     RADDR[1]           In      -         0.872       -         
=================================================================================================================================================
Total path delay (propagation time + setup) of 0.992 is 0.584(58.9%) logic and 0.408(41.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      1000.000
    - Setup time:                            0.120
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         999.880

    - Propagation time:                      0.872
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 999.008

    Number of logic level(s):                0
    Starting point:                          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut / IFIFO_RADDR[2]
    Ending point:                            u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut / RADDR[2]
    The start point is clocked by            ipsl_phy_io_Z8|ioclk_01_inferred_clock [rising] on pin CLKA
    The end   point is clocked by            ipsl_phy_io_Z8|ioclk_01_inferred_clock [rising] on pin DESCLK

Instance / Net                                                                        Pin                Pin               Arrival     No. of    
Name                                                                  Type            Name               Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut          GTP_DDC_E1      IFIFO_RADDR[2]     Out     0.464     0.464       -         
dqs_ififo_rpoint_0[2]                                                 Net             -                  -       0.408     -           8         
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut     GTP_ISERDES     RADDR[2]           In      -         0.872       -         
=================================================================================================================================================
Total path delay (propagation time + setup) of 0.992 is 0.584(58.9%) logic and 0.408(41.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: pll_50_400|clkout1_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                                                                Starting                                                                         Arrival            
Instance                                                                                        Reference                             Type           Pin     Net                 Time        Slack  
                                                                                                Clock                                                                                               
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[1]      pll_50_400|clkout1_inferred_clock     GTP_DFF_CE     Q       cnt[1]              0.290       991.706
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[0]      pll_50_400|clkout1_inferred_clock     GTP_DFF_CE     Q       cnt[0]              0.290       991.754
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[4]      pll_50_400|clkout1_inferred_clock     GTP_DFF_CE     Q       cnt[4]              0.290       992.061
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[5]      pll_50_400|clkout1_inferred_clock     GTP_DFF_CE     Q       cnt[5]              0.290       992.084
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[3]      pll_50_400|clkout1_inferred_clock     GTP_DFF_CE     Q       cnt[3]              0.290       992.191
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[2]      pll_50_400|clkout1_inferred_clock     GTP_DFF_CE     Q       cnt[2]              0.290       992.239
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[6]      pll_50_400|clkout1_inferred_clock     GTP_DFF_CE     Q       cnt[6]              0.290       993.840
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.ddrc_init_start                   pll_50_400|clkout1_inferred_clock     GTP_DFF_PE     Q       ddrc_init_start     0.290       995.070
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.psel        pll_50_400|clkout1_inferred_clock     GTP_DFF_C      Q       init_psel           0.290       995.277
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.penable     pll_50_400|clkout1_inferred_clock     GTP_DFF_C      Q       init_penable        0.290       995.709
====================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                   Starting                                                                            Required            
Instance                                                           Reference                             Type           Pin          Net               Time         Slack  
                                                                   Clock                                                                                                   
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut     pll_50_400|clkout1_inferred_clock     GTP_DDRPHY     PWRITE       ddrc_pwrite       996.782      991.706
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                      pll_50_400|clkout1_inferred_clock     GTP_DDRC       PWRITE       ddrc_pwrite       996.782      991.706
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut     pll_50_400|clkout1_inferred_clock     GTP_DDRPHY     PADDR[2]     ddrc_paddr[2]     998.089      992.784
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                      pll_50_400|clkout1_inferred_clock     GTP_DDRC       PADDR[2]     ddrc_paddr[2]     998.089      992.784
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut     pll_50_400|clkout1_inferred_clock     GTP_DDRPHY     PADDR[7]     ddrc_paddr[7]     997.967      992.835
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                      pll_50_400|clkout1_inferred_clock     GTP_DDRC       PADDR[7]     ddrc_paddr[7]     997.967      992.835
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut     pll_50_400|clkout1_inferred_clock     GTP_DDRPHY     PADDR[9]     ddrc_paddr[9]     998.195      992.889
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                      pll_50_400|clkout1_inferred_clock     GTP_DDRC       PADDR[9]     ddrc_paddr[9]     998.195      992.889
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut     pll_50_400|clkout1_inferred_clock     GTP_DDRPHY     PADDR[5]     ddrc_paddr[5]     998.127      992.891
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                      pll_50_400|clkout1_inferred_clock     GTP_DDRC       PADDR[5]     ddrc_paddr[5]     998.127      992.891
===========================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      1000.000
    - Setup time:                            3.218
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         996.782

    - Propagation time:                      5.077
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 991.706

    Number of logic level(s):                3
    Starting point:                          u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[1] / Q
    Ending point:                            u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut / PWRITE
    The start point is clocked by            pll_50_400|clkout1_inferred_clock [rising] on pin CLK
    The end   point is clocked by            pll_50_400|clkout1_inferred_clock [rising] on pin PCLK

Instance / Net                                                                                                        Pin        Pin               Arrival     No. of    
Name                                                                                                   Type           Name       Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[1]             GTP_DFF_CE     Q          Out     0.290     0.290       -         
cnt[1]                                                                                                 Net            -          -       2.773     -           81        
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.un2_pwrite_0_0     GTP_LUT3       I1         In      -         3.063       -         
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.un2_pwrite_0_0     GTP_LUT3       Z          Out     0.306     3.369       -         
un2_pwrite_0_0                                                                                         Net            -          -       0.269     -           1         
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.un2_pwrite         GTP_LUT5       I4         In      -         3.638       -         
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.un2_pwrite         GTP_LUT5       Z          Out     0.176     3.813       -         
un2_pwrite                                                                                             Net            -          -       0.798     -           48        
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.ddrc_pwrite                              GTP_LUT2       I1         In      -         4.612       -         
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.ddrc_pwrite                              GTP_LUT2       Z          Out     0.176     4.788       -         
ddrc_pwrite                                                                                            Net            -          -       0.289     -           2         
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut                                         GTP_DDRPHY     PWRITE     In      -         5.077       -         
=========================================================================================================================================================================
Total path delay (propagation time + setup) of 8.294 is 4.166(50.2%) logic and 4.128(49.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      1000.000
    - Setup time:                            3.218
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         996.782

    - Propagation time:                      5.077
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 991.706

    Number of logic level(s):                3
    Starting point:                          u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[1] / Q
    Ending point:                            u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc / PWRITE
    The start point is clocked by            pll_50_400|clkout1_inferred_clock [rising] on pin CLK
    The end   point is clocked by            pll_50_400|clkout1_inferred_clock [rising] on pin PCLK

Instance / Net                                                                                                        Pin        Pin               Arrival     No. of    
Name                                                                                                   Type           Name       Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[1]             GTP_DFF_CE     Q          Out     0.290     0.290       -         
cnt[1]                                                                                                 Net            -          -       2.773     -           81        
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.un2_pwrite_0_0     GTP_LUT3       I1         In      -         3.063       -         
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.un2_pwrite_0_0     GTP_LUT3       Z          Out     0.306     3.369       -         
un2_pwrite_0_0                                                                                         Net            -          -       0.269     -           1         
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.un2_pwrite         GTP_LUT5       I4         In      -         3.638       -         
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.un2_pwrite         GTP_LUT5       Z          Out     0.176     3.813       -         
un2_pwrite                                                                                             Net            -          -       0.798     -           48        
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.ddrc_pwrite                              GTP_LUT2       I1         In      -         4.612       -         
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.ddrc_pwrite                              GTP_LUT2       Z          Out     0.176     4.788       -         
ddrc_pwrite                                                                                            Net            -          -       0.289     -           2         
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                                                          GTP_DDRC       PWRITE     In      -         5.077       -         
=========================================================================================================================================================================
Total path delay (propagation time + setup) of 8.294 is 4.166(50.2%) logic and 4.128(49.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      1000.000
    - Setup time:                            3.218
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         996.782

    - Propagation time:                      5.028
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 991.754

    Number of logic level(s):                3
    Starting point:                          u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[0] / Q
    Ending point:                            u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut / PWRITE
    The start point is clocked by            pll_50_400|clkout1_inferred_clock [rising] on pin CLK
    The end   point is clocked by            pll_50_400|clkout1_inferred_clock [rising] on pin PCLK

Instance / Net                                                                                                        Pin        Pin               Arrival     No. of    
Name                                                                                                   Type           Name       Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[0]             GTP_DFF_CE     Q          Out     0.290     0.290       -         
cnt[0]                                                                                                 Net            -          -       2.780     -           82        
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.un2_pwrite_0_0     GTP_LUT3       I0         In      -         3.070       -         
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.un2_pwrite_0_0     GTP_LUT3       Z          Out     0.251     3.321       -         
un2_pwrite_0_0                                                                                         Net            -          -       0.269     -           1         
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.un2_pwrite         GTP_LUT5       I4         In      -         3.589       -         
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.un2_pwrite         GTP_LUT5       Z          Out     0.176     3.765       -         
un2_pwrite                                                                                             Net            -          -       0.798     -           48        
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.ddrc_pwrite                              GTP_LUT2       I1         In      -         4.564       -         
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.ddrc_pwrite                              GTP_LUT2       Z          Out     0.176     4.740       -         
ddrc_pwrite                                                                                            Net            -          -       0.289     -           2         
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut                                         GTP_DDRPHY     PWRITE     In      -         5.028       -         
=========================================================================================================================================================================
Total path delay (propagation time + setup) of 8.246 is 4.111(49.9%) logic and 4.135(50.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: pll_50_400|clkout3_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                                                                    Starting                                                                             Arrival            
Instance                                                                                            Reference                             Type          Pin          Net                 Time        Slack  
                                                                                                    Clock                                                                                                   
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                                                       pll_50_400|clkout3_inferred_clock     GTP_DDRC      WREADY_1     wready_1            0.968       993.364
u_aq_axi_master.reg_wvalid                                                                          pll_50_400|clkout3_inferred_clock     GTP_DFF_C     Q            s00_axi_wvalid      0.290       993.828
u_aq_axi_master.rd_fifo_enable                                                                      pll_50_400|clkout3_inferred_clock     GTP_DFF_C     Q            rd_fifo_enable      0.290       993.897
u_aq_axi_master.rd_first_data                                                                       pll_50_400|clkout3_inferred_clock     GTP_DFF_C     Q            rd_first_data       0.290       994.137
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                                                       pll_50_400|clkout3_inferred_clock     GTP_DDRC      RVALID_1     rvalid_1            0.784       994.506
u_aq_axi_master.reg_arvalid                                                                         pll_50_400|clkout3_inferred_clock     GTP_DFF_C     Q            s00_axi_arvalid     0.290       994.853
u_aq_axi_master.reg_awvalid                                                                         pll_50_400|clkout3_inferred_clock     GTP_DFF_C     Q            s00_axi_awvalid     0.290       994.864
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.rbin[0]     pll_50_400|clkout3_inferred_clock     GTP_DFF_C     Q            rd_addr[0]          0.290       995.086
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.rbin[1]     pll_50_400|clkout3_inferred_clock     GTP_DFF_C     Q            rd_addr[1]          0.290       995.120
frame_read_write_m0.read_buf.U_ipml_fifo_afifo_64i_32o_128.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin[0]      pll_50_400|clkout3_inferred_clock     GTP_DFF_C     Q            wr_addr[0]          0.290       995.132
============================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                                        Starting                                                                                      Required            
Instance                                                                                                Reference                             Type           Pin     Net                              Time         Slack  
                                                                                                        Clock                                                                                                             
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty     pll_50_400|clkout3_inferred_clock     GTP_DFF_P      D       asyn_rempty_2_NE_i_0             1000.020     993.364
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rd_water_level[8]          pll_50_400|clkout3_inferred_clock     GTP_DFF_C      D       un1_rd_water_level_2_s_8_Z       1000.023     994.241
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rd_water_level[7]          pll_50_400|clkout3_inferred_clock     GTP_DFF_C      D       un1_rd_water_level_2_cry_7_Z     1000.023     994.275
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rd_water_level[6]          pll_50_400|clkout3_inferred_clock     GTP_DFF_C      D       un1_rd_water_level_2_cry_6_Z     1000.023     994.309
frame_read_write_m0.read_buf.U_ipml_fifo_afifo_64i_32o_128.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_wfull       pll_50_400|clkout3_inferred_clock     GTP_DFF_C      D       asyn_wfull_5                     1000.020     994.506
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.rptr[7]         pll_50_400|clkout3_inferred_clock     GTP_DFF_C      D       N_47_i                           1000.023     994.570
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.rptr[6]         pll_50_400|clkout3_inferred_clock     GTP_DFF_C      D       N_48_i                           1000.023     994.604
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.rptr[5]         pll_50_400|clkout3_inferred_clock     GTP_DFF_C      D       N_49_i                           1000.023     994.638
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.rptr[4]         pll_50_400|clkout3_inferred_clock     GTP_DFF_C      D       N_50_i                           1000.023     994.672
u_aq_axi_master.rd_fifo_cnt[0]                                                                          pll_50_400|clkout3_inferred_clock     GTP_DFF_CE     CE      rd_fifo_cnte                     999.645      994.675
==========================================================================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      1000.000
    - Setup time:                            -0.020
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1000.020

    - Propagation time:                      6.656
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 993.364

    Number of logic level(s):                14
    Starting point:                          u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc / WREADY_1
    Ending point:                            frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty / D
    The start point is clocked by            pll_50_400|clkout3_inferred_clock [rising] on pin ACLK_1
    The end   point is clocked by            pll_50_400|clkout3_inferred_clock [rising] on pin CLK

Instance / Net                                                                                                                       Pin          Pin               Arrival     No. of    
Name                                                                                                               Type              Name         Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                                                                      GTP_DDRC          WREADY_1     Out     0.968     0.968       -         
wready_1                                                                                                           Net               -            -       0.308     -           3         
u_aq_axi_master.rd_fifo_cntlde_0_o2                                                                                GTP_LUT4          I0           In      -         1.276       -         
u_aq_axi_master.rd_fifo_cntlde_0_o2                                                                                GTP_LUT4          Z            Out     0.251     1.527       -         
wr_burst_data_req                                                                                                  Net               -            -       2.511     -           37        
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_0_cy                       GTP_LUT5CARRY     I3           In      -         4.038       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_0_cy                       GTP_LUT5CARRY     COUT         Out     0.346     4.384       -         
rbnext_cry_0_cy                                                                                                    Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_0                          GTP_LUT5CARRY     CIN          In      -         4.384       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_0                          GTP_LUT5CARRY     COUT         Out     0.034     4.418       -         
rbnext_cry_0                                                                                                       Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_1                          GTP_LUT5CARRY     CIN          In      -         4.418       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_1                          GTP_LUT5CARRY     COUT         Out     0.034     4.452       -         
rbnext_cry_1                                                                                                       Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_2                          GTP_LUT5CARRY     CIN          In      -         4.452       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_2                          GTP_LUT5CARRY     COUT         Out     0.034     4.486       -         
rbnext_cry_2                                                                                                       Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_3                          GTP_LUT5CARRY     CIN          In      -         4.486       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_3                          GTP_LUT5CARRY     COUT         Out     0.034     4.520       -         
rbnext_cry_3                                                                                                       Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_4                          GTP_LUT5CARRY     CIN          In      -         4.520       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_4                          GTP_LUT5CARRY     COUT         Out     0.034     4.554       -         
rbnext_cry_4                                                                                                       Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_5                          GTP_LUT5CARRY     CIN          In      -         4.554       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_5                          GTP_LUT5CARRY     COUT         Out     0.034     4.588       -         
rbnext_cry_5                                                                                                       Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_6                          GTP_LUT5CARRY     CIN          In      -         4.588       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_6                          GTP_LUT5CARRY     COUT         Out     0.034     4.622       -         
rbnext_cry_6                                                                                                       Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_7                          GTP_LUT5CARRY     CIN          In      -         4.622       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_7                          GTP_LUT5CARRY     COUT         Out     0.034     4.656       -         
rbnext_cry_7                                                                                                       Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_s_8                            GTP_LUT5CARRY     CIN          In      -         4.656       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_s_8                            GTP_LUT5CARRY     Z            Out     0.232     4.888       -         
rbnext[8]                                                                                                          Net               -            -       0.328     -           4         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty_2_8_i_1_x2     GTP_LUT2          I1           In      -         5.216       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty_2_8_i_1_x2     GTP_LUT2          Z            Out     0.176     5.392       -         
dsp_join_kb_42[8]                                                                                                  Net               -            -       0.269     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty_2_NE_0_1       GTP_LUT5          I1           In      -         5.661       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty_2_NE_0_1       GTP_LUT5          Z            Out     0.306     5.967       -         
asyn_rempty_2_NE_0_1                                                                                               Net               -            -       0.269     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty_2_NE_i         GTP_LUT5          I3           In      -         6.236       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty_2_NE_i         GTP_LUT5          Z            Out     0.420     6.656       -         
asyn_rempty_2_NE_i_0                                                                                               Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty                GTP_DFF_P         D            In      -         6.656       -         
==========================================================================================================================================================================================
Total path delay (propagation time + setup) of 6.636 is 2.951(44.5%) logic and 3.685(55.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      1000.000
    - Setup time:                            -0.023
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1000.023

    - Propagation time:                      6.316
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 993.707

    Number of logic level(s):                10
    Starting point:                          u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc / WREADY_1
    Ending point:                            frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty / D
    The start point is clocked by            pll_50_400|clkout3_inferred_clock [rising] on pin ACLK_1
    The end   point is clocked by            pll_50_400|clkout3_inferred_clock [rising] on pin CLK

Instance / Net                                                                                                                          Pin          Pin               Arrival     No. of    
Name                                                                                                                  Type              Name         Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                                                                         GTP_DDRC          WREADY_1     Out     0.968     0.968       -         
wready_1                                                                                                              Net               -            -       0.308     -           3         
u_aq_axi_master.rd_fifo_cntlde_0_o2                                                                                   GTP_LUT4          I0           In      -         1.276       -         
u_aq_axi_master.rd_fifo_cntlde_0_o2                                                                                   GTP_LUT4          Z            Out     0.251     1.527       -         
wr_burst_data_req                                                                                                     Net               -            -       2.511     -           37        
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_0_cy                          GTP_LUT5CARRY     I3           In      -         4.038       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_0_cy                          GTP_LUT5CARRY     COUT         Out     0.346     4.384       -         
rbnext_cry_0_cy                                                                                                       Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_0                             GTP_LUT5CARRY     CIN          In      -         4.384       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_0                             GTP_LUT5CARRY     COUT         Out     0.034     4.418       -         
rbnext_cry_0                                                                                                          Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_1                             GTP_LUT5CARRY     CIN          In      -         4.418       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_1                             GTP_LUT5CARRY     COUT         Out     0.034     4.452       -         
rbnext_cry_1                                                                                                          Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_2                             GTP_LUT5CARRY     CIN          In      -         4.452       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_2                             GTP_LUT5CARRY     COUT         Out     0.034     4.486       -         
rbnext_cry_2                                                                                                          Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_3                             GTP_LUT5CARRY     CIN          In      -         4.486       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_3                             GTP_LUT5CARRY     COUT         Out     0.034     4.520       -         
rbnext_cry_3                                                                                                          Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_4                             GTP_LUT5CARRY     CIN          In      -         4.520       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_4                             GTP_LUT5CARRY     Z            Out     0.232     4.752       -         
N_148                                                                                                                 Net               -            -       0.348     -           5         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty_2_4_0_a3_0_x2     GTP_LUT3          I0           In      -         5.100       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty_2_4_0_a3_0_x2     GTP_LUT3          Z            Out     0.251     5.351       -         
N_62_i                                                                                                                Net               -            -       0.269     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty_2_NE_1            GTP_LUT5          I0           In      -         5.620       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty_2_NE_1            GTP_LUT5          Z            Out     0.251     5.871       -         
asyn_rempty_2_NE_1                                                                                                    Net               -            -       0.269     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty_2_NE_i            GTP_LUT5          I4           In      -         6.139       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty_2_NE_i            GTP_LUT5          Z            Out     0.176     6.316       -         
asyn_rempty_2_NE_i_0                                                                                                  Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty                   GTP_DFF_P         D            In      -         6.316       -         
=============================================================================================================================================================================================
Total path delay (propagation time + setup) of 6.292 is 2.588(41.1%) logic and 3.705(58.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      1000.000
    - Setup time:                            -0.020
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1000.020

    - Propagation time:                      6.277
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 993.743

    Number of logic level(s):                11
    Starting point:                          u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc / WREADY_1
    Ending point:                            frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty / D
    The start point is clocked by            pll_50_400|clkout3_inferred_clock [rising] on pin ACLK_1
    The end   point is clocked by            pll_50_400|clkout3_inferred_clock [rising] on pin CLK

Instance / Net                                                                                                                     Pin          Pin               Arrival     No. of    
Name                                                                                                             Type              Name         Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                                                                    GTP_DDRC          WREADY_1     Out     0.968     0.968       -         
wready_1                                                                                                         Net               -            -       0.308     -           3         
u_aq_axi_master.rd_fifo_cntlde_0_o2                                                                              GTP_LUT4          I0           In      -         1.276       -         
u_aq_axi_master.rd_fifo_cntlde_0_o2                                                                              GTP_LUT4          Z            Out     0.251     1.527       -         
wr_burst_data_req                                                                                                Net               -            -       2.511     -           37        
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_0_cy                     GTP_LUT5CARRY     I3           In      -         4.038       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_0_cy                     GTP_LUT5CARRY     COUT         Out     0.346     4.384       -         
rbnext_cry_0_cy                                                                                                  Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_0                        GTP_LUT5CARRY     CIN          In      -         4.384       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_0                        GTP_LUT5CARRY     COUT         Out     0.034     4.418       -         
rbnext_cry_0                                                                                                     Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_1                        GTP_LUT5CARRY     CIN          In      -         4.418       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_1                        GTP_LUT5CARRY     COUT         Out     0.034     4.452       -         
rbnext_cry_1                                                                                                     Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_2                        GTP_LUT5CARRY     CIN          In      -         4.452       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_2                        GTP_LUT5CARRY     COUT         Out     0.034     4.486       -         
rbnext_cry_2                                                                                                     Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_3                        GTP_LUT5CARRY     CIN          In      -         4.486       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_3                        GTP_LUT5CARRY     COUT         Out     0.034     4.520       -         
rbnext_cry_3                                                                                                     Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_4                        GTP_LUT5CARRY     CIN          In      -         4.520       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_4                        GTP_LUT5CARRY     COUT         Out     0.034     4.554       -         
rbnext_cry_4                                                                                                     Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_5                        GTP_LUT5CARRY     CIN          In      -         4.554       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_5                        GTP_LUT5CARRY     COUT         Out     0.034     4.588       -         
rbnext_cry_5                                                                                                     Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_6                        GTP_LUT5CARRY     CIN          In      -         4.588       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_6                        GTP_LUT5CARRY     Z            Out     0.232     4.820       -         
rbnext[6]                                                                                                        Net               -            -       0.348     -           5         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty_2_NE_0_1     GTP_LUT5          I3           In      -         5.168       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty_2_NE_0_1     GTP_LUT5          Z            Out     0.420     5.588       -         
asyn_rempty_2_NE_0_1                                                                                             Net               -            -       0.269     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty_2_NE_i       GTP_LUT5          I3           In      -         5.857       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty_2_NE_i       GTP_LUT5          Z            Out     0.420     6.277       -         
asyn_rempty_2_NE_i_0                                                                                             Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty              GTP_DFF_P         D            In      -         6.277       -         
========================================================================================================================================================================================
Total path delay (propagation time + setup) of 6.257 is 2.821(45.1%) logic and 3.436(54.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: sys_clk
====================================



Starting Points with Worst Slack
********************************

                                                                                                    Starting                                                   Arrival           
Instance                                                                                            Reference     Type           Pin     Net                   Time        Slack 
                                                                                                    Clock                                                                        
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[1]                                               sys_clk       GTP_DFF_CE     Q       state[1]              0.290       14.934
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[0]                                               sys_clk       GTP_DFF_CE     Q       state[0]              0.290       15.032
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[4]                                               sys_clk       GTP_DFF_CE     Q       state[4]              0.290       15.127
sd_card_bmp_m0.sd_card_top_m0.spi_master_m0.MISO_shift[1]                                           sys_clk       GTP_DFF_CE     Q       spi_data_out[1]       0.290       15.147
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin[0]     sys_clk       GTP_DFF_C      Q       dsp_join_kb_40[0]     0.290       15.157
sd_card_bmp_m0.sd_card_top_m0.spi_master_m0.MISO_shift[2]                                           sys_clk       GTP_DFF_CE     Q       spi_data_out[2]       0.290       15.162
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.byte_cnt[14]                                           sys_clk       GTP_DFF_CE     Q       byte_cnt[14]          0.290       15.221
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin[1]     sys_clk       GTP_DFF_C      Q       dsp_join_kb_40[1]     0.290       15.226
sd_card_bmp_m0.sd_card_top_m0.spi_master_m0.MISO_shift[0]                                           sys_clk       GTP_DFF_CE     Q       spi_data_out[0]       0.290       15.257
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin[2]     sys_clk       GTP_DFF_C      Q       dsp_join_kb_40[2]     0.290       15.260
=================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                                       Starting                                                         Required           
Instance                                                                                               Reference     Type           Pin     Net                         Time         Slack 
                                                                                                       Clock                                                                               
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[0]                                                  sys_clk       GTP_DFF_CE     CE      un1_CS_reg_1_sqmuxa_i_0     19.636       14.934
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[1]                                                  sys_clk       GTP_DFF_CE     CE      un1_CS_reg_1_sqmuxa_i_0     19.636       14.934
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[2]                                                  sys_clk       GTP_DFF_CE     CE      un1_CS_reg_1_sqmuxa_i_0     19.636       14.934
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[3]                                                  sys_clk       GTP_DFF_CE     CE      un1_CS_reg_1_sqmuxa_i_0     19.636       14.934
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[4]                                                  sys_clk       GTP_DFF_CE     CE      un1_CS_reg_1_sqmuxa_i_0     19.636       14.934
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_wfull     sys_clk       GTP_DFF_C      D       asyn_wfull_2                20.020       15.157
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.byte_cnt[0]                                               sys_clk       GTP_DFF_CE     D       byte_cnt_lm[0]              20.023       15.340
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.byte_cnt[1]                                               sys_clk       GTP_DFF_CE     D       byte_cnt_lm[1]              20.023       15.340
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.byte_cnt[2]                                               sys_clk       GTP_DFF_CE     D       byte_cnt_lm[2]              20.023       15.340
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.byte_cnt[3]                                               sys_clk       GTP_DFF_CE     D       byte_cnt_lm[3]              20.023       15.340
===========================================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      20.000
    - Setup time:                            0.364
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         19.636

    - Propagation time:                      4.702
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     14.934

    Number of logic level(s):                6
    Starting point:                          sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[1] / Q
    Ending point:                            sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[0] / CE
    The start point is clocked by            sys_clk [rising] on pin CLK
    The end   point is clocked by            sys_clk [rising] on pin CLK

Instance / Net                                                                          Pin      Pin               Arrival     No. of    
Name                                                                     Type           Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[1]                    GTP_DFF_CE     Q        Out     0.290     0.290       -         
state[1]                                                                 Net            -        -       0.750     -           26        
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state134_1_0                GTP_LUT3       I1       In      -         1.040       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state134_1_0                GTP_LUT3       Z        Out     0.306     1.346       -         
state134_1_0                                                             Net            -        -       0.328     -           4         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.CS_reg_1_sqmuxa             GTP_LUT4       I1       In      -         1.674       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.CS_reg_1_sqmuxa             GTP_LUT4       Z        Out     0.306     1.980       -         
CS_reg_1_sqmuxa                                                          Net            -        -       0.289     -           2         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_0_0     GTP_LUT4       I0       In      -         2.269       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_0_0     GTP_LUT4       Z        Out     0.251     2.520       -         
un1_CS_reg_1_sqmuxa_0_0                                                  Net            -        -       0.269     -           1         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_3_0     GTP_LUT5       I2       In      -         2.788       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_3_0     GTP_LUT5       Z        Out     0.416     3.204       -         
un1_CS_reg_1_sqmuxa_3_0                                                  Net            -        -       0.269     -           1         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_1_1     GTP_LUT5       I1       In      -         3.473       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_1_1     GTP_LUT5       Z        Out     0.306     3.779       -         
un1_CS_reg_1_sqmuxa_1_1                                                  Net            -        -       0.269     -           1         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_i       GTP_LUT5       I1       In      -         4.048       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_i       GTP_LUT5       Z        Out     0.306     4.354       -         
un1_CS_reg_1_sqmuxa_i_0                                                  Net            -        -       0.348     -           5         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[0]                    GTP_DFF_CE     CE       In      -         4.702       -         
=========================================================================================================================================
Total path delay (propagation time + setup) of 5.066 is 2.545(50.2%) logic and 2.521(49.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      20.000
    - Setup time:                            0.364
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         19.636

    - Propagation time:                      4.702
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     14.934

    Number of logic level(s):                6
    Starting point:                          sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[1] / Q
    Ending point:                            sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[1] / CE
    The start point is clocked by            sys_clk [rising] on pin CLK
    The end   point is clocked by            sys_clk [rising] on pin CLK

Instance / Net                                                                          Pin      Pin               Arrival     No. of    
Name                                                                     Type           Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[1]                    GTP_DFF_CE     Q        Out     0.290     0.290       -         
state[1]                                                                 Net            -        -       0.750     -           26        
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state134_1_0                GTP_LUT3       I1       In      -         1.040       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state134_1_0                GTP_LUT3       Z        Out     0.306     1.346       -         
state134_1_0                                                             Net            -        -       0.328     -           4         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.CS_reg_1_sqmuxa             GTP_LUT4       I1       In      -         1.674       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.CS_reg_1_sqmuxa             GTP_LUT4       Z        Out     0.306     1.980       -         
CS_reg_1_sqmuxa                                                          Net            -        -       0.289     -           2         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_0_0     GTP_LUT4       I0       In      -         2.269       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_0_0     GTP_LUT4       Z        Out     0.251     2.520       -         
un1_CS_reg_1_sqmuxa_0_0                                                  Net            -        -       0.269     -           1         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_3_0     GTP_LUT5       I2       In      -         2.788       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_3_0     GTP_LUT5       Z        Out     0.416     3.204       -         
un1_CS_reg_1_sqmuxa_3_0                                                  Net            -        -       0.269     -           1         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_1_1     GTP_LUT5       I1       In      -         3.473       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_1_1     GTP_LUT5       Z        Out     0.306     3.779       -         
un1_CS_reg_1_sqmuxa_1_1                                                  Net            -        -       0.269     -           1         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_i       GTP_LUT5       I1       In      -         4.048       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_i       GTP_LUT5       Z        Out     0.306     4.354       -         
un1_CS_reg_1_sqmuxa_i_0                                                  Net            -        -       0.348     -           5         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[1]                    GTP_DFF_CE     CE       In      -         4.702       -         
=========================================================================================================================================
Total path delay (propagation time + setup) of 5.066 is 2.545(50.2%) logic and 2.521(49.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      20.000
    - Setup time:                            0.364
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         19.636

    - Propagation time:                      4.702
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     14.934

    Number of logic level(s):                6
    Starting point:                          sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[1] / Q
    Ending point:                            sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[2] / CE
    The start point is clocked by            sys_clk [rising] on pin CLK
    The end   point is clocked by            sys_clk [rising] on pin CLK

Instance / Net                                                                          Pin      Pin               Arrival     No. of    
Name                                                                     Type           Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[1]                    GTP_DFF_CE     Q        Out     0.290     0.290       -         
state[1]                                                                 Net            -        -       0.750     -           26        
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state134_1_0                GTP_LUT3       I1       In      -         1.040       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state134_1_0                GTP_LUT3       Z        Out     0.306     1.346       -         
state134_1_0                                                             Net            -        -       0.328     -           4         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.CS_reg_1_sqmuxa             GTP_LUT4       I1       In      -         1.674       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.CS_reg_1_sqmuxa             GTP_LUT4       Z        Out     0.306     1.980       -         
CS_reg_1_sqmuxa                                                          Net            -        -       0.289     -           2         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_0_0     GTP_LUT4       I0       In      -         2.269       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_0_0     GTP_LUT4       Z        Out     0.251     2.520       -         
un1_CS_reg_1_sqmuxa_0_0                                                  Net            -        -       0.269     -           1         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_3_0     GTP_LUT5       I2       In      -         2.788       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_3_0     GTP_LUT5       Z        Out     0.416     3.204       -         
un1_CS_reg_1_sqmuxa_3_0                                                  Net            -        -       0.269     -           1         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_1_1     GTP_LUT5       I1       In      -         3.473       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_1_1     GTP_LUT5       Z        Out     0.306     3.779       -         
un1_CS_reg_1_sqmuxa_1_1                                                  Net            -        -       0.269     -           1         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_i       GTP_LUT5       I1       In      -         4.048       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_i       GTP_LUT5       Z        Out     0.306     4.354       -         
un1_CS_reg_1_sqmuxa_i_0                                                  Net            -        -       0.348     -           5         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[2]                    GTP_DFF_CE     CE       In      -         4.702       -         
=========================================================================================================================================
Total path delay (propagation time + setup) of 5.066 is 2.545(50.2%) logic and 2.521(49.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: video_pll|clkout0_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                 Starting                                                                       Arrival            
Instance                         Reference                            Type        Pin     Net                   Time        Slack  
                                 Clock                                                                                             
-----------------------------------------------------------------------------------------------------------------------------------
dvi_encoder_m0.encb.n0q_m[0]     video_pll|clkout0_inferred_clock     GTP_DFF     Q       dsp_join_kb_23[1]     0.290       994.419
dvi_encoder_m0.encb.n1q_m[1]     video_pll|clkout0_inferred_clock     GTP_DFF     Q       n1q_m[1]              0.290       994.514
dvi_encoder_m0.encg.n0q_m[0]     video_pll|clkout0_inferred_clock     GTP_DFF     Q       dsp_join_kb_37[1]     0.290       994.589
dvi_encoder_m0.encr.n0q_m[0]     video_pll|clkout0_inferred_clock     GTP_DFF     Q       dsp_join_kb_30[1]     0.290       994.589
dvi_encoder_m0.encg.n1q_m[1]     video_pll|clkout0_inferred_clock     GTP_DFF     Q       n1q_m[1]              0.290       994.684
dvi_encoder_m0.encr.n1q_m[1]     video_pll|clkout0_inferred_clock     GTP_DFF     Q       n1q_m[1]              0.290       994.684
dvi_encoder_m0.encb.n1q_m[3]     video_pll|clkout0_inferred_clock     GTP_DFF     Q       n1q_m[3]              0.290       994.715
dvi_encoder_m0.encb.n0q_m[2]     video_pll|clkout0_inferred_clock     GTP_DFF     Q       dsp_join_kb_23[3]     0.290       994.718
dvi_encoder_m0.encb.n1q_m[2]     video_pll|clkout0_inferred_clock     GTP_DFF     Q       n1q_m[2]              0.290       994.719
dvi_encoder_m0.encr.n0q_m[2]     video_pll|clkout0_inferred_clock     GTP_DFF     Q       dsp_join_kb_30[3]     0.290       994.812
===================================================================================================================================


Ending Points with Worst Slack
******************************

                               Starting                                                                      Required            
Instance                       Reference                            Type          Pin     Net                Time         Slack  
                               Clock                                                                                             
---------------------------------------------------------------------------------------------------------------------------------
dvi_encoder_m0.encb.cnt[4]     video_pll|clkout0_inferred_clock     GTP_DFF_C     D       un10_s_4_Z_1       1000.023     994.419
dvi_encoder_m0.encb.cnt[3]     video_pll|clkout0_inferred_clock     GTP_DFF_C     D       un10_cry_3_Z_1     1000.023     994.453
dvi_encoder_m0.encb.cnt[2]     video_pll|clkout0_inferred_clock     GTP_DFF_C     D       un10_cry_2_Z_1     1000.023     994.487
dvi_encoder_m0.encr.cnt[4]     video_pll|clkout0_inferred_clock     GTP_DFF_C     D       un10_s_4_Z_0       1000.023     994.589
dvi_encoder_m0.encg.cnt[4]     video_pll|clkout0_inferred_clock     GTP_DFF_C     D       un10_s_4_Z         1000.023     994.589
dvi_encoder_m0.encg.cnt[3]     video_pll|clkout0_inferred_clock     GTP_DFF_C     D       un10_cry_3_Z       1000.023     994.623
dvi_encoder_m0.encr.cnt[3]     video_pll|clkout0_inferred_clock     GTP_DFF_C     D       un10_cry_3_Z_0     1000.023     994.623
dvi_encoder_m0.encb.cnt[1]     video_pll|clkout0_inferred_clock     GTP_DFF_C     D       un10_cry_1_Z_1     1000.020     994.644
dvi_encoder_m0.encr.cnt[2]     video_pll|clkout0_inferred_clock     GTP_DFF_C     D       un10_cry_2_Z_0     1000.020     994.776
dvi_encoder_m0.encg.cnt[2]     video_pll|clkout0_inferred_clock     GTP_DFF_C     D       un10_cry_2_Z       1000.020     994.776
=================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      1000.000
    - Setup time:                            -0.023
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1000.023

    - Propagation time:                      5.604
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 994.419

    Number of logic level(s):                12
    Starting point:                          dvi_encoder_m0.encb.n0q_m[0] / Q
    Ending point:                            dvi_encoder_m0.encb.cnt[4] / D
    The start point is clocked by            video_pll|clkout0_inferred_clock [rising] on pin CLK
    The end   point is clocked by            video_pll|clkout0_inferred_clock [rising] on pin CLK

Instance / Net                                                  Pin      Pin               Arrival     No. of    
Name                                          Type              Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------
dvi_encoder_m0.encb.n0q_m[0]                  GTP_DFF           Q        Out     0.290     0.290       -         
dsp_join_kb_23[1]                             Net               -        -       0.368     -           6         
dvi_encoder_m0.encb.un4_decision3_ac0_3_0     GTP_LUT2          I0       In      -         0.658       -         
dvi_encoder_m0.encb.un4_decision3_ac0_3_0     GTP_LUT2          Z        Out     0.251     0.909       -         
un4_decision3_ac0_3_0                         Net               -        -       0.269     -           1         
dvi_encoder_m0.encb.un4_decision3_c4          GTP_LUT5          I4       In      -         1.178       -         
dvi_encoder_m0.encb.un4_decision3_c4          GTP_LUT5          Z        Out     0.176     1.354       -         
un4_decision3_c4_1                            Net               -        -       0.269     -           1         
dvi_encoder_m0.encb.un1_decision3[0]          GTP_LUT5          I3       In      -         1.623       -         
dvi_encoder_m0.encb.un1_decision3[0]          GTP_LUT5          Z        Out     0.420     2.042       -         
N_450                                         Net               -        -       0.328     -           4         
dvi_encoder_m0.encb.cnt_3_sqmuxa              GTP_LUT3          I0       In      -         2.371       -         
dvi_encoder_m0.encb.cnt_3_sqmuxa              GTP_LUT3          Z        Out     0.251     2.622       -         
cnt_3_sqmuxa                                  Net               -        -       0.448     -           10        
dvi_encoder_m0.encb.un10_4_axb_0_1            GTP_LUT3          I1       In      -         3.070       -         
dvi_encoder_m0.encb.un10_4_axb_0_1            GTP_LUT3          Z        Out     0.306     3.376       -         
un10_4_axb_0_1                                Net               -        -       0.269     -           1         
dvi_encoder_m0.encb.un10_4_axb_0              GTP_LUT4          I3       In      -         3.644       -         
dvi_encoder_m0.encb.un10_4_axb_0              GTP_LUT4          Z        Out     0.176     3.820       -         
un10_4_axb_0                                  Net               -        -       0.269     -           1         
dvi_encoder_m0.encb.un10_4_cry_0_0            GTP_LUT5CARRY     I3       In      -         4.089       -         
dvi_encoder_m0.encb.un10_4_cry_0_0            GTP_LUT5CARRY     COUT     Out     0.346     4.435       -         
un10_4_cry_0_0                                Net               -        -       0.000     -           1         
dvi_encoder_m0.encb.un10_4_cry_1              GTP_LUT5CARRY     CIN      In      -         4.435       -         
dvi_encoder_m0.encb.un10_4_cry_1              GTP_LUT5CARRY     Z        Out     0.232     4.667       -         
un10_4[1]                                     Net               -        -       0.289     -           2         
dvi_encoder_m0.encb.un10_cry_1                GTP_LUT5CARRY     I2       In      -         4.955       -         
dvi_encoder_m0.encb.un10_cry_1                GTP_LUT5CARRY     COUT     Out     0.348     5.303       -         
un10_cry_1                                    Net               -        -       0.000     -           1         
dvi_encoder_m0.encb.un10_cry_2                GTP_LUT5CARRY     CIN      In      -         5.303       -         
dvi_encoder_m0.encb.un10_cry_2                GTP_LUT5CARRY     COUT     Out     0.034     5.338       -         
un10_cry_2                                    Net               -        -       0.000     -           1         
dvi_encoder_m0.encb.un10_cry_3                GTP_LUT5CARRY     CIN      In      -         5.338       -         
dvi_encoder_m0.encb.un10_cry_3                GTP_LUT5CARRY     COUT     Out     0.034     5.372       -         
un10_cry_3                                    Net               -        -       0.000     -           1         
dvi_encoder_m0.encb.un10_s_4                  GTP_LUT5CARRY     CIN      In      -         5.372       -         
dvi_encoder_m0.encb.un10_s_4                  GTP_LUT5CARRY     Z        Out     0.232     5.604       -         
un10_s_4_Z_1                                  Net               -        -       0.000     -           1         
dvi_encoder_m0.encb.cnt[4]                    GTP_DFF_C         D        In      -         5.604       -         
=================================================================================================================
Total path delay (propagation time + setup) of 5.580 is 3.073(55.1%) logic and 2.508(44.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      1000.000
    - Setup time:                            -0.023
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1000.023

    - Propagation time:                      5.601
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 994.422

    Number of logic level(s):                12
    Starting point:                          dvi_encoder_m0.encb.n0q_m[0] / Q
    Ending point:                            dvi_encoder_m0.encb.cnt[4] / D
    The start point is clocked by            video_pll|clkout0_inferred_clock [rising] on pin CLK
    The end   point is clocked by            video_pll|clkout0_inferred_clock [rising] on pin CLK

Instance / Net                                                  Pin      Pin               Arrival     No. of    
Name                                          Type              Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------
dvi_encoder_m0.encb.n0q_m[0]                  GTP_DFF           Q        Out     0.290     0.290       -         
dsp_join_kb_23[1]                             Net               -        -       0.368     -           6         
dvi_encoder_m0.encb.un4_decision3_ac0_3_0     GTP_LUT2          I0       In      -         0.658       -         
dvi_encoder_m0.encb.un4_decision3_ac0_3_0     GTP_LUT2          Z        Out     0.251     0.909       -         
un4_decision3_ac0_3_0                         Net               -        -       0.269     -           1         
dvi_encoder_m0.encb.un4_decision3_c4          GTP_LUT5          I4       In      -         1.178       -         
dvi_encoder_m0.encb.un4_decision3_c4          GTP_LUT5          Z        Out     0.176     1.354       -         
un4_decision3_c4_1                            Net               -        -       0.269     -           1         
dvi_encoder_m0.encb.un1_decision3[0]          GTP_LUT5          I3       In      -         1.623       -         
dvi_encoder_m0.encb.un1_decision3[0]          GTP_LUT5          Z        Out     0.420     2.042       -         
N_450                                         Net               -        -       0.328     -           4         
dvi_encoder_m0.encb.cnt_3_sqmuxa              GTP_LUT3          I0       In      -         2.371       -         
dvi_encoder_m0.encb.cnt_3_sqmuxa              GTP_LUT3          Z        Out     0.251     2.622       -         
cnt_3_sqmuxa                                  Net               -        -       0.448     -           10        
dvi_encoder_m0.encb.un10_4_axb_0_1            GTP_LUT3          I1       In      -         3.070       -         
dvi_encoder_m0.encb.un10_4_axb_0_1            GTP_LUT3          Z        Out     0.306     3.376       -         
un10_4_axb_0_1                                Net               -        -       0.269     -           1         
dvi_encoder_m0.encb.un10_4_axb_0              GTP_LUT4          I3       In      -         3.644       -         
dvi_encoder_m0.encb.un10_4_axb_0              GTP_LUT4          Z        Out     0.176     3.820       -         
un10_4_axb_0                                  Net               -        -       0.269     -           1         
dvi_encoder_m0.encb.un10_4_cry_0_0            GTP_LUT5CARRY     I3       In      -         4.089       -         
dvi_encoder_m0.encb.un10_4_cry_0_0            GTP_LUT5CARRY     COUT     Out     0.346     4.435       -         
un10_4_cry_0_0                                Net               -        -       0.000     -           1         
dvi_encoder_m0.encb.un10_4_cry_1              GTP_LUT5CARRY     CIN      In      -         4.435       -         
dvi_encoder_m0.encb.un10_4_cry_1              GTP_LUT5CARRY     Z        Out     0.232     4.667       -         
un10_4[1]                                     Net               -        -       0.289     -           2         
dvi_encoder_m0.encb.un10_cry_1                GTP_LUT5CARRY     I3       In      -         4.955       -         
dvi_encoder_m0.encb.un10_cry_1                GTP_LUT5CARRY     COUT     Out     0.346     5.301       -         
un10_cry_1                                    Net               -        -       0.000     -           1         
dvi_encoder_m0.encb.un10_cry_2                GTP_LUT5CARRY     CIN      In      -         5.301       -         
dvi_encoder_m0.encb.un10_cry_2                GTP_LUT5CARRY     COUT     Out     0.034     5.335       -         
un10_cry_2                                    Net               -        -       0.000     -           1         
dvi_encoder_m0.encb.un10_cry_3                GTP_LUT5CARRY     CIN      In      -         5.335       -         
dvi_encoder_m0.encb.un10_cry_3                GTP_LUT5CARRY     COUT     Out     0.034     5.369       -         
un10_cry_3                                    Net               -        -       0.000     -           1         
dvi_encoder_m0.encb.un10_s_4                  GTP_LUT5CARRY     CIN      In      -         5.369       -         
dvi_encoder_m0.encb.un10_s_4                  GTP_LUT5CARRY     Z        Out     0.232     5.601       -         
un10_s_4_Z_1                                  Net               -        -       0.000     -           1         
dvi_encoder_m0.encb.cnt[4]                    GTP_DFF_C         D        In      -         5.601       -         
=================================================================================================================
Total path delay (propagation time + setup) of 5.578 is 3.071(55.0%) logic and 2.508(45.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      1000.000
    - Setup time:                            -0.023
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1000.023

    - Propagation time:                      5.569
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 994.454

    Number of logic level(s):                11
    Starting point:                          dvi_encoder_m0.encb.n0q_m[0] / Q
    Ending point:                            dvi_encoder_m0.encb.cnt[3] / D
    The start point is clocked by            video_pll|clkout0_inferred_clock [rising] on pin CLK
    The end   point is clocked by            video_pll|clkout0_inferred_clock [rising] on pin CLK

Instance / Net                                                  Pin      Pin               Arrival     No. of    
Name                                          Type              Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------
dvi_encoder_m0.encb.n0q_m[0]                  GTP_DFF           Q        Out     0.290     0.290       -         
dsp_join_kb_23[1]                             Net               -        -       0.368     -           6         
dvi_encoder_m0.encb.un4_decision3_ac0_3_0     GTP_LUT2          I0       In      -         0.658       -         
dvi_encoder_m0.encb.un4_decision3_ac0_3_0     GTP_LUT2          Z        Out     0.251     0.909       -         
un4_decision3_ac0_3_0                         Net               -        -       0.269     -           1         
dvi_encoder_m0.encb.un4_decision3_c4          GTP_LUT5          I4       In      -         1.178       -         
dvi_encoder_m0.encb.un4_decision3_c4          GTP_LUT5          Z        Out     0.176     1.354       -         
un4_decision3_c4_1                            Net               -        -       0.269     -           1         
dvi_encoder_m0.encb.un1_decision3[0]          GTP_LUT5          I3       In      -         1.623       -         
dvi_encoder_m0.encb.un1_decision3[0]          GTP_LUT5          Z        Out     0.420     2.042       -         
N_450                                         Net               -        -       0.328     -           4         
dvi_encoder_m0.encb.cnt_3_sqmuxa              GTP_LUT3          I0       In      -         2.371       -         
dvi_encoder_m0.encb.cnt_3_sqmuxa              GTP_LUT3          Z        Out     0.251     2.622       -         
cnt_3_sqmuxa                                  Net               -        -       0.448     -           10        
dvi_encoder_m0.encb.un10_4_axb_0_1            GTP_LUT3          I1       In      -         3.070       -         
dvi_encoder_m0.encb.un10_4_axb_0_1            GTP_LUT3          Z        Out     0.306     3.376       -         
un10_4_axb_0_1                                Net               -        -       0.269     -           1         
dvi_encoder_m0.encb.un10_4_axb_0              GTP_LUT4          I3       In      -         3.644       -         
dvi_encoder_m0.encb.un10_4_axb_0              GTP_LUT4          Z        Out     0.176     3.820       -         
un10_4_axb_0                                  Net               -        -       0.269     -           1         
dvi_encoder_m0.encb.un10_4_cry_0_0            GTP_LUT5CARRY     I3       In      -         4.089       -         
dvi_encoder_m0.encb.un10_4_cry_0_0            GTP_LUT5CARRY     COUT     Out     0.346     4.435       -         
un10_4_cry_0_0                                Net               -        -       0.000     -           1         
dvi_encoder_m0.encb.un10_4_cry_1              GTP_LUT5CARRY     CIN      In      -         4.435       -         
dvi_encoder_m0.encb.un10_4_cry_1              GTP_LUT5CARRY     Z        Out     0.232     4.667       -         
un10_4[1]                                     Net               -        -       0.289     -           2         
dvi_encoder_m0.encb.un10_cry_1                GTP_LUT5CARRY     I2       In      -         4.955       -         
dvi_encoder_m0.encb.un10_cry_1                GTP_LUT5CARRY     COUT     Out     0.348     5.303       -         
un10_cry_1                                    Net               -        -       0.000     -           1         
dvi_encoder_m0.encb.un10_cry_2                GTP_LUT5CARRY     CIN      In      -         5.303       -         
dvi_encoder_m0.encb.un10_cry_2                GTP_LUT5CARRY     COUT     Out     0.034     5.338       -         
un10_cry_2                                    Net               -        -       0.000     -           1         
dvi_encoder_m0.encb.un10_cry_3                GTP_LUT5CARRY     CIN      In      -         5.338       -         
dvi_encoder_m0.encb.un10_cry_3                GTP_LUT5CARRY     Z        Out     0.232     5.569       -         
un10_cry_3_Z_1                                Net               -        -       0.000     -           1         
dvi_encoder_m0.encb.cnt[3]                    GTP_DFF_C         D        In      -         5.569       -         
=================================================================================================================
Total path delay (propagation time + setup) of 5.546 is 3.039(54.8%) logic and 2.508(45.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: video_pll|clkout1_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                       Starting                                                                        Arrival            
Instance                                               Reference                            Type          Pin     Net                  Time        Slack  
                                                       Clock                                                                                              
----------------------------------------------------------------------------------------------------------------------------------------------------------
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[2]         video_pll|clkout1_inferred_clock     GTP_DFF_R     Q       TMDS_mod5[2]         0.290       998.638
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_0h[0]     video_pll|clkout1_inferred_clock     GTP_DFF       Q       TMDS_shift_0h[0]     0.290       999.030
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_0l[0]     video_pll|clkout1_inferred_clock     GTP_DFF       Q       TMDS_shift_0l[0]     0.290       999.030
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_1h[0]     video_pll|clkout1_inferred_clock     GTP_DFF       Q       TMDS_shift_1h[0]     0.290       999.030
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_1l[0]     video_pll|clkout1_inferred_clock     GTP_DFF       Q       TMDS_shift_1l[0]     0.290       999.030
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_2h[0]     video_pll|clkout1_inferred_clock     GTP_DFF_R     Q       TMDS_shift_2h[0]     0.290       999.030
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_2l[0]     video_pll|clkout1_inferred_clock     GTP_DFF_R     Q       TMDS_shift_2l[0]     0.290       999.030
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_3h[0]     video_pll|clkout1_inferred_clock     GTP_DFF_R     Q       TMDS_shift_3h[0]     0.290       999.030
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_3l[0]     video_pll|clkout1_inferred_clock     GTP_DFF_R     Q       TMDS_shift_3l[0]     0.290       999.030
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[0]         video_pll|clkout1_inferred_clock     GTP_DFF_R     Q       CO0                  0.290       999.038
==========================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                       Starting                                                                     Required            
Instance                                               Reference                            Type           Pin     Net              Time         Slack  
                                                       Clock                                                                                            
--------------------------------------------------------------------------------------------------------------------------------------------------------
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[0]         video_pll|clkout1_inferred_clock     GTP_DFF_R      R       TMDS_mod5[2]     999.693      998.638
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[1]         video_pll|clkout1_inferred_clock     GTP_DFF_RE     R       TMDS_mod5[2]     999.693      998.638
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[2]         video_pll|clkout1_inferred_clock     GTP_DFF_R      R       TMDS_mod5[2]     999.693      998.638
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_2h[0]     video_pll|clkout1_inferred_clock     GTP_DFF_R      R       TMDS_mod5[2]     999.693      998.638
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_2l[0]     video_pll|clkout1_inferred_clock     GTP_DFF_R      R       TMDS_mod5[2]     999.693      998.638
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_3h[0]     video_pll|clkout1_inferred_clock     GTP_DFF_R      R       TMDS_mod5[2]     999.693      998.638
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_3h[1]     video_pll|clkout1_inferred_clock     GTP_DFF_R      R       TMDS_mod5[2]     999.693      998.638
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_3h[2]     video_pll|clkout1_inferred_clock     GTP_DFF_R      R       TMDS_mod5[2]     999.693      998.638
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_3l[0]     video_pll|clkout1_inferred_clock     GTP_DFF_R      R       TMDS_mod5[2]     999.693      998.638
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_3l[1]     video_pll|clkout1_inferred_clock     GTP_DFF_R      R       TMDS_mod5[2]     999.693      998.638
========================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      1000.000
    - Setup time:                            0.307
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         999.693

    - Propagation time:                      1.055
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 998.638

    Number of logic level(s):                0
    Starting point:                          dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[2] / Q
    Ending point:                            dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[0] / R
    The start point is clocked by            video_pll|clkout1_inferred_clock [rising] on pin CLK
    The end   point is clocked by            video_pll|clkout1_inferred_clock [rising] on pin CLK

Instance / Net                                                   Pin      Pin               Arrival     No. of    
Name                                               Type          Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[2]     GTP_DFF_R     Q        Out     0.290     0.290       -         
TMDS_mod5[2]                                       Net           -        -       0.765     -           41        
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[0]     GTP_DFF_R     R        In      -         1.055       -         
==================================================================================================================
Total path delay (propagation time + setup) of 1.362 is 0.597(43.8%) logic and 0.765(56.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      1000.000
    - Setup time:                            0.307
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         999.693

    - Propagation time:                      1.055
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 998.638

    Number of logic level(s):                0
    Starting point:                          dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[2] / Q
    Ending point:                            dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[1] / R
    The start point is clocked by            video_pll|clkout1_inferred_clock [rising] on pin CLK
    The end   point is clocked by            video_pll|clkout1_inferred_clock [rising] on pin CLK

Instance / Net                                                    Pin      Pin               Arrival     No. of    
Name                                               Type           Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[2]     GTP_DFF_R      Q        Out     0.290     0.290       -         
TMDS_mod5[2]                                       Net            -        -       0.765     -           41        
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[1]     GTP_DFF_RE     R        In      -         1.055       -         
===================================================================================================================
Total path delay (propagation time + setup) of 1.362 is 0.597(43.8%) logic and 0.765(56.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      1000.000
    - Setup time:                            0.307
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         999.693

    - Propagation time:                      1.055
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 998.638

    Number of logic level(s):                0
    Starting point:                          dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[2] / Q
    Ending point:                            dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_3h[2] / R
    The start point is clocked by            video_pll|clkout1_inferred_clock [rising] on pin CLK
    The end   point is clocked by            video_pll|clkout1_inferred_clock [rising] on pin CLK

Instance / Net                                                       Pin      Pin               Arrival     No. of    
Name                                                   Type          Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[2]         GTP_DFF_R     Q        Out     0.290     0.290       -         
TMDS_mod5[2]                                           Net           -        -       0.765     -           41        
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_3h[2]     GTP_DFF_R     R        In      -         1.055       -         
======================================================================================================================
Total path delay (propagation time + setup) of 1.362 is 0.597(43.8%) logic and 0.765(56.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                                         Starting                                                            Arrival            
Instance                                                 Reference     Type           Pin               Net                  Time        Slack  
                                                         Clock                                                                                  
------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1                   System        GTP_PLL_E1     CLKOUT0           pll_phy_clk          0.000       998.719
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy     System        GTP_DLL        DELAY_STEP[0]     dll_step_copy[0]     0.000       999.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy     System        GTP_DLL        DELAY_STEP[1]     dll_step_copy[1]     0.000       999.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy     System        GTP_DLL        DELAY_STEP[2]     dll_step_copy[2]     0.000       999.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy     System        GTP_DLL        DELAY_STEP[3]     dll_step_copy[3]     0.000       999.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy     System        GTP_DLL        DELAY_STEP[4]     dll_step_copy[4]     0.000       999.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy     System        GTP_DLL        DELAY_STEP[5]     dll_step_copy[5]     0.000       999.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy     System        GTP_DLL        DELAY_STEP[6]     dll_step_copy[6]     0.000       999.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy     System        GTP_DLL        DELAY_STEP[7]     dll_step_copy[7]     0.000       999.731
u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1                   System        GTP_PLL_E1     LOCK              pll_lock_c           0.000       999.731
================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                   Starting                                                   Required            
Instance                                                                           Reference     Type          Pin       Net                  Time         Slack  
                                                                                   Clock                                                                          
------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dll_hmemc_dut                  System        GTP_DLL       CLKIN     ioclk_01_i           1000.000     998.719
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy                               System        GTP_DLL       CLKIN     pll_phy_clk          1000.000     999.692
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[0]     System        GTP_DFF_C     D         dll_step_copy[0]     1000.020     999.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[1]     System        GTP_DFF_C     D         dll_step_copy[1]     1000.020     999.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[2]     System        GTP_DFF_C     D         dll_step_copy[2]     1000.020     999.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[3]     System        GTP_DFF_C     D         dll_step_copy[3]     1000.020     999.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[4]     System        GTP_DFF_C     D         dll_step_copy[4]     1000.020     999.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[5]     System        GTP_DFF_C     D         dll_step_copy[5]     1000.020     999.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[6]     System        GTP_DFF_C     D         dll_step_copy[6]     1000.020     999.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[7]     System        GTP_DFF_C     D         dll_step_copy[7]     1000.020     999.731
==================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      1000.000
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         1000.000

    - Propagation time:                      1.281
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 998.719

    Number of logic level(s):                1
    Starting point:                          u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1 / CLKOUT0
    Ending point:                            u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dll_hmemc_dut / CLKIN
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                                                          Pin         Pin               Arrival     No. of    
Name                                                                   Type             Name        Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1                                 GTP_PLL_E1       CLKOUT0     Out     0.000     0.000       -         
pll_phy_clk                                                            Net              -           -       0.308     -           3         
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclkbuf01_dut     GTP_IOCLKBUF     CLKIN       In      -         0.308       -         
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclkbuf01_dut     GTP_IOCLKBUF     CLKOUT      Out     0.306     0.615       -         
ioclk_01_i                                                             Net              -           -       0.667     -           21        
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dll_hmemc_dut      GTP_DLL          CLKIN       In      -         1.281       -         
============================================================================================================================================
Total path delay (propagation time + setup) of 1.281 is 0.306(23.9%) logic and 0.975(76.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      1000.000
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         1000.000

    - Propagation time:                      0.308
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 999.692

    Number of logic level(s):                0
    Starting point:                          u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1 / CLKOUT0
    Ending point:                            u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy / CLKIN
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                                          Pin         Pin               Arrival     No. of    
Name                                                     Type           Name        Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1                   GTP_PLL_E1     CLKOUT0     Out     0.000     0.000       -         
pll_phy_clk                                              Net            -           -       0.308     -           3         
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy     GTP_DLL        CLKIN       In      -         0.308       -         
============================================================================================================================
Total path delay (propagation time + setup) of 0.308 is 0.000(0.0%) logic and 0.308(100.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      1000.000
    - Setup time:                            -0.020
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1000.020

    - Propagation time:                      0.289
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 999.731

    Number of logic level(s):                0
    Starting point:                          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy / DELAY_STEP[0]
    Ending point:                            u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[0] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            pll_50_400|clkout1_inferred_clock [rising] on pin CLK

Instance / Net                                                                                   Pin               Pin               Arrival     No. of    
Name                                                                               Type          Name              Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy                               GTP_DLL       DELAY_STEP[0]     Out     0.000     0.000       -         
dll_step_copy[0]                                                                   Net           -                 -       0.289     -           2         
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[0]     GTP_DFF_C     D                 In      -         0.289       -         
===========================================================================================================================================================
Total path delay (propagation time + setup) of 0.269 is -0.020(-7.4%) logic and 0.289(107.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied

Finished final timing analysis (Real Time elapsed 0h:00m:44s; CPU Time elapsed 0h:00m:34s; Memory used current: 420MB peak: 460MB)


Finished timing report (Real Time elapsed 0h:00m:44s; CPU Time elapsed 0h:00m:34s; Memory used current: 420MB peak: 460MB)

---------------------------------------
Resource Usage Report for ipsl_hmemc_top_test 

Mapping to part: pgl22gbg324-7
Cell usage:
GTP_DDC_E1      5 uses
GTP_DDRC        1 use
GTP_DDRPHY      1 use
GTP_DFF         122 uses
GTP_DFF_C       482 uses
GTP_DFF_CE      491 uses
GTP_DFF_E       19 uses
GTP_DFF_P       20 uses
GTP_DFF_PE      19 uses
GTP_DFF_R       9 uses
GTP_DFF_RE      1 use
GTP_DFF_S       1 use
GTP_DLL         2 uses
GTP_DRM18K      4 uses
GTP_GRS         1 use
GTP_INV         69 uses
GTP_IOCLKBUF    2 uses
GTP_IOCLKDIV    1 use
GTP_IODELAY     16 uses
GTP_ISERDES     16 uses
GTP_LUT2        432 uses
GTP_LUT3        356 uses
GTP_LUT4        237 uses
GTP_LUT5        336 uses
GTP_LUT5CARRY   658 uses
GTP_OSERDES     54 uses
GTP_PLL_E1      2 uses
GTP_ROM64X1     30 uses

I/O ports: 78
GTP_INBUF      4 uses
GTP_INBUFG     2 uses
GTP_IOBUF      16 uses
GTP_IOBUFCO    2 uses
GTP_OUTBUF     13 uses
GTP_OUTBUFT    37 uses
GTP_OUTBUFTCO  1 use


RAM/ROM usage summary

Distributed Rams : 30.00 of 1110 (2.70%)


Mapping Summary:
Total LUTs: 2079 of 17536 (11.86%)
	LUTs as dram: 0 of 4440 (0.00%)
	LUTs as logic: 2079 
Total Registers: 1164 of 26304 (4.43%)

DRM18K:
Total DRM18K =  4 of 48 (8.33%)

APMs:
Total APMs =  0.00 of 30 (0.00%)

Total I/O primitives =  75 of 240 (31.25%)


 Number of unique control sets:              71
 CLK(clkout3_i), C(rst_n_c_i_0), P(GND), CE(VCC)		: 125
 CLK(clkout3_i), C(GND), P(GND), CE(VCC)		: 1
 CLK(clkout3_i), C(GND), P(rst_n_c_i_0), CE(VCC)		: 4
 CLK(clkout3_i), C(rst_n_c_i_0), P(GND), CE(N_490_i_0)		: 2
 CLK(clkout3_i), C(rst_n_c_i_0), P(GND), CE(rd_state_0_sqmuxa)		: 2
 CLK(clkout3_i), C(rst_n_c_i_0), P(GND), CE(un1_M_AXI_AWLOCK_15_0)		: 21
 CLK(clkout3_i), C(rst_n_c_i_0), P(GND), CE(reg_rd_lence[0])		: 2
 CLK(clkout3_i), C(rst_n_c_i_0), P(GND), CE(un1_MASTER_RST_2_0_0)		: 21
 CLK(clkout3_i), C(rst_n_c_i_0), P(GND), CE(reg_wr_lence[0])		: 2
 CLK(clkout3_i), C(rst_n_c_i_0), P(GND), CE(reg_w_lene)		: 8
 CLK(clkout3_i), C(rst_n_c_i_0), P(GND), CE(reg_r_lene)		: 8
 CLK(clkout3_i), C(rst_n_c_i_0), P(GND), CE(rd_fifo_cnte)		: 32
 CLK(clkout1_i), C(global_reset_i_0), P(GND), CE(dll_step_copy_synced4_NE_i_0)		: 8
 CLK(clkout1_i), C(GND), P(global_reset_i_0), CE(VCC)		: 5
 CLK(clkout1_i), C(global_reset_i_0), P(GND), CE(VCC)		: 41
 CLK(dll_update_n_i), C(global_reset_i_0), P(GND), CE(VCC)		: 8
 CLK(clkout1_i), C(GND), P(GND), CE(VCC)		: 34
 CLK(clkout1_i), C(GND), P(global_reset_i_0), CE(N_82_i_0)		: 1
 CLK(clkout1_i), C(global_reset_i_0), P(GND), CE(N_82_i_0)		: 1
 CLK(clkout1_i), C(rst_n_c_i_0), P(GND), CE(VCC)		: 17
 CLK(clkout1_i), C(GND), P(rst_n_c_i_0), CE(VCC)		: 1
 CLK(clkout1_i), C(rst_n_c_i_0), P(GND), CE(N_6_i_0)		: 8
 CLK(clkout1_i), C(presetn_i_0), P(GND), CE(VCC)		: 3
 CLK(clkout1_i), C(presetn_i_0), P(GND), CE(cnte)		: 7
 CLK(clkout1_i), C(resetn_i_0), P(GND), CE(un1_init_preset8_0_a2)		: 1
 CLK(clkout1_i), C(GND), P(resetn_i_0), CE(un1_init_preset8_0_a2)		: 1
 CLK(clkout1_i), C(GND), P(resetn_i_0), CE(VCC)		: 1
 CLK(clkout1_i), C(GND), P(resetn_i_0), CE(ddrc_init_done)		: 1
 CLK(clkout1_i), C(resetn_i_0), P(GND), CE(ddrc_init_done)		: 1
 CLK(clkout1_i), C(resetn_i_0), P(GND), CE(ddrc_rst_cnte)		: 5
 CLK(clkout1_i), C(resetn_i_0), P(GND), CE(rst_cnt7)		: 5
 CLK(clkout3_i), C(rst_n_c_i_0), P(GND), CE(read_cnte)		: 19
 CLK(clkout0_i), C(read_fifo_aclr), P(GND), CE(VCC)		: 36
 CLK(clkout3_i), C(read_fifo_aclr), P(GND), CE(VCC)		: 39
 CLK(clkout0_i), C(GND), P(read_fifo_aclr), CE(VCC)		: 1
 CLK(clkout3_i), C(rst_n_c_i_0), P(GND), CE(write_cnte)		: 19
 CLK(clkout3_i), C(write_fifo_aclr), P(GND), CE(VCC)		: 38
 CLK(sys_clk_c[0]), C(write_fifo_aclr), P(GND), CE(VCC)		: 37
 CLK(clkout3_i), C(GND), P(write_fifo_aclr), CE(VCC)		: 1
 CLK(clkout0_i), C(rst_n_c_i_0), P(GND), CE(VCC)		: 87
 CLK(clkout0_i), C(rst_n_c_i_0), P(GND), CE(hs_reg5)		: 12
 CLK(clkout0_i), C(GND), P(GND), CE(rst_n_c)		: 3
 CLK(clkout1_i), R(TMDS_mod5[2]), S(GND), CE(CO0)		: 1
 CLK(clkout1_i), R(TMDS_mod5[2]), S(GND), CE(VCC)		: 9
 CLK(clkout0_i), C(GND), P(GND), CE(VCC)		: 88
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(N_54_i_0)		: 8
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(N_52_i_0)		: 8
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(clk_edge_cnte)		: 6
 CLK(sys_clk_c[0]), C(GND), P(rst_n_c_i_0), CE(VCC)		: 7
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(VCC)		: 51
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(un1_CS_reg_1_sqmuxa_i_0)		: 5
 CLK(sys_clk_c[0]), C(GND), P(rst_n_c_i_0), CE(N_95_i_0)		: 8
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(block_read_data5)		: 8
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(byte_cnte)		: 16
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(state_i_0[4])		: 10
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(N_165_i_0)		: 43
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(state_ns_a3_0[5])		: 32
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(bmp_datace[0])		: 8
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(bmp_datace[8])		: 8
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(bmp_datace[16])		: 8
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(sd_init_done)		: 2
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(N_342_0)		: 32
 CLK(sys_clk_c[0]), C(GND), P(GND), CE(width_0_sqmuxa)		: 16
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(header_1_0_sqmuxa)		: 8
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(header_0_0_sqmuxa)		: 8
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(N_344_i_0)		: 23
 CLK(sys_clk_c[0]), C(GND), P(rst_n_c_i_0), CE(N_344_i_0)		: 6
 CLK(sys_clk_c[0]), C(GND), P(rst_n_c_i_0), CE(un1_state43_1_0_a2)		: 2
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(bmp_len_cnte)		: 32
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(rd_cnte)		: 10
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(q_rege)		: 32

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:44s; CPU Time elapsed 0h:00m:34s; Memory used current: 239MB peak: 460MB)

Process took 0h:00m:44s realtime, 0h:00m:34s cputime
# Tue May  7 16:41:38 2019

###########################################################]
