IP Generator (Version 2020.3 build 62942)
Check out license ...
Start generating at 2022-04-23 22:29
Instance: FIFO56x32 (D:\FPGA_CODE\Other_work\fruit\Test\Test_fifo\ipcore\FIFO56x32\FIFO56x32.idf)
Model: Distributed FIFO (1.2)
Part: Logos-PGL22G-MBG324--6
Create directory 'rtl' ...
Copy 'rtl\ipm_distributed_fifo_ctr_v1_0.v' to 'rtl' ...
Copy 'rtl\ipm_distributed_fifo_v1_2.v.xml' to 'rtl' ...
Copy 'rtl\ipm_distributed_sdpram_v1_2.v.xml' to 'rtl' ...
Compile file 'rtl\ipm_distributed_fifo_v1_2.v.xml' to 'rtl\ipm_distributed_fifo_v1_2_FIFO56x32.v' ...
Compile file 'rtl\ipm_distributed_sdpram_v1_2.v.xml' to 'rtl\ipm_distributed_sdpram_v1_2_FIFO56x32.v' ...
Copy 'ipm_distributed_fifo_wrapper_v1_2.v.xml' ...
Copy 'ipm_distributed_fifo_wrapper_v1_2_tb.v.xml' ...
Compile file 'ipm_distributed_fifo_wrapper_v1_2.v.xml' to 'FIFO56x32.v' ...
Found top module 'FIFO56x32' in file 'FIFO56x32.v'.
Compile file 'ipm_distributed_fifo_wrapper_v1_2_tb.v.xml' to 'FIFO56x32_tb.v' ...
Create template file 'FIFO56x32_tmpl.v' ...
Create template file 'FIFO56x32_tmpl.vhdl' ...
There are 4 source files to synthesize.
Synthesis is disabled.
Done: 0 error(s), 0 warning(s)
