./../example_design/bench/ddr_test_top_tb.v                                 
./../example_design/bench/mem/ddr3.v                                        
./../example_design/bench/mem/ddr3_parameters.vh                            
                                                                            
./../example_design/rtl/test_rd_ctrl_128bit.v                               
./../example_design/rtl/test_wr_ctrl_128bit.v                               
./../example_design/rtl/test_rd_ctrl_64bit.v                                
./../example_design/rtl/test_wr_ctrl_64bit.v                                
./../example_design/rtl/ipsl_hmemc_top_test.v                                
./../example_design/rtl/test_main_ctrl.v                                    
./../example_design/rtl/prbs31_128bit.v                                     
                                                                            
./../rtl/pll/pll_50_400.v                                                   
./../rtl/ipsl_ddrc_apb_reset.v                                                   
./../rtl/ipsl_ddrc_reset_ctrl.v                                              
./../rtl/ipsl_ddrphy_dll_update_ctrl.v                                       
./../rtl/ipsl_ddrphy_reset_ctrl.v                                            
./../rtl/ipsl_ddrphy_training_ctrl.v                                         
./../rtl/ipsl_ddrphy_update_ctrl.v                                           
./../rtl/ipsl_hmemc_ddrc_top.v                                               
./../rtl/ipsl_hmemc_phy_top.v                                                
./../rtl/ipsl_phy_io.v                                                       
./../ddr3.v                                                            
                                                                            
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/rstn_sync.vp                       
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/sync.vp                                           
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/sync_h.vp                                         
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/sadrlspk42p32x64m1b1w0c0p0d0t0_fast_func.vp       
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/sadrlspk42p32x64m1b1w0c0p0d0t0read_fast_func.vp   
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/DWC_ddr_umctl2_cc_constants.vp               
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/ddrc_parameters.vp                           
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/apb/DWC_ddr_umctl2_apb_defines.vp            
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/DWC_ddr_umctl2.vp                            
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/xpi/DWC_ddr_umctl2_retime.vp                 
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/xpi/DWC_ddr_umctl2_bcm21.vp                  
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/xpi/DWC_ddr_umctl2_bcm05.vp                  
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/xpi/DWC_ddr_umctl2_bcm07.vp                  
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/xpi/DWC_ddr_umctl2_bcm02.vp                  
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/xpi/DWC_ddr_umctl2_bcm06.vp                  
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/xpi/DWC_ddr_umctl2_bcm50.vp                  
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/xpi/DWC_ddr_umctl2_bcm56.vp                  
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/xpi/DWC_ddr_umctl2_bcm_wrap_mem_array.vp     
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/xpi/DWC_ddr_umctl2_bcm57.vp                  
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/xpi/DWC_ddr_umctl2_bcm65.vp                  
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/rt/DWC_ddr_umctl2_gfifo.vp                   
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/te/te_mux.vp                                 
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/be/bypass.vp                                 
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/rd/rd.vp                                     
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/ih/ih_core_in_if.vp                          
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/ih/ih_core_out_if.vp                         
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/ih/ih_address_map.vp                         
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/ih/ih_address_map_wrapper.vp                 
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/ih/ih_be_if.vp                               
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/ih/ih_te_if.vp                               
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/ih/ih_fifo_if.vp                             
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/ih/ih_fifo_control.vp                        
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/ih/ih.vp                                     
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/mr/mr_data_steering.vp                       
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/mr/mr_ram_rd_pipeline.vp                     
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/mr/mr.vp                                     
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/pi/pi.vp                                     
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/rt/rt.vp                                     
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/select_nets/select_node.vp                   
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/select_nets/select_net.vp                    
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/select_nets/select_node_lite.vp              
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/select_nets/select_net_lite.vp               
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/te/te_nxt_vp_update.vp                       
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/te/te_filter_vp.vp                           
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/te/te_filter.vp                              
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/te/te_rd_nxt.vp                              
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/te/te_wr_nxt.vp                              
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/te/te_rd_replace.vp                          
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/te/te_wr_replace.vp                          
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/te/te_rd_cam.vp                              
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/te/te_rd_entry.vp                            
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/te/te_rd_mux.vp                              
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/te/teengine.vp                               
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/te/te_wr_cam.vp                              
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/te/te_wr_entry.vp                            
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/te/te_wr_mux.vp                              
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/te/te_misc.vp                                
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/ts/bsm.vp                                    
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/ts/gs_phyupd.vp                              
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/ts/gs_phymstr.vp                             
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/ts/gs_ctrlupd.vp                             
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/ts/gs_zq_calib.vp                            
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/ts/gs_global_constraints.vp                  
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/ts/gs_global_fsm.vp                          
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/ts/gs_global_fsm_sr_hw_lp.vp                 
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/ts/gs_dfilp.vp                               
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/ts/gs_q_fsm.vp                               
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/ts/gs_glue.vp                                
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/ts/gs_init_ddr_fsm.vp                        
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/ts/gs_next_xact.vp                           
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/ts/gs_rank_constraints.vp                    
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/ts/gs_odt.vp                                 
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/ts/gs.vp                                     
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/ts/gs_load_mr.vp                             
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/ts/gs_ref_rdwr_switch.vp                     
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/ts/os_glue.vp                                
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/ts/ts.vp                                     
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/wu/memc_wu.vp                                
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/wu/memc_wu_wdata_if.vp                       
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/fifo/sync_fifo_rst.vp                        
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrc_source_codes/ddrc/fifo/ingot_sync_fifo_flopout_rst.vp          
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C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrphy_source_codes/ddrphy/pgl_ddrphy_slice_rddata_align.vp       
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrphy_source_codes/ddrphy/pgl_ddrphy_slice_top.vp                
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrphy_source_codes/ddrphy/pgl_ddrphy_wdata_path_adj.vp           
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrphy_source_codes/ddrphy/pgl_ddrphy_wrlvl.vp                    
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrphy_source_codes/ddrphy/pgl_ddrphy_update.vp                   
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrphy_source_codes/ddrphy/pgl_ddrphy_rowaddr.vp                  
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrphy_source_codes/ddrphy/pgl_ddrphy_top.vp                      
C:\pango\PDS_2019.1-patch2\ip\system_ip\ipsl_hmemc\ipsl_hmemc_eval\ipsl_hmemc/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/ddrphy_source_codes/ddrphy/pgl_ddrphy_gatecal.vp                  
                                                                     
+define+SIMULATION  
+define+den4096Mb   
+define+sg25E       
+define+x16         
