#Generated by Fabric Compiler ( version 2019.1-patch2 <build 42169> ) at Tue May  7 09:59:54 2019

set_arch -family Logos -device PGL22G -speedgrade -7 -package BG324
synthesize -synplify_pro 
dev_map 
pnr 
report_timing 
gen_bit_stream 
set_arch -family Logos -device PGL22G -speedgrade -7 -package BG324
synthesize -synplify_pro 
dev_map 
set_arch -family Logos -device PGL22G -speedgrade -7 -package BG324
synthesize -synplify_pro 
dev_map 
pnr 
set_arch -family Logos -device PGL22G -speedgrade -7 -package BG324
synthesize -synplify_pro 
set_arch -family Logos -device PGL22G -speedgrade -7 -package BG324
synthesize -synplify_pro 
set_arch -family Logos -device PGL22G -speedgrade -7 -package BG324
synthesize -synplify_pro 
dev_map 
pnr 
set_arch -family Logos -device PGL22G -speedgrade -7 -package BG324
synthesize -synplify_pro 
dev_map 
pnr 
set_arch -family Logos -device PGL22G -speedgrade -7 -package BG324
synthesize -synplify_pro 
dev_map 
set_arch -family Logos -device PGL22G -speedgrade -7 -package BG324
synthesize -synplify_pro 
dev_map 
pnr 
set_arch -family Logos -device PGL22G -speedgrade -7 -package BG324
synthesize -synplify_pro 
dev_map 
pnr 
pnr 
set_arch -family Logos -device PGL22G -speedgrade -7 -package BG324
synthesize -synplify_pro 
dev_map 
pnr 
set_arch -family Logos -device PGL22G -speedgrade -7 -package BG324
synthesize -synplify_pro 
dev_map 
pnr 
set_arch -family Logos -device PGL22G -speedgrade -7 -package BG324
synthesize -synplify_pro 
dev_map 
pnr 
report_timing 
gen_bit_stream 
set_arch -family Logos -device PGL22G -speedgrade -7 -package BG324
synthesize -synplify_pro 
dev_map 
pnr 
report_timing 
gen_bit_stream 
set_arch -family Logos -device PGL22G -speedgrade -7 -package BG324
synthesize -synplify_pro 
dev_map 
set_arch -family Logos -device PGL22G -speedgrade -7 -package BG324
synthesize -synplify_pro 
dev_map 
pnr 
report_timing 
gen_bit_stream 
set_arch -family Logos -device PGL22G -speedgrade -7 -package BG324
synthesize -synplify_pro 
dev_map 
pnr 
report_timing 
gen_bit_stream 
set_arch -family Logos -device PGL22G -speedgrade -7 -package BG324
synthesize -synplify_pro 
dev_map 
pnr 
report_timing 
gen_bit_stream 
set_arch -family Logos -device PGL22G -speedgrade -7 -package BG324
synthesize -synplify_pro 
dev_map 
pnr 
report_timing 
gen_bit_stream 
add_design D:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/source/video_pll/inst.idf
add_design D:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/source/afifo_64i_32o_128/inst.idf
add_design D:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/source/afifo_32i_64o_256/inst.idf
add_design "D:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/source/dvi_tx/dvi_encoder.v"
add_design "D:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/source/dvi_tx/encode.v"
add_design "D:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/source/dvi_tx/serdes_4b_10to1.v"
add_design "D:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/source/sd_card/sd_card_cmd.v"
add_design "D:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/source/sd_card/sd_card_sec_read_write.v"
add_design "D:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/source/sd_card/sd_card_top.v"
add_design "D:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/source/sd_card/spi_master.v"
add_design "D:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/source/src/aq_axi_master.v"
add_design "D:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/source/src/ax_debounce.v"
add_design "D:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/source/src/bmp_read.v"
add_design "D:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/source/src/color_bar.v"
add_design "D:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/source/src/frame_fifo_read.v"
add_design "D:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/source/src/frame_fifo_write.v"
add_design "D:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/source/src/frame_read_write.v"
add_design "D:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/source/src/sd_card_bmp.v"
add_design "D:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/source/src/top.v"
add_design "D:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/source/src/video_timing_data.v"
remove_design -force -verilog "D:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/source/src/top.v"
set_arch -family Logos -device PGL22G -speedgrade -7 -package BG324
synthesize -synplify_pro 
set_arch -family Logos -device PGL22G -speedgrade -7 -package BG324
synthesize -synplify_pro 
dev_map 
pnr 
report_timing 
gen_bit_stream 
set_arch -family Logos -device PGL22G -speedgrade -7 -package BG324
synthesize -synplify_pro 
dev_map 
pnr 
report_timing 
gen_bit_stream 
set_arch -family Logos -device PGL22G -speedgrade -7 -package BG324
synthesize -synplify_pro 
dev_map 
pnr 
report_timing 
gen_bit_stream 
remove_design -verilog "D:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/example_design/rtl/test_wr_ctrl_64bit.v"
remove_design -verilog "D:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/example_design/rtl/test_rd_ctrl_64bit.v"
remove_design -verilog "D:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/example_design/rtl/prbs31_128bit.v"
remove_design -verilog "D:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/example_design/rtl/test_main_ctrl.v"
add_design "D:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/source/src/video_define.v"
set_arch -family Logos -device PGL22G -speedgrade -7 -package BG324
synthesize -synplify_pro 
dev_map 
pnr 
report_timing 
gen_bit_stream 
pnr -mode "fast" -optimize_multi_corner_timing -fix_hold_violation 
report_timing 
gen_bit_stream 
pnr -mode "performance" -optimize_multi_corner_timing -place_only -fix_hold_violation 
pnr -mode "performance" -optimize_multi_corner_timing -fix_hold_violation 
report_timing 
gen_bit_stream 
pnr -mode "fast" -fix_hold_violation 
report_timing 
gen_bit_stream 
set_arch -family Logos -device PGL22G -speedgrade -7 -package BG324
synthesize -synplify_pro 
dev_map 
pnr -mode "fast" -fix_hold_violation 
report_timing 
gen_bit_stream 
pnr -mode "fast" -optimize_multi_corner_timing -fix_hold_violation 
report_timing 
gen_bit_stream 
set_arch -family Logos -device PGL22G -speedgrade -7 -package BG324
synthesize -synplify_pro 
dev_map 
pnr -mode "fast" -fix_hold_violation 
report_timing 
gen_bit_stream 
