///////////////////////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2014 PANGO MICROSYSTEMS, INC
// ALL RIGHTS REVERVED.
//
// THE SOURCE CODE CONTAINED HEREIN IS PROPRIETARY TO PANGO MICROSYSTEMS, INC.
// IT SHALL NOT BE REPRODUCED OR DISCLOSED IN WHOLE OR IN PART OR USED BY
// PARTIES WITHOUT WRITTEN AUTHORIZATION FROM THE OWNER.
//
//////////////////////////////////////////////////////////////////////////////
//the trig_unit module, it get the match information
//
//
// Modification history
//change rst intitial value from parameter,2020/06/01
//----------------------------------------------------------------------

module ips_dbc_trig_unit_v1_3
#(
  parameter  NEW_JTAG_IF               = 1,
  parameter  MU_PIPELINE               = 0,	    //0~4, EXPERIMENTAL
  parameter  MU_TYPE                   = 1,	    //0~5, basic/basic+edge/extended/extended+edge/range/range+edge
  parameter  MU_WIDTH                  = 8,	    //1~256
  parameter  MU_CNT                    = 0,	    //0~32, 0=Disable
  parameter  SIGNAL_MSB                = 1,	    //= MU_TYPE[0]==0 ? MU_WIDTH-(MU_CNT==0) : MU_WIDTH*2-(MU_CNT==0);    
  parameter  MU_CHAIN_BIT              = 25,	  //{mu_function,mu_bit0,mu_bit1...mu_bit255,mu_cnt_mode,mu_cnt_value}
  parameter [804:0] INIT_MU_CONFIG_SRC = 0   //the initial trig unit config which the jtag still not available
 )
(
  input                         h_rstn      ,
  input [1:0]                   clk_conf_trig ,
  input [1:0]                   rst_conf_trig ,
  input                         conf_sel      ,
  input                         conf_tdi      ,
  input                         shift_i,
  input [SIGNAL_MSB:0]          signal_combine,
  output                        match,
  input                         trig_mu_neg,
  input                         conf_rden,
  input [4:0]                   conf_id,
  input                         conf_sel_rd,
  output                        conf_rdlast,
  output                        conf_rdata,
  output reg                    test_reg0           
);  	
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`pragma protect end_protected
endmodule