Selecting top level module GTP_LUT5CARRY
@N: CG364 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\synthesize\synplify_impl\syntmp\GTP_LUT5CARRY.v":7:7:7:21|Synthesizing module INT_LUTMUX4_UDP in library work.
Running optimization stage 1 on INT_LUTMUX4_UDP .......
@N: CG364 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\synthesize\synplify_impl\syntmp\GTP_LUT5CARRY.v":25:7:25:21|Synthesizing module INT_LUTMUX2_UDP in library work.
Running optimization stage 1 on INT_LUTMUX2_UDP .......
@N: CG364 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\synthesize\synplify_impl\syntmp\GTP_LUT5CARRY.v":39:7:39:19|Synthesizing module GTP_LUT5CARRY in library work.
@W: CG532 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\synthesize\synplify_impl\syntmp\GTP_LUT5CARRY.v":55:4:55:10|Within an initial block, only Verilog force statements and memory $readmemh/$readmemb initialization statements are recognized, and all other content is ignored.
Running optimization stage 1 on GTP_LUT5CARRY .......
Running optimization stage 2 on GTP_LUT5CARRY .......
@N: CL159 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\synthesize\synplify_impl\syntmp\GTP_LUT5CARRY.v":48:19:48:20|Input ID is unused.
Running optimization stage 2 on INT_LUTMUX2_UDP .......
Running optimization stage 2 on INT_LUTMUX4_UDP .......
