
Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03P-Beta2
Install: C:\pango\PDS_2019.1-patch2\syn
OS: Windows 6.1

Hostname: ALINX000007-PC

Implementation : synplify_impl

# Written on Tue May  7 16:40:50 2019

##### FILES SYNTAX CHECKED ##############################################
Constraint File(s):      "D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\ddr_324_left.fdc"

#Run constraint checker to find more issues with constraints.
#########################################################################



No issues found in constraint syntax.



Clock Summary
*************

          Start                                                        Requested     Requested     Clock        Clock                    Clock
Level     Clock                                                        Frequency     Period        Type         Group                    Load 
----------------------------------------------------------------------------------------------------------------------------------------------
0 -       sys_clk                                                      50.0 MHz      20.000        declared     default_clkgroup         470  
                                                                                                                                              
0 -       System                                                       1.0 MHz       1000.000      system       system_clkgroup          2    
                                                                                                                                              
0 -       pll_50_400|clkout3_inferred_clock                            1.0 MHz       1000.000      inferred     Inferred_clkgroup_0      549  
                                                                                                                                              
0 -       video_pll|clkout0_inferred_clock                             1.0 MHz       1000.000      inferred     Inferred_clkgroup_71     245  
                                                                                                                                              
0 -       pll_50_400|clkout1_inferred_clock                            1.0 MHz       1000.000      inferred     Inferred_clkgroup_1      148  
                                                                                                                                              
0 -       video_pll|clkout1_inferred_clock                             1.0 MHz       1000.000      inferred     Inferred_clkgroup_72     59   
                                                                                                                                              
0 -       ipsl_phy_io_Z8|ioclk_01_inferred_clock                       1.0 MHz       1000.000      inferred     Inferred_clkgroup_4      19   
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_ca_clk_r_03_inferred_clock                1.0 MHz       1000.000      inferred     Inferred_clkgroup_49     12   
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_clkw_ca_03_inferred_clock                 1.0 MHz       1000.000      inferred     Inferred_clkgroup_51     12   
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs0_clk_r_inferred_clock                     1.0 MHz       1000.000      inferred     Inferred_clkgroup_10     10   
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs1_clk_r_inferred_clock                     1.0 MHz       1000.000      inferred     Inferred_clkgroup_37     10   
                                                                                                                                              
0 -       ipsl_ddrphy_dll_update_ctrl|dll_update_n_inferred_clock      1.0 MHz       1000.000      inferred     Inferred_clkgroup_70     9    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_ca_clk_r_01_inferred_clock                1.0 MHz       1000.000      inferred     Inferred_clkgroup_24     9    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_clkw290_0_inferred_clock                  1.0 MHz       1000.000      inferred     Inferred_clkgroup_12     9    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_clkw290_1_inferred_clock                  1.0 MHz       1000.000      inferred     Inferred_clkgroup_38     9    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_clkw_ca_01_inferred_clock                 1.0 MHz       1000.000      inferred     Inferred_clkgroup_26     9    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_90_0_inferred_clock                       1.0 MHz       1000.000      inferred     Inferred_clkgroup_14     8    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_90_1_inferred_clock                       1.0 MHz       1000.000      inferred     Inferred_clkgroup_36     8    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_ca_clk_r_04_inferred_clock                1.0 MHz       1000.000      inferred     Inferred_clkgroup_63     5    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_clkw_ca_04_inferred_clock                 1.0 MHz       1000.000      inferred     Inferred_clkgroup_65     5    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|IOCLK_DIV_inferred_clock                      1.0 MHz       1000.000      inferred     Inferred_clkgroup_2      2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[3]              1.0 MHz       1000.000      inferred     Inferred_clkgroup_13     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[4]              1.0 MHz       1000.000      inferred     Inferred_clkgroup_15     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[5]              1.0 MHz       1000.000      inferred     Inferred_clkgroup_16     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[6]              1.0 MHz       1000.000      inferred     Inferred_clkgroup_17     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[7]              1.0 MHz       1000.000      inferred     Inferred_clkgroup_18     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[10]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_21     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[11]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_22     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[12]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_23     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[27]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_35     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[28]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_39     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[29]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_40     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[32]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_43     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[33]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_44     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[34]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_45     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[35]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_46     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[36]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_47     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|ioclk_02_inferred_clock                       1.0 MHz       1000.000      inferred     Inferred_clkgroup_8      2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[2]              1.0 MHz       1000.000      inferred     Inferred_clkgroup_11     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[9]              1.0 MHz       1000.000      inferred     Inferred_clkgroup_19     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[17]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_25     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[18]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_27     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[19]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_28     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[20]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_29     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[21]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_30     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[22]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_31     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[23]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_32     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[24]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_33     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[25]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_34     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[31]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_41     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[37]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_48     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[40]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_50     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[41]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_52     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[42]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_53     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[43]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_54     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[44]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_55     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[45]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_56     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[46]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_57     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[47]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_58     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[48]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_59     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[49]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_60     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[51]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_61     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[52]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_62     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[55]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_64     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[56]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_66     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[57]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_67     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[58]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_68     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[59]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_69     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[0]     1.0 MHz       1000.000      inferred     Inferred_clkgroup_3      1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[1]     1.0 MHz       1000.000      inferred     Inferred_clkgroup_5      1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[2]     1.0 MHz       1000.000      inferred     Inferred_clkgroup_6      1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[3]     1.0 MHz       1000.000      inferred     Inferred_clkgroup_7      1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[4]     1.0 MHz       1000.000      inferred     Inferred_clkgroup_9      1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_clkw_0_inferred_clock                     1.0 MHz       1000.000      inferred     Inferred_clkgroup_20     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_clkw_1_inferred_clock                     1.0 MHz       1000.000      inferred     Inferred_clkgroup_42     1    
==============================================================================================================================================


Clock Load Summary
******************

                                                             Clock     Source                                                                                             Clock Pin                                                                                                 Non-clock Pin                                                                   Non-clock Pin
Clock                                                        Load      Pin                                                                                                Seq Example                                                                                               Seq Example                                                                     Comb Example 
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
sys_clk                                                      470       sys_clk(port)                                                                                      frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wrptr2[8:0].C     -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
System                                                       2         -                                                                                                  u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc.ACLK_2                                                      -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
pll_50_400|clkout3_inferred_clock                            549       u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1.CLKOUT3(GTP_PLL_E1)                                         u_aq_axi_master.reg_r_last.C                                                                              -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
video_pll|clkout0_inferred_clock                             245       video_pll_m0.u_pll_e1.CLKOUT0(GTP_PLL_E1)                                                          frame_read_write_m0.read_buf.U_ipml_fifo_afifo_64i_32o_128.U_ipml_fifo_ctrl.ASYN_CTRL\.rwptr1[8:0].C      -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
pll_50_400|clkout1_inferred_clock                            148       u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1.CLKOUT1(GTP_PLL_E1)                                         u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc.PCLK                                                        -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
video_pll|clkout1_inferred_clock                             59        video_pll_m0.u_pll_e1.CLKOUT1(GTP_PLL_E1)                                                          dvi_encoder_m0.serdes_4b_10to1_m0.gtp_ogddr0.SERCLK                                                       -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|ioclk_01_inferred_clock                       19        u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclkbuf01_dut.CLKOUT(GTP_IOCLKBUF)            u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.CLKA                                         -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_ca_clk_r_03_inferred_clock                12        u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut.RCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr40_dut.SERCLK                                 -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_clkw_ca_03_inferred_clock                 12        u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut.WCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr40_dut.OCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs0_clk_r_inferred_clock                     10        u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.RCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr2_dut.SERCLK                                  -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs1_clk_r_inferred_clock                     10        u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.RCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr27_dut.SERCLK                                 -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_ddrphy_dll_update_ctrl|dll_update_n_inferred_clock      9         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_dll_update_ctrl.dll_update_n.Q[0](dffr)             u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.last_dll_step[7:0].C                           u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DLL_UPDATE_N     -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_ca_clk_r_01_inferred_clock                9         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut.RCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr17_dut.SERCLK                                 -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_clkw290_0_inferred_clock                  9         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.WCLK_DELAY(GTP_DDC_E1)                u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr2_dut.OCLK                                    -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_clkw290_1_inferred_clock                  9         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.WCLK_DELAY(GTP_DDC_E1)                u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr27_dut.OCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_clkw_ca_01_inferred_clock                 9         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut.WCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr17_dut.OCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_90_0_inferred_clock                       8         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.DQSI_DELAY(GTP_DDC_E1)                u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut.ICLK                                    -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_90_1_inferred_clock                       8         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.DQSI_DELAY(GTP_DDC_E1)                u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr27_dut.ICLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_ca_clk_r_04_inferred_clock                5         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut.RCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr55_dut.SERCLK                                 -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_clkw_ca_04_inferred_clock                 5         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut.WCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr55_dut.OCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|IOCLK_DIV_inferred_clock                      2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclkdiv_dut.CLKDIVOUT(GTP_IOCLKDIV)           u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc.CORE_DDRC_CORE_CLK                                          -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[3]              2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[3](GTP_DDRPHY)          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut.RCLK                                    -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[4]              2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[4](GTP_DDRPHY)          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr4_dut.RCLK                                    -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[5]              2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[5](GTP_DDRPHY)          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr5_dut.RCLK                                    -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[6]              2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[6](GTP_DDRPHY)          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr6_dut.RCLK                                    -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[7]              2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[7](GTP_DDRPHY)          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr7_dut.RCLK                                    -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[10]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[10](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr10_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[11]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[11](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr11_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[12]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[12](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr12_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[27]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[27](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr27_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[28]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[28](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr28_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[29]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[29](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr29_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[32]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[32](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr32_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[33]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[33](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr33_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[34]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[34](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr34_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[35]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[35](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr35_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[36]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[36](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr36_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|ioclk_02_inferred_clock                       2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclkbuf02_dut.CLKOUT(GTP_IOCLKBUF)            u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut.CLKA                                         -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[2]              1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[2](GTP_DDRPHY)          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr2_dut.RCLK                                    -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[9]              1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[9](GTP_DDRPHY)          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr9_dut.RCLK                                    -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[17]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[17](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr17_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[18]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[18](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr18_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[19]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[19](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr19_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[20]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[20](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr20_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[21]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[21](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr21_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[22]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[22](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr22_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[23]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[23](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr23_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[24]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[24](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr24_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[25]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[25](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[31]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[31](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr31_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[37]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[37](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[40]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[40](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr40_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[41]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[41](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr41_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[42]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[42](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr42_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[43]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[43](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr43_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[44]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[44](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr44_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[45]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[45](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr45_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[46]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[46](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr46_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[47]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[47](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr47_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[48]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[48](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr48_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[49]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[49](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr49_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[51]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[51](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr51_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[52]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[52](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[55]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[55](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr55_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[56]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[56](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr56_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[57]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[57](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr57_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[58]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[58](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr58_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[59]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[59](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[0]     1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[0](GTP_DDRPHY)     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.CLKB                                         -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[1]     1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[1](GTP_DDRPHY)     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut.CLKB                                         -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[2]     1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[2](GTP_DDRPHY)     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.CLKB                                         -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[3]     1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[3](GTP_DDRPHY)     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut.CLKB                                         -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[4]     1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[4](GTP_DDRPHY)     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut.CLKB                                         -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_clkw_0_inferred_clock                     1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.WCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr9_dut.OCLK                                    -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_clkw_1_inferred_clock                     1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.WCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr31_dut.OCLK                                   -                                                                               -            
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