Generated by Fabric Compiler ( version 2019.1-patch2 <build 42169> ) at Tue May  7 16:41:43 2019

Compile takes 0.171601 sec.
Top module ipsl_hmemc_top_test is elaborated successfully.
Timing Constraint:
-------------------------------------------------------
create_clock -period 20.000 -waveform {0.000 10.000} -name {sys_clk} [get_ports {sys_clk}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {pll_50_400|clkout3_inferred_clock} [get_pins {u_ipsl_hmemc_top/u_pll_50_400/u_pll_e1:CLKOUT3}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {pll_50_400|clkout1_inferred_clock} [get_pins {u_ipsl_hmemc_top/u_pll_50_400/u_pll_e1:CLKOUT1}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|IOCLK_DIV_inferred_clock} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ioclkdiv_dut:CLKDIVOUT}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[0]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:DQS_CLK_REGIONAL[0]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|ioclk_01_inferred_clock} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ioclkbuf01_dut:CLKOUT}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[1]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:DQS_CLK_REGIONAL[1]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[2]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:DQS_CLK_REGIONAL[2]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[3]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:DQS_CLK_REGIONAL[3]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|ioclk_02_inferred_clock} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ioclkbuf02_dut:CLKOUT}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[4]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:DQS_CLK_REGIONAL[4]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|dqs0_clk_r_inferred_clock} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/dqs0_dut:RCLK}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[2]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[2]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|dqs_clkw290_0_inferred_clock} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/dqs0_dut:WCLK_DELAY}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[3]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[3]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|dqs_90_0_inferred_clock} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/dqs0_dut:DQSI_DELAY}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[4]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[4]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[5]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[5]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[6]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[6]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[7]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[7]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[9]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[9]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|dqs_clkw_0_inferred_clock} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/dqs0_dut:WCLK}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[10]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[10]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[11]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[11]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[12]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[12]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|dqs_ca_clk_r_01_inferred_clock} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/dqs1_dut:RCLK}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[17]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[17]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|dqs_clkw_ca_01_inferred_clock} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/dqs1_dut:WCLK}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[18]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[18]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[19]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[19]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[20]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[20]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[21]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[21]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[22]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[22]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[23]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[23]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[24]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[24]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[25]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[25]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[27]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[27]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|dqs_90_1_inferred_clock} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/dqs2_dut:DQSI_DELAY}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|dqs1_clk_r_inferred_clock} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/dqs2_dut:RCLK}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|dqs_clkw290_1_inferred_clock} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/dqs2_dut:WCLK_DELAY}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[28]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[28]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[29]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[29]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[31]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[31]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|dqs_clkw_1_inferred_clock} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/dqs2_dut:WCLK}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[32]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[32]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[33]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[33]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[34]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[34]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[35]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[35]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[36]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[36]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[37]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[37]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|dqs_ca_clk_r_03_inferred_clock} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/dqs3_dut:RCLK}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[40]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[40]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|dqs_clkw_ca_03_inferred_clock} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/dqs3_dut:WCLK}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[41]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[41]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[42]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[42]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[43]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[43]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[44]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[44]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[45]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[45]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[46]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[46]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[47]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[47]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[48]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[48]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[49]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[49]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[51]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[51]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[52]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[52]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|dqs_ca_clk_r_04_inferred_clock} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/dqs4_dut:RCLK}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[55]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[55]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|dqs_clkw_ca_04_inferred_clock} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/dqs4_dut:WCLK}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[56]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[56]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[57]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[57]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[58]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[58]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[59]} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut:IOL_CLK_SYS[59]}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {ipsl_ddrphy_dll_update_ctrl|dll_update_n_inferred_clock} [get_pins {u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ddrphy_dll_update_ctrl/dll_update_n:Q}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {video_pll|clkout0_inferred_clock} [get_pins {video_pll_m0/u_pll_e1:CLKOUT0}]
create_clock -period 1000.000 -waveform {0.000 500.000} -name {video_pll|clkout1_inferred_clock} [get_pins {video_pll_m0/u_pll_e1:CLKOUT1}]
set_clock_groups -name {Inferred_clkgroup_0} -asynchronous -group [get_clocks {pll_50_400|clkout3_inferred_clock}]
set_clock_groups -name {Inferred_clkgroup_1} -asynchronous -group [get_clocks {pll_50_400|clkout1_inferred_clock}]
set_clock_groups -name {Inferred_clkgroup_2} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|IOCLK_DIV_inferred_clock}]
set_clock_groups -name {Inferred_clkgroup_3} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[0]}]
set_clock_groups -name {Inferred_clkgroup_4} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|ioclk_01_inferred_clock}]
set_clock_groups -name {Inferred_clkgroup_5} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[1]}]
set_clock_groups -name {Inferred_clkgroup_6} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[2]}]
set_clock_groups -name {Inferred_clkgroup_7} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[3]}]
set_clock_groups -name {Inferred_clkgroup_8} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|ioclk_02_inferred_clock}]
set_clock_groups -name {Inferred_clkgroup_9} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[4]}]
set_clock_groups -name {Inferred_clkgroup_10} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|dqs0_clk_r_inferred_clock}]
set_clock_groups -name {Inferred_clkgroup_11} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[2]}]
set_clock_groups -name {Inferred_clkgroup_12} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|dqs_clkw290_0_inferred_clock}]
set_clock_groups -name {Inferred_clkgroup_13} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[3]}]
set_clock_groups -name {Inferred_clkgroup_14} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|dqs_90_0_inferred_clock}]
set_clock_groups -name {Inferred_clkgroup_15} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[4]}]
set_clock_groups -name {Inferred_clkgroup_16} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[5]}]
set_clock_groups -name {Inferred_clkgroup_17} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[6]}]
set_clock_groups -name {Inferred_clkgroup_18} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[7]}]
set_clock_groups -name {Inferred_clkgroup_19} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[9]}]
set_clock_groups -name {Inferred_clkgroup_20} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|dqs_clkw_0_inferred_clock}]
set_clock_groups -name {Inferred_clkgroup_21} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[10]}]
set_clock_groups -name {Inferred_clkgroup_22} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[11]}]
set_clock_groups -name {Inferred_clkgroup_23} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[12]}]
set_clock_groups -name {Inferred_clkgroup_24} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|dqs_ca_clk_r_01_inferred_clock}]
set_clock_groups -name {Inferred_clkgroup_25} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[17]}]
set_clock_groups -name {Inferred_clkgroup_26} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|dqs_clkw_ca_01_inferred_clock}]
set_clock_groups -name {Inferred_clkgroup_27} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[18]}]
set_clock_groups -name {Inferred_clkgroup_28} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[19]}]
set_clock_groups -name {Inferred_clkgroup_29} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[20]}]
set_clock_groups -name {Inferred_clkgroup_30} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[21]}]
set_clock_groups -name {Inferred_clkgroup_31} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[22]}]
set_clock_groups -name {Inferred_clkgroup_32} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[23]}]
set_clock_groups -name {Inferred_clkgroup_33} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[24]}]
set_clock_groups -name {Inferred_clkgroup_34} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[25]}]
set_clock_groups -name {Inferred_clkgroup_35} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[27]}]
set_clock_groups -name {Inferred_clkgroup_36} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|dqs_90_1_inferred_clock}]
set_clock_groups -name {Inferred_clkgroup_37} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|dqs1_clk_r_inferred_clock}]
set_clock_groups -name {Inferred_clkgroup_38} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|dqs_clkw290_1_inferred_clock}]
set_clock_groups -name {Inferred_clkgroup_39} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[28]}]
set_clock_groups -name {Inferred_clkgroup_40} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[29]}]
set_clock_groups -name {Inferred_clkgroup_41} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[31]}]
set_clock_groups -name {Inferred_clkgroup_42} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|dqs_clkw_1_inferred_clock}]
set_clock_groups -name {Inferred_clkgroup_43} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[32]}]
set_clock_groups -name {Inferred_clkgroup_44} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[33]}]
set_clock_groups -name {Inferred_clkgroup_45} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[34]}]
set_clock_groups -name {Inferred_clkgroup_46} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[35]}]
set_clock_groups -name {Inferred_clkgroup_47} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[36]}]
set_clock_groups -name {Inferred_clkgroup_48} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[37]}]
set_clock_groups -name {Inferred_clkgroup_49} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|dqs_ca_clk_r_03_inferred_clock}]
set_clock_groups -name {Inferred_clkgroup_50} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[40]}]
set_clock_groups -name {Inferred_clkgroup_51} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|dqs_clkw_ca_03_inferred_clock}]
set_clock_groups -name {Inferred_clkgroup_52} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[41]}]
set_clock_groups -name {Inferred_clkgroup_53} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[42]}]
set_clock_groups -name {Inferred_clkgroup_54} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[43]}]
set_clock_groups -name {Inferred_clkgroup_55} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[44]}]
set_clock_groups -name {Inferred_clkgroup_56} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[45]}]
set_clock_groups -name {Inferred_clkgroup_57} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[46]}]
set_clock_groups -name {Inferred_clkgroup_58} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[47]}]
set_clock_groups -name {Inferred_clkgroup_59} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[48]}]
set_clock_groups -name {Inferred_clkgroup_60} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[49]}]
set_clock_groups -name {Inferred_clkgroup_61} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[51]}]
set_clock_groups -name {Inferred_clkgroup_62} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[52]}]
set_clock_groups -name {Inferred_clkgroup_63} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|dqs_ca_clk_r_04_inferred_clock}]
set_clock_groups -name {Inferred_clkgroup_64} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[55]}]
set_clock_groups -name {Inferred_clkgroup_65} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|dqs_clkw_ca_04_inferred_clock}]
set_clock_groups -name {Inferred_clkgroup_66} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[56]}]
set_clock_groups -name {Inferred_clkgroup_67} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[57]}]
set_clock_groups -name {Inferred_clkgroup_68} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[58]}]
set_clock_groups -name {Inferred_clkgroup_69} -asynchronous -group [get_clocks {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[59]}]
set_clock_groups -name {Inferred_clkgroup_70} -asynchronous -group [get_clocks {ipsl_ddrphy_dll_update_ctrl|dll_update_n_inferred_clock}]
set_clock_groups -name {Inferred_clkgroup_71} -asynchronous -group [get_clocks {video_pll|clkout0_inferred_clock}]
set_clock_groups -name {Inferred_clkgroup_72} -asynchronous -group [get_clocks {video_pll|clkout1_inferred_clock}]

Logical Constraint:
+-----------------------------------------------------------------------------+
| Object                                     | Attribute     | Value         
+-----------------------------------------------------------------------------+
| u_ipsl_hmemc_top/u_pll_50_400/u_pll_e1     | PAP_LOC       | PLL_82_71     
+-----------------------------------------------------------------------------+

IO Constraint :
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| PORT                   | DIRECTION     | LOC     | VCCIO     | IOSTANDARD     | BUS_KEEPER     | SLEW     | DRIVE     | PMOS_FINGER     | NMOS_FINGER     | HYS_DRIVE_MODE     | VREF_MODE     | VREF_MODE_VALUE     | DDR_TERM_MODE     | DIFF_IN_TERM_MODE     | OPEN_DRAIN     | IN_DELAY     | OUT_DELAY     | DIFF_DRV_STRENGTH     | IO_REGISTER     | VIRTUAL_IO     
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| pad_dq_ch0[0]          | inout         | T8      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                
| pad_dq_ch0[1]          | inout         | T6      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                
| pad_dq_ch0[2]          | inout         | R6      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                
| pad_dq_ch0[3]          | inout         | R9      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                
| pad_dq_ch0[4]          | inout         | T9      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                
| pad_dq_ch0[5]          | inout         | N4      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                
| pad_dq_ch0[6]          | inout         | N5      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                
| pad_dq_ch0[7]          | inout         | P6      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                
| pad_dq_ch0[8]          | inout         | T4      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                
| pad_dq_ch0[9]          | inout         | V9      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                
| pad_dq_ch0[10]         | inout         | U9      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                
| pad_dq_ch0[11]         | inout         | V7      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                
| pad_dq_ch0[12]         | inout         | U7      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                
| pad_dq_ch0[13]         | inout         | V6      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                
| pad_dq_ch0[14]         | inout         | U6      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                
| pad_dq_ch0[15]         | inout         | V5      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                
| pad_dqs_ch0[0]         | inout         | N6      | 1.5       | SSTL15D_I      | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   | ON                    |                |              |               |                       |                 |                
| pad_dqs_ch0[1]         | inout         | U8      | 1.5       | SSTL15D_I      | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   | ON                    |                |              |               |                       |                 |                
| pad_dqsn_ch0[0]        | inout         | N7      | 1.5       | SSTL15D_I      | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   | ON                    |                |              |               |                       |                 |                
| pad_dqsn_ch0[1]        | inout         | V8      | 1.5       | SSTL15D_I      | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   | ON                    |                |              |               |                       |                 |                
| clk_led                | output        | A3      | 3.3       | LVCMOS33       | PULLUP         | FAST     | 4         |                 |                 | OFF                |               |                     |                   |                       |                |              |               |                       |                 |                
| ddr_init_done          | output        | B2      | 3.3       | LVCMOS33       | PULLUP         | FAST     | 4         |                 |                 | OFF                |               |                     |                   |                       |                |              |               |                       |                 |                
| ddrphy_rst_done        | output        | A2      | 3.3       | LVCMOS33       | PULLUP         | FAST     | 4         |                 |                 | OFF                |               |                     |                   |                       |                |              |               |                       |                 |                
| err_flag               | output        | B1      | 3.3       | LVCMOS33       | PULLUP         | FAST     | 4         |                 |                 | OFF                |               |                     |                   |                       |                |              |               |                       |                 |                
| led[0]                 | output        | U10     | 3.3       | LVCMOS33       | PULLUP         | FAST     | 4         |                 |                 | OFF                |               |                     |                   |                       |                |              |               |                       |                 |                
| led[1]                 | output        | V10     | 3.3       | LVCMOS33       | PULLUP         | FAST     | 4         |                 |                 | OFF                |               |                     |                   |                       |                |              |               |                       |                 |                
| led[2]                 | output        | U11     | 3.3       | LVCMOS33       | PULLUP         | FAST     | 4         |                 |                 | OFF                |               |                     |                   |                       |                |              |               |                       |                 |                
| led[3]                 | output        | V11     | 3.3       | LVCMOS33       | PULLUP         | FAST     | 4         |                 |                 | OFF                |               |                     |                   |                       |                |              |               |                       |                 |                
| pad_addr_ch0[0]        | output        | M4      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                
| pad_addr_ch0[1]        | output        | M3      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                
| pad_addr_ch0[2]        | output        | P2      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                
| pad_addr_ch0[3]        | output        | P1      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                
| pad_addr_ch0[4]        | output        | L5      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                
| pad_addr_ch0[5]        | output        | M5      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                
| pad_addr_ch0[6]        | output        | N2      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                
| pad_addr_ch0[7]        | output        | N1      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                
| pad_addr_ch0[8]        | output        | K4      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                
| pad_addr_ch0[9]        | output        | M1      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                
| pad_addr_ch0[10]       | output        | M6      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                
| pad_addr_ch0[11]       | output        | L1      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                
| pad_addr_ch0[12]       | output        | K2      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                
| pad_addr_ch0[13]       | output        | K1      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                
| pad_addr_ch0[14]       | output        | J2      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                
| pad_addr_ch0[15]       | output        | J1      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                
| pad_ba_ch0[0]          | output        | U2      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                
| pad_ba_ch0[1]          | output        | U1      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                
| pad_ba_ch0[2]          | output        | T2      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                
| pad_casn_ch0           | output        | T1      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                
| pad_cke_ch0            | output        | L4      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                
| pad_csn_ch0            | output        | R1      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                
| pad_ddr_clk_w          | output        | U3      | 1.5       | SSTL15D_I      | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                
| pad_ddr_clkn_w         | output        | V3      | 1.5       | SSTL15D_I      | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                
| pad_dm_rdqs_ch0[0]     | output        | R8      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                
| pad_dm_rdqs_ch0[1]     | output        | U5      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                
| pad_loop_out           | output        | P8      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                
| pad_loop_out_h         | output        | U4      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                
| pad_odt_ch0            | output        | V2      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                
| pad_rasn_ch0           | output        | R2      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                
| pad_rstn_ch0           | output        | M2      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                
| pad_wen_ch0            | output        | V1      | 1.5       | SSTL15_I       | UNUSED         | FAST     | 7.5       |                 |                 |                    |               |                     |                   |                       |                |              |               |                       |                 |                
| pll_lock               | output        | B4      | 3.3       | LVCMOS33       | PULLUP         | FAST     | 4         |                 |                 | OFF                |               |                     |                   |                       |                |              |               |                       |                 |                
| sd_dclk                | output        | V13     | 3.3       | LVCMOS33       | PULLUP         | FAST     | 4         |                 |                 | OFF                |               |                     |                   |                       |                |              |               |                       |                 |                
| sd_mosi                | output        | U14     | 3.3       | LVCMOS33       | PULLUP         | FAST     | 4         |                 |                 | OFF                |               |                     |                   |                       |                |              |               |                       |                 |                
| sd_ncs                 | output        | V14     | 3.3       | LVCMOS33       | PULLUP         | FAST     | 4         |                 |                 | OFF                |               |                     |                   |                       |                |              |               |                       |                 |                
| tmds_clk_n             | output        | A16     | 3.3       | LVTTL33        | NONE           | FAST     | 12        |                 |                 | OFF                |               |                     |                   |                       |                |              |               |                       |                 |                
| tmds_clk_p             | output        | B16     | 3.3       | LVTTL33        | NONE           | FAST     | 12        |                 |                 | OFF                |               |                     |                   |                       |                |              |               |                       |                 |                
| tmds_data_n[0]         | output        | A14     | 3.3       | LVTTL33        | NONE           | FAST     | 12        |                 |                 | OFF                |               |                     |                   |                       |                |              |               |                       |                 |                
| tmds_data_n[1]         | output        | A11     | 3.3       | LVTTL33        | NONE           | FAST     | 12        |                 |                 | OFF                |               |                     |                   |                       |                |              |               |                       |                 |                
| tmds_data_n[2]         | output        | A10     | 3.3       | LVTTL33        | NONE           | FAST     | 12        |                 |                 | OFF                |               |                     |                   |                       |                |              |               |                       |                 |                
| tmds_data_p[0]         | output        | B14     | 3.3       | LVTTL33        | NONE           | FAST     | 12        |                 |                 | OFF                |               |                     |                   |                       |                |              |               |                       |                 |                
| tmds_data_p[1]         | output        | B11     | 3.3       | LVTTL33        | NONE           | FAST     | 12        |                 |                 | OFF                |               |                     |                   |                       |                |              |               |                       |                 |                
| tmds_data_p[2]         | output        | B10     | 3.3       | LVTTL33        | NONE           | FAST     | 12        |                 |                 | OFF                |               |                     |                   |                       |                |              |               |                       |                 |                
| key                    | input         | V12     | 3.3       | LVCMOS33       | PULLUP         |          |           |                 |                 |                    | NOHYS         |                     |                   |                       |                |              |               |                       |                 |                
| pad_loop_in            | input         | P7      | 1.5       | SSTL15_I       | UNUSED         |          |           |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                
| pad_loop_in_h          | input         | V4      | 1.5       | SSTL15_I       | UNUSED         |          |           |                 |                 |                    |               | IN                  | 0.5               | ON                    |                |              |               |                       |                 |                
| rst_n                  | input         | U12     | 3.3       | LVCMOS33       | PULLUP         |          |           |                 |                 |                    | NOHYS         |                     |                   |                       |                |              |               |                       |                 |                
| sd_miso                | input         | U13     | 3.3       | LVCMOS33       | PULLUP         |          |           |                 |                 |                    | NOHYS         |                     |                   |                       |                |              |               |                       |                 |                
| sys_clk                | input         | B5      | 3.3       | LVCMOS33       | PULLUP         |          |           |                 |                 |                    | NOHYS         |                     |                   |                       |                |              |               |                       |                 |                
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


Clock Signal:
+------------------------------------------------------------------------------------------------------------------------------+
| Port_Name     | Clk_Source_Inst     | Clk_Inst_Name             | Net_Name         | Fanout     | Constraint_To_Clk_Pad     
+------------------------------------------------------------------------------------------------------------------------------+
| sys_clk       | sys_clk_ibuf        | video_pll_m0/u_pll_e1     | sys_clk_c[0]     | 438        | No Need                   
+------------------------------------------------------------------------------------------------------------------------------+


Reset Signal:
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Net_Name                                                                      | Rst_Source_Inst                                                                   | Fanout     
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| rst_n_c_i_0                                                                   | rst_n_c_i                                                                         | 772        
| _$$_GND_$$_                                                                   | _$$_GND_$$_                                                                       | 3830       
| dvi_encoder_m0/serdes_4b_10to1_m0/TMDS_mod5 [2]                               | dvi_encoder_m0/serdes_4b_10to1_m0/TMDS_mod5[2]                                    | 41         
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/srb_rst_dll                             | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_ddrphy_reset_ctrl/srb_rst_dll        | 2          
| u_ipsl_hmemc_top/u_ipsl_hmemc_ddrc_top/u_ipsl_ddrc_reset_ctrl/resetn_i_0      | u_ipsl_hmemc_top/u_ipsl_hmemc_ddrc_top/u_ipsl_ddrc_reset_ctrl/resetn_i            | 15         
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/global_reset_i_0                        | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_ddrphy_reset_ctrl/global_reset_i     | 64         
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_rst_dll            | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut                    | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_dqs_rst [0]        | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut                    | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_dqs_rst [1]        | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut                    | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_dqs_rst [2]        | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut                    | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_dqs_rst [3]        | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut                    | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_dqs_rst [4]        | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ddrphy_dut                    | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/srb_dqs_rstn                            | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_ddrphy_reset_ctrl/srb_dqs_rstn       | 3          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [3]        | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[3].inv_dut        | 2          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [4]        | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[4].inv_dut        | 2          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [5]        | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[5].inv_dut        | 2          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [6]        | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[6].inv_dut        | 2          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [7]        | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[7].inv_dut        | 2          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [10]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[10].inv_dut       | 2          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [11]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[11].inv_dut       | 2          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [12]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[12].inv_dut       | 2          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [27]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[27].inv_dut       | 2          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [28]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[28].inv_dut       | 2          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [29]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[29].inv_dut       | 2          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [32]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[32].inv_dut       | 2          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [33]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[33].inv_dut       | 2          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [34]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[34].inv_dut       | 2          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [35]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[35].inv_dut       | 2          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [36]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[36].inv_dut       | 2          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [2]        | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[2].inv_dut        | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [9]        | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[9].inv_dut        | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [17]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[17].inv_dut       | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [18]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[18].inv_dut       | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [19]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[19].inv_dut       | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [20]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[20].inv_dut       | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [21]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[21].inv_dut       | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [22]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[22].inv_dut       | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [23]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[23].inv_dut       | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [24]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[24].inv_dut       | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [25]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[25].inv_dut       | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [31]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[31].inv_dut       | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [37]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[37].inv_dut       | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [40]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[40].inv_dut       | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [41]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[41].inv_dut       | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [42]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[42].inv_dut       | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [43]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[43].inv_dut       | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [44]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[44].inv_dut       | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [45]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[45].inv_dut       | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [46]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[46].inv_dut       | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [47]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[47].inv_dut       | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [48]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[48].inv_dut       | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [49]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[49].inv_dut       | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [51]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[51].inv_dut       | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [52]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[52].inv_dut       | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [55]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[55].inv_dut       | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [56]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[56].inv_dut       | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [57]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[57].inv_dut       | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [58]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[58].inv_dut       | 1          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/buffer_iol_lrs [59]       | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/gtp_int_dut[59].inv_dut       | 1          
| frame_read_write_m0/read_fifo_aclr                                            | frame_read_write_m0/frame_fifo_read_m0/fifo_aclr                                  | 81         
| frame_read_write_m0/write_fifo_aclr                                           | frame_read_write_m0/frame_fifo_write_m0/fifo_aclr                                 | 81         
| u_ipsl_hmemc_top/u_ipsl_hmemc_ddrc_top/u_ipsl_ddrc_reset_ctrl/presetn_i_0     | u_ipsl_hmemc_top/u_ipsl_hmemc_ddrc_top/u_ipsl_ddrc_reset_ctrl/presetn_i           | 10         
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


Other High Fanout Signal:
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Net_Name                                                                                        | Driver                                                                                             | Fanout     
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| ui_clk[0]                                                                                       | u_ipsl_hmemc_top/u_pll_50_400/u_pll_e1                                                             | 349        
| video_clk[0]                                                                                    | video_pll_m0/u_pll_e1                                                                              | 229        
| u_ipsl_hmemc_top/pll_pclk                                                                       | u_ipsl_hmemc_top/u_pll_50_400/u_pll_e1                                                             | 112        
| u_ipsl_hmemc_top/u_ipsl_hmemc_ddrc_top/u_ipsl_ddrc_reset_ctrl/u_ipsl_ddrc_apb_reset/cnt [0]     | u_ipsl_hmemc_top/u_ipsl_hmemc_ddrc_top/u_ipsl_ddrc_reset_ctrl/u_ipsl_ddrc_apb_reset/cnt[0]         | 82         
| u_ipsl_hmemc_top/u_ipsl_hmemc_ddrc_top/u_ipsl_ddrc_reset_ctrl/u_ipsl_ddrc_apb_reset/cnt [1]     | u_ipsl_hmemc_top/u_ipsl_hmemc_ddrc_top/u_ipsl_ddrc_reset_ctrl/u_ipsl_ddrc_apb_reset/cnt[1]         | 81         
| u_ipsl_hmemc_top/u_ipsl_hmemc_ddrc_top/u_ipsl_ddrc_reset_ctrl/u_ipsl_ddrc_apb_reset/cnt [4]     | u_ipsl_hmemc_top/u_ipsl_hmemc_ddrc_top/u_ipsl_ddrc_reset_ctrl/u_ipsl_ddrc_apb_reset/cnt[4]         | 78         
| u_ipsl_hmemc_top/u_ipsl_hmemc_ddrc_top/u_ipsl_ddrc_reset_ctrl/u_ipsl_ddrc_apb_reset/cnt [2]     | u_ipsl_hmemc_top/u_ipsl_hmemc_ddrc_top/u_ipsl_ddrc_reset_ctrl/u_ipsl_ddrc_apb_reset/cnt[2]         | 76         
| u_ipsl_hmemc_top/u_ipsl_hmemc_ddrc_top/u_ipsl_ddrc_reset_ctrl/u_ipsl_ddrc_apb_reset/cnt [3]     | u_ipsl_hmemc_top/u_ipsl_hmemc_ddrc_top/u_ipsl_ddrc_reset_ctrl/u_ipsl_ddrc_apb_reset/cnt[3]         | 75         
| u_ipsl_hmemc_top/u_ipsl_hmemc_ddrc_top/u_ipsl_ddrc_reset_ctrl/u_ipsl_ddrc_apb_reset/cnt [5]     | u_ipsl_hmemc_top/u_ipsl_hmemc_ddrc_top/u_ipsl_ddrc_reset_ctrl/u_ipsl_ddrc_apb_reset/cnt[5]         | 74         
| dvi_encoder_m0/de_reg                                                                           | dvi_encoder_m0/encb/de_reg                                                                         | 69         
| video_clk5x                                                                                     | video_pll_m0/u_pll_e1                                                                              | 57         
| u_ipsl_hmemc_top/u_ipsl_hmemc_ddrc_top/u_ipsl_ddrc_reset_ctrl/ddrc_init_start_Z                 | u_ipsl_hmemc_top/u_ipsl_hmemc_ddrc_top/u_ipsl_ddrc_reset_ctrl/ddrc_init_start                      | 56         
| u_aq_axi_master/wr_state [0]                                                                    | u_aq_axi_master/wr_state[0]                                                                        | 56         
| sd_card_bmp_m0/bmp_read_m0/rd_cnt [0]                                                           | sd_card_bmp_m0/bmp_read_m0/rd_cnt[0]                                                               | 53         
| u_ipsl_hmemc_top/u_ipsl_hmemc_ddrc_top/u_ipsl_ddrc_reset_ctrl/un2_pwrite                        | u_ipsl_hmemc_top/u_ipsl_hmemc_ddrc_top/u_ipsl_ddrc_reset_ctrl/u_ipsl_ddrc_apb_reset/un2_pwrite     | 48         
| frame_read_write_m0/frame_fifo_read_m0/state [1]                                                | frame_read_write_m0/frame_fifo_read_m0/state[1]                                                    | 46         
| frame_read_write_m0/frame_fifo_write_m0/state [1]                                               | frame_read_write_m0/frame_fifo_write_m0/state[1]                                                   | 45         
| sd_card_bmp_m0/bmp_read_m0/N_342_0                                                              | sd_card_bmp_m0/bmp_read_m0/rd_cnt_0_sqmuxa_i_o2                                                    | 45         
| u_ipsl_hmemc_top/u_ipsl_hmemc_ddrc_top/u_ipsl_ddrc_reset_ctrl/u_ipsl_ddrc_apb_reset/cnt [6]     | u_ipsl_hmemc_top/u_ipsl_hmemc_ddrc_top/u_ipsl_ddrc_reset_ctrl/u_ipsl_ddrc_apb_reset/cnt[6]         | 45         
| u_ipsl_hmemc_top/u_ipsl_hmemc_ddrc_top/u_ipsl_ddrc_reset_ctrl/init_psel                         | u_ipsl_hmemc_top/u_ipsl_hmemc_ddrc_top/u_ipsl_ddrc_reset_ctrl/u_ipsl_ddrc_apb_reset/psel           | 43         
| sd_card_bmp_m0/sd_card_top_m0/sd_card_sec_read_write_m0/N_165_i_0                               | sd_card_bmp_m0/sd_card_top_m0/sd_card_sec_read_write_m0/N_165_i                                    | 43         
| u_ipsl_hmemc_top/u_ipsl_hmemc_ddrc_top/u_ipsl_ddrc_reset_ctrl/presetn_Z                         | u_ipsl_hmemc_top/u_ipsl_hmemc_ddrc_top/u_ipsl_ddrc_reset_ctrl/presetn                              | 42         
| wr_burst_data_req                                                                               | u_aq_axi_master/rd_fifo_cntlde_0_o2                                                                | 37         
| sd_card_bmp_m0/bmp_read_m0/state [4]                                                            | sd_card_bmp_m0/bmp_read_m0/state[4]                                                                | 37         
| sd_card_bmp_m0/sd_card_top_m0/sd_card_sec_read_write_m0/state_Z [5]                             | sd_card_bmp_m0/sd_card_top_m0/sd_card_sec_read_write_m0/state[5]                                   | 36         
| rd_burst_len[6]                                                                                 | frame_read_write_m0/frame_fifo_read_m0/rd_burst_len_1[6]                                           | 36         
| u_aq_axi_master/rd_state [0]                                                                    | u_aq_axi_master/rd_state[0]                                                                        | 33         
| sd_card_bmp_m0/bmp_read_m0/N_300                                                                | sd_card_bmp_m0/bmp_read_m0/width_4_i_i_o3_2[0]                                                     | 32         
| u_aq_axi_master/rd_fifo_cnte                                                                    | u_aq_axi_master/rd_fifo_cntlde_0                                                                   | 32         
| sd_card_bmp_m0/ax_debounce_m0/q_reset_Z                                                         | sd_card_bmp_m0/ax_debounce_m0/q_reset                                                              | 32         
| sd_card_bmp_m0/ax_debounce_m0/q_rege                                                            | sd_card_bmp_m0/ax_debounce_m0/q_reglde                                                             | 32         
| sd_card_bmp_m0/bmp_read_m0/bmp_len_cnte                                                         | sd_card_bmp_m0/bmp_read_m0/bmp_len_cntlde                                                          | 32         
| sd_card_bmp_m0/sd_card_top_m0/sd_card_sec_read_write_m0/state_ns_a3_0 [5]                       | sd_card_bmp_m0/sd_card_top_m0/sd_card_sec_read_write_m0/state_ns_a3_0[5]                           | 32         
| sd_card_bmp_m0/bmp_read_m0/N_344_i_0                                                            | sd_card_bmp_m0/bmp_read_m0/N_344_i                                                                 | 29         
| frame_read_write_m0/frame_fifo_write_m0/write_req_d2_Z                                          | frame_read_write_m0/frame_fifo_write_m0/write_req_d2                                               | 29         
| wr_burst_req                                                                                    | frame_read_write_m0/frame_fifo_write_m0/wr_burst_req                                               | 29         
| sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/state [2]                                          | sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/state[2]                                              | 28         
| frame_read_write_m0/frame_fifo_read_m0/read_req_d2_Z                                            | frame_read_write_m0/frame_fifo_read_m0/read_req_d2                                                 | 28         
| sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/state [3]                                          | sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/state[3]                                              | 27         
| sd_card_bmp_m0/sd_card_top_m0/spi_master_m0/state [0]                                           | sd_card_bmp_m0/sd_card_top_m0/spi_master_m0/state[0]                                               | 26         
| sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/state [1]                                          | sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/state[1]                                              | 26         
| sd_card_bmp_m0/sd_card_top_m0/spi_wr_ack                                                        | sd_card_bmp_m0/sd_card_top_m0/spi_master_m0/state[3]                                               | 25         
| video_timing_data_m0/video_de_d0_Z                                                              | video_timing_data_m0/video_de_d0                                                                   | 25         
| u_aq_axi_master/rd_state_0_sqmuxa                                                               | u_aq_axi_master/rd_state_0_sqmuxa_0_a3                                                             | 24         
| wr_burst_len[6]                                                                                 | frame_read_write_m0/frame_fifo_write_m0/wr_burst_len_1[6]                                          | 23         
| sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/state [0]                                          | sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/state[0]                                              | 23         
| sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/state [4]                                          | sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/state[4]                                              | 22         
| u_aq_axi_master/un1_M_AXI_AWLOCK_15_0_Z                                                         | u_aq_axi_master/un1_M_AXI_AWLOCK_15_0                                                              | 21         
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ioclk_01                                    | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/ioclkbuf01_dut                                 | 21         
| sd_card_bmp_m0/bmp_read_m0/rd_cnt [2]                                                           | sd_card_bmp_m0/bmp_read_m0/rd_cnt[2]                                                               | 21         
| u_aq_axi_master/un1_MASTER_RST_2_0_0_Z                                                          | u_aq_axi_master/un1_MASTER_RST_2_0_0                                                               | 21         
| frame_read_write_m0/frame_fifo_read_m0/read_cnte                                                | frame_read_write_m0/frame_fifo_read_m0/read_cntlde                                                 | 19         
| sd_card_bmp_m0/sd_card_top_m0/spi_master_m0/state [2]                                           | sd_card_bmp_m0/sd_card_top_m0/spi_master_m0/state[2]                                               | 19         
| frame_read_write_m0/frame_fifo_write_m0/write_cnte                                              | frame_read_write_m0/frame_fifo_write_m0/write_cntlde_0                                             | 19         
| sd_card_bmp_m0/sd_card_top_m0/spi_master_m0/state [4]                                           | sd_card_bmp_m0/sd_card_top_m0/spi_master_m0/state[4]                                               | 19         
| sd_card_bmp_m0/bmp_read_m0/N_301                                                                | sd_card_bmp_m0/bmp_read_m0/header_1_0_sqmuxa_0_o3                                                  | 18         
| sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/byte_cnte                                          | sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/byte_cntlde                                           | 16         
| sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/N_193_i_0                                          | sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/N_193_i                                               | 16         
| sd_card_bmp_m0/bmp_read_m0/N_299                                                                | sd_card_bmp_m0/bmp_read_m0/file_len_7_i_o3_0[8]                                                    | 16         
| sd_card_bmp_m0/bmp_read_m0/N_304                                                                | sd_card_bmp_m0/bmp_read_m0/width_4_i_i_o3_1[0]                                                     | 16         
| sd_card_bmp_m0/bmp_read_m0/width_0_sqmuxa_Z                                                     | sd_card_bmp_m0/bmp_read_m0/width_0_sqmuxa                                                          | 16         
| sd_card_bmp_m0/sd_init_done                                                                     | sd_card_bmp_m0/sd_card_top_m0/sd_card_sec_read_write_m0/sd_init_done                               | 15         
| video_timing_data_m0/color_bar_m0/hs_reg5                                                       | video_timing_data_m0/color_bar_m0/hs_reg5_0_a2                                                     | 14         
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/dqs_clkw_ca_03                              | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/dqs3_dut                                       | 12         
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/dqs_ca_clk_r_03                             | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/dqs3_dut                                       | 12         
| sd_card_bmp_m0/sd_sec_read_data [5]                                                             | sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/block_read_data[5]                                    | 11         
| sd_card_bmp_m0/sd_sec_read_data [4]                                                             | sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/block_read_data[4]                                    | 11         
| sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/block_read_data5_Z                                 | sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/block_read_data5                                      | 11         
| sd_card_bmp_m0/sd_sec_read_data [3]                                                             | sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/block_read_data[3]                                    | 11         
| sd_card_bmp_m0/sd_sec_read_data [6]                                                             | sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/block_read_data[6]                                    | 11         
| sd_card_bmp_m0/sd_sec_read_data [2]                                                             | sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/block_read_data[2]                                    | 11         
| sd_card_bmp_m0/sd_card_top_m0/sd_card_sec_read_write_m0/state_Z [2]                             | sd_card_bmp_m0/sd_card_top_m0/sd_card_sec_read_write_m0/state[2]                                   | 11         
| sd_card_bmp_m0/sd_sec_read_data [1]                                                             | sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/block_read_data[1]                                    | 11         
| s00_axi_wvalid                                                                                  | u_aq_axi_master/reg_wvalid                                                                         | 11         
| sd_card_bmp_m0/sd_sec_read_data [7]                                                             | sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/block_read_data[7]                                    | 11         
| sd_card_bmp_m0/sd_card_top_m0/sd_card_sec_read_write_m0/state_ns_o2 [1]                         | sd_card_bmp_m0/sd_card_top_m0/sd_card_sec_read_write_m0/state_ns_o2[1]                             | 11         
| sd_card_bmp_m0/sd_sec_read_data [0]                                                             | sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/block_read_data[0]                                    | 11         
| dvi_encoder_m0/encb/dout_14 [9]                                                                 | dvi_encoder_m0/encb/dout_14[9]                                                                     | 11         
| sd_card_bmp_m0/state [3]                                                                        | sd_card_bmp_m0/bmp_read_m0/state[3]                                                                | 11         
| dvi_encoder_m0/encr/dout_14 [9]                                                                 | dvi_encoder_m0/encr/dout_14[9]                                                                     | 11         
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/dqs1_clk_r                                  | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/dqs2_dut                                       | 10         
| sd_card_bmp_m0/bmp_read_m0/rd_cnte                                                              | sd_card_bmp_m0/bmp_read_m0/rd_cntlde                                                               | 10         
| dvi_encoder_m0/encb/c0_reg_Z                                                                    | dvi_encoder_m0/encb/c0_reg                                                                         | 10         
| sd_card_bmp_m0/state [1]                                                                        | sd_card_bmp_m0/bmp_read_m0/state[1]                                                                | 10         
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/dqs0_clk_r                                  | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/dqs0_dut                                       | 10         
| dvi_encoder_m0/encb/cnt_3_sqmuxa_Z                                                              | dvi_encoder_m0/encb/cnt_3_sqmuxa                                                                   | 10         
| sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/un1_state_5_Z                                      | sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/un1_state_5                                           | 10         
| sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/state_i_0 [4]                                      | sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/state_i[4]                                            | 10         
| u_aq_axi_master/wr_state [2]                                                                    | u_aq_axi_master/wr_state[2]                                                                        | 10         
| sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/state_i_0 [3]                                      | sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/state_i_0[3]                                          | 10         
| sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/byte_cnt [1]                                       | sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/byte_cnt[1]                                           | 10         
| u_aq_axi_master/N_272_0                                                                         | u_aq_axi_master/un1_rd_state_i_o3                                                                  | 10         
| sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/byte_cnt [0]                                       | sd_card_bmp_m0/sd_card_top_m0/sd_card_cmd_m0/byte_cnt[0]                                           | 10         
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/dqs_clkw290_0                               | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/dqs0_dut                                       | 9          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/dqs_ca_clk_r_01                             | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/dqs1_dut                                       | 9          
| dvi_encoder_m0/encr/cnt_3_sqmuxa_Z                                                              | dvi_encoder_m0/encr/cnt_3_sqmuxa                                                                   | 9          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/dll_update_n [0]                                          | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ddrphy_dll_update_ctrl/dll_update_n                        | 9          
| u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/dqs_clkw290_1                               | u_ipsl_hmemc_top/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/dqs2_dut                                       | 9          
| dvi_encoder_m0/encg/dout_14 [9]                                                                 | dvi_encoder_m0/encg/dout_14[9]                                                                     | 9          
| dvi_encoder_m0/encg/cnt_3_sqmuxa_Z                                                              | dvi_encoder_m0/encg/cnt_3_sqmuxa                                                                   | 9          
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


Device mapping started.
Optimizing circuit logic.
Checking design netlist.
Processing tech operator.
Converting tech operator to gate operator.
Processing gate operator.
Device mapping done.
Total device mapping takes 0.592804 sec.

Device Utilization Summary:
+-------------------------------------------------------------------------+
| Logic Utilization     | Used     | Available     | Utilization(%)     
+-------------------------------------------------------------------------+
| APM                   | 0        | 30            | 0                   
| IOCKDLY               | 0        | 24            | 0                   
| FF                    | 1164     | 26304         | 5                   
| LUT                   | 2111     | 17536         | 13                  
| Distributed RAM       | 0        | 1110          | 0                   
| DLL                   | 2        | 6             | 34                  
| DQSL                  | 5        | 18            | 28                  
| DRM                   | 4        | 48            | 9                   
| FUSECODE              | 0        | 1             | 0                   
| IO                    | 78       | 240           | 33                  
| IOCKDIV               | 1        | 12            | 9                   
| IOCKGATE              | 2        | 12            | 17                  
| IPAL                  | 0        | 1             | 0                   
| PLL                   | 2        | 6             | 34                  
| RCKB                  | 0        | 24            | 0                   
| SCANCHAIN             | 0        | 4             | 0                   
| START                 | 0        | 1             | 0                   
| USCM                  | 5        | 20            | 25                  
| HMEMC                 | 1        | 2             | 50                  
| ADC                   | 0        | 1             | 0                   
| CRYSTAL               | 0        | 6             | 0                   
| FLSIF                 | 0        | 1             | 0                   
| RESCAL                | 0        | 6             | 0                   
| UDID                  | 0        | 1             | 0                   
+-------------------------------------------------------------------------+

Virtual IO Port Info:
NULL

Inputs and Outputs :
+----------------------------------------------------------------------------------------------------------------------------------+
| Type       | File Name                                                                                                          
+----------------------------------------------------------------------------------------------------------------------------------+
| Input      | D:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/synthesize/ipsl_hmemc_top_test.vm          
|            | D:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/synthesize/synplify.scf                    
|            | D:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/synthesize/synplify.lcf                    
| Output     | D:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/device_map/ipsl_hmemc_top_test_map.adf     
|            | D:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/device_map/ipsl_hmemc_top_test.dmr         
|            | D:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/device_map/ipsl_hmemc_top_test_dmr.prt     
+----------------------------------------------------------------------------------------------------------------------------------+


Flow Command: dev_map 
Peak memory: 192,176,128 bytes
Total CPU  time to dev_map completion : 4.586 sec
Total real time to dev_map completion : 7.000 sec
