module Top_FPGA (
    input            pixelclk,
//    input            sys_clk ,
    input            rstin   ,
    input    [23:0]  i_rgb   ,
    input            i_hsync ,
    input            i_vsync ,
    input            i_de    ,

    input            red_en  ,
    input            grenn_en,
    input            blue_en ,
    input            uart_rx ,
    output           uart_tx   
);

    wire   [23:0]  VGA_rgb      ;
    wire           VGA_hsync    ;
    wire           VGA_vsync    ;
    wire           VGA_de       ;
    
    wire           frame_vaild  ;
    wire   [2:0]   frame_cnt    ;
    wire   [3:0]   fruit_num    ;
    wire           apple_type_en;
    wire           pear_type_en ;
    wire           banan_type_en;
    wire           mango_type_en;
    wire           orang_type_en;
    wire           grape_type_en;
    wire           pitay_type_en;
    wire           kiwi_type_en ;
    wire           enable_r     ; //color instruct signal output to uart 
    wire           enable_g     ;
    wire           enable_y     ;
    wire           enable_p     ;
    wire           enable_n     ;
    wire           enable_py    ; //pure yellow
    wire           enable_o     ; //orange
    wire           enable_pk    ;//pink  

    wire           k_frame_vaild  ;
    wire   [2:0]   k_frame_cnt    ;
    wire   [4:0]   k_fruit_num    ; 
    wire           k_apple_type_en;
    wire           k_pear_type_en ;
    wire           k_banan_type_en;
    wire           k_mango_type_en;
    wire           k_orang_type_en;
    wire           k_grape_type_en;
    wire           k_pitay_type_en;
    wire           k_kiwi_type_en ;
    wire           k_enable_r     ; //color instruct signal output to uart 
    wire           k_enable_g     ;
    wire           k_enable_y     ;
    wire           k_enable_p     ;
    wire           k_enable_n     ;
    wire           k_enable_py    ; //pure yellow
    wire           k_enable_o     ; //orange
    wire           k_enable_pk    ;//pink

ISP #(
    .P_LOG_ENABLE  (32'd1)
)I1(
    .pixelclk      (pixelclk     ),
    .rstin         (rstin        ),
    .i_rgb         (i_rgb        ),
    .i_hsync       (i_hsync      ),
    .i_vsync       (i_vsync      ),
    .i_de          (i_de         ),
     
    .red_en        (red_en       ),
    .grenn_en      (grenn_en     ),
    .blue_en       (blue_en      ),
    .key_in        (3'b111       ),
    .VGA_rgb       (VGA_rgb      ),
    .VGA_hsync     (VGA_hsync    ),
    .VGA_vsync     (VGA_vsync    ),
    .VGA_de        (VGA_de       ),
    .frame_cnt     (frame_cnt    ),
    .fruit_num     (fruit_num    ),
    .frame_vaild   (frame_vaild  ),
    .apple_type_en (apple_type_en),
    .pear_type_en  (pear_type_en ),
    .banan_type_en (banan_type_en),
    .mango_type_en (mango_type_en),
    .orang_type_en (orang_type_en),
    .grape_type_en (grape_type_en),
    .pitay_type_en (pitay_type_en),
    .kiwi_type_en  (kiwi_type_en ),
    .enable_r      (enable_r     ), //color instruct signal output to uart 
    .enable_g      (enable_g     ),
    .enable_y      (enable_y     ),
    .enable_p      (enable_p     ),
    .enable_n      (enable_n     ),
    .enable_py     (enable_py    ), //pure yellow
    .enable_o      (enable_o     ), //orange
    .enable_pk     (enable_pk    ) //pink  
   );

uart_ctrl u1(
    .sys_clk       (pixelclk     ),
    .rst_n         (rstin        ),
    .frame_vaild   (frame_vaild  ),
    .s_frame_cnt   (frame_cnt    ),
//color enable signal  
    .red_en        (enable_r     ),
    .green_en      (enable_g     ),
    .yellow_en     (enable_y     ),
    .purple_en     (enable_p     ),
    .brown_en      (enable_n     ),
    .pyellow_en    (enable_py    ),
    .orange_en     (enable_o     ),
    .pink_en       (enable_pk    ),
//fruit type enable signal
    .apple_type_en (apple_type_en),
    .pear_type_en  (pear_type_en ),
    .banan_type_en (banan_type_en),
    .mango_type_en (mango_type_en),
    .orang_type_en (orang_type_en),
    .grape_type_en (grape_type_en),
    .pitay_type_en (pitay_type_en),
    .kiwi_type_en  (kiwi_type_en ),    
    .fruit_num     (fruit_num    ),
    .uart_rx       (uart_rx      ),
    .uart_tx       (uart_tx      )
);

//PULSE_GEN P1(
//    .RST        (~rstin    ),//(i)
//    .CLK_I      (pixelclk  ),//(i)
//    .CLK_O      (sys_clk   ),//(i)
//    .PULSE_I    (enable_r  ),//(i)
//    .PULSE_O    (k_enable_r) //(o)
//);
//PULSE_GEN P2(
//    .RST        (~rstin    ),//(i)
//    .CLK_I      (pixelclk  ),//(i)
//    .CLK_O      (sys_clk   ),//(i)
//    .PULSE_I    (enable_g  ),//(i)
//    .PULSE_O    (k_enable_g) //(o)
//);
//PULSE_GEN P3(
//    .RST        (~rstin    ),//(i)
//    .CLK_I      (pixelclk  ),//(i)
//    .CLK_O      (sys_clk   ),//(i)
//    .PULSE_I    (enable_y  ),//(i)
//    .PULSE_O    (k_enable_y) //(o)
//);
//PULSE_GEN P4(
//    .RST        (~rstin    ),//(i)
//    .CLK_I      (pixelclk  ),//(i)
//    .CLK_O      (sys_clk   ),//(i)
//    .PULSE_I    (enable_p  ),//(i)
//    .PULSE_O    (k_enable_p) //(o)
//);
//PULSE_GEN P5(
//    .RST        (~rstin    ),//(i)
//    .CLK_I      (pixelclk  ),//(i)
//    .CLK_O      (sys_clk   ),//(i)
//    .PULSE_I    (enable_p  ),//(i)
//    .PULSE_O    (k_enable_p) //(o)
//);
endmodule