Start generating at 2019-05-06 10:21
Instance: ddr3 (D:\example_ziguang\sd_picture_hdmi\ipcore\ddr3)
Model: Logos HMEMC, Version 1.0
Family: Logos
Device: PGL22G
Package: BG324
Speed Grade: -7
Create directory 'example_design' ...
Create directory 'pnr' ...
Create directory 'pnr\ctrl_phy_22' ...
Create directory 'rtl' ...
Create directory 'sim' ...
Copy 'example_design\bench' to 'example_design' ...
Copy 'example_design\rtl' to 'example_design' ...
Copy 'pnr\ctrl_phy_22\ip_filelist.f' to 'pnr\ctrl_phy_22' ...
Copy 'pnr\ctrl_phy_22\prj_filelist.f' to 'pnr\ctrl_phy_22' ...
Copy 'rtl\ipsl_ddrc_apb_reset.v' to 'rtl' ...
Copy 'rtl\ipsl_ddrc_reset_ctrl.v' to 'rtl' ...
Copy 'rtl\ipsl_ddrphy_dll_update_ctrl.v' to 'rtl' ...
Copy 'rtl\ipsl_ddrphy_reset_ctrl.v' to 'rtl' ...
Copy 'rtl\ipsl_ddrphy_training_ctrl.v' to 'rtl' ...
Copy 'rtl\ipsl_ddrphy_update_ctrl.v' to 'rtl' ...
Copy 'rtl\ipsl_hmemc_ddrc_top.v' to 'rtl' ...
Copy 'rtl\ipsl_hmemc_phy_top.v' to 'rtl' ...
Copy 'rtl\ipsl_phy_io.v' to 'rtl' ...
Copy 'rtl\pll' to 'rtl' ...
Copy 'ipsl_hmemc_top_v1_0_wrapper.v.xml' ...
Compile file 'ipsl_hmemc_top_v1_0_wrapper.v.xml' to 'ddr3.v' ...
Found module 'ddr3' in file 'ddr3.v'.
Compile file 'rtl\pll\pll_50_400.v.xml' to 'rtl\pll\pll_50_400.v' ...
Compile file 'example_design\rtl\ipsl_hmemc_top_test.v.xml' to 'example_design\rtl\ipsl_hmemc_top_test.v' ...
Compile file 'example_design\bench\ddr_test_top_tb.v.xml' to 'example_design\bench\ddr_test_top_tb.v' ...
Run file 'createFiles.tcl' ...
Generate template file 'ddr3_tmpl.v' ...
Done: 0 error(s), 0 warning(s)
