
`timescale 1ns/1ps
module  threshold_binary#(
        parameter P_LOG_ENABLE   = 0 ,
        parameter DW        = 24 ,
        parameter Y_TH      = 36 ,
        parameter Y_TL      = 22 ,
        parameter CB_TH     = 138,
        parameter CB_TL     = 129,
        parameter CR_TH     = 141,
        parameter CR_TL     = 129, //deep red apple

//        parameter Y_TH_B      = 115 ,
//        parameter Y_TL_B      = 25  ,
//        parameter CB_TH_B     = 255 ,
//        parameter CB_TL_B     = 186 ,
//        parameter CR_TH_B     = 140 ,
//        parameter CR_TL_B     = 80  , //blule

        parameter Y_TH_G      = 126 ,
        parameter Y_TL_G      = 72  ,
        parameter CB_TH_G     = 139 ,
        parameter CB_TL_G     = 128 ,
        parameter CR_TH_G     = 130 ,
        parameter CR_TL_G     = 128 , //green pear

        parameter Y_TH_Y_B    = 164 ,
        parameter Y_TL_Y_B    = 130 ,
        parameter CB_TH_Y_B   = 140 ,
        parameter CB_TL_Y_B   = 128 ,
        parameter CR_TH_Y_B   = 142 ,
        parameter CR_TL_Y_B   = 137 ,  //light yellow banana

        parameter Y_TH_Y_M    = 167 ,
        parameter Y_TL_Y_M    = 145 ,
        parameter CB_TH_Y_M   = 164 ,
        parameter CB_TL_Y_M   = 144 ,
        parameter CR_TH_Y_M   = 180 ,
        parameter CR_TL_Y_M   = 140 ,  //pure yellow mango

        parameter Y_TH_Y_O    = 128 ,
        parameter Y_TL_Y_O    = 63  ,
        parameter CB_TH_Y_O   = 141 ,
        parameter CB_TL_Y_O   = 128 ,
        parameter CR_TH_Y_O   = 179 ,
        parameter CR_TL_Y_O   = 171 ,  //orange orange

        parameter Y_TH_P      = 79  ,
        parameter Y_TL_P      = 37  ,
        parameter CB_TH_P     = 154 ,
        parameter CB_TL_P     = 134 ,
        parameter CR_TH_P     = 160 ,
        parameter CR_TL_P     = 153 ,   //purple grape

        parameter Y_TH_PK     = 160 ,
        parameter Y_TL_PK     = 56  ,
        parameter CB_TH_PK    = 208 ,
        parameter CB_TL_PK    = 146 ,
        parameter CR_TH_PK    = 193 ,
        parameter CR_TL_PK    = 156 ,   //pink pitaya

        parameter Y_TH_N      = 187  ,
        parameter Y_TL_N      = 20  ,
        parameter CB_TH_N     = 191 ,
        parameter CB_TL_N     = 128 ,
        parameter CR_TH_N     = 145 ,
        parameter CR_TL_N     = 132     //brown kiwi fruit        
)(
        input                            pixelclk   ,
        input                            reset_n    ,
        input [DW-1:0]                   i_ycbcr    ,
        input [DW-1:0]                   i_rgb      ,
        input                            i_hsync    ,
        input                            i_vsync    ,
        input                            i_de       ,
        
        output                           y_large_g  ,
        output                           p_large_g  ,
        output                           p_large_o  ,
        output                           r_large_g  ,
        output                           n_large_g  ,
        output                           pk_large_o ,
        output                           r_large_py ,
        output                           pk_large_py,
        output                           y_large_py ,
        output                           py_large_g ,
        output                           enable_r   , //color instruct signal output to uart 
//        output                           enable_b   ,
        output                           enable_g   ,
        output                           enable_y   ,
        output                           enable_p   ,
        output                           enable_n   ,
        output                           enable_py  , //pure yellow
        output                           enable_o   , //orange
        output                           enable_pk  , //pink
        output  [DW-1:0]                 binary_g   ,
        output  [DW-1:0]                 binary_o   ,
        output  [DW-1:0]                 binary_y   ,
        output  [DW-1:0]                 binary_py  ,
        output [DW-1:0]                  o_rgb      ,
        output                           o_hsync    ,
        output                           o_vsync    ,   
        output                           o_de                                                                                                
);

parameter         y_threold = 20'd10000;

localparam        R_TH_B = 218;
localparam        R_TL_B = 149;
localparam        G_TH_B = 203; 
localparam        G_TL_B = 139;
localparam        B_TH_B = 7  ;
localparam        B_TL_B = 0  ;

reg  [DW-1:0]           binary_r      ; //red
reg  [DW-1:0]           r_binary_g     ; //green
reg  [DW-1:0]           r_binary_o     ; //orange
reg  [DW-1:0]           r_binary_y     ; //yellow
reg  [DW-1:0]           r_binary_py    ; //pure yellow


reg  [DW-1:0]           i_rgb_r       ;
reg                     h_sync_r      ;
reg                     v_sync_r      ;
//color instruct signal output to uart 
reg                     r_enable_r    ; //red
reg                     r_enable_b    ; //blue
reg                     r_enable_g    ; //green
reg                     r_enable_y    ; //light yellow
reg                     r_enable_p    ; //purple
reg                     r_enable_n    ; //brown
reg                     r_enable_py   ; //pure yellow
reg                     r_enable_o    ; //orange
reg                     r_enable_pk   ; //pink
reg                     de_r          ;

reg         [19:0]      g_cnt  /* synthesis syn_preserve = 1 */;
reg         [19:0]      y_cnt  ;
reg         [19:0]      o_cnt  ;
reg         [19:0]     py_cnt  ;
reg         [19:0]      p_cnt  ;
reg         [19:0]      r_cnt  /* synthesis syn_preserve = 1 */;
reg         [19:0]      n_cnt  ;
reg         [19:0]     pk_cnt  ;

reg                    r_pk_large_o;
reg                    r_y_large_g;
reg                    r_p_large_g;
reg                    r_p_large_o;
reg                    r_r_large_g;
reg                    r_n_large_g;
reg                    r_r_large_py;
reg                    r_pk_large_py;
reg                    r_y_large_py;
reg                    r_py_large_g;

assign     pk_large_o= r_pk_large_o;
assign     n_large_g = r_n_large_g;
assign     r_large_g = r_r_large_g;
assign     p_large_g = r_p_large_g;
assign     p_large_o = r_p_large_o;
assign     y_large_g = r_y_large_g;
assign     r_large_py = r_r_large_py;
assign     pk_large_py = r_pk_large_py;
assign     y_large_py = r_y_large_py;
assign     py_large_g = r_py_large_g;

wire                    en0           ; //red enable signal
wire                    en1           ;
wire                    en2           ;
wire                    en0_b         ; //blue enable signal
wire                    en1_b         ;
wire                    en2_b         ;
wire                    en0_g         ; //green enable signal
wire                    en1_g         ;
wire                    en2_g         ;
wire                    en0_y         ; //light yellow enable signal
wire                    en1_y         ;
wire                    en2_y         ;
wire                    en0_p         ; //purple enable signal
wire                    en1_p         ;
wire                    en2_p         ;
wire                    en0_n         ; //brown enable signal
wire                    en1_n         ;
wire                    en2_n         ;
wire                    en0_py        ; //pure yellow enable signal
wire                    en1_py        ;
wire                    en2_py        ;
wire                    en0_o         ; //orange enable signal
wire                    en1_o         ;
wire                    en2_o         ;
wire                    en0_pk        ; //pink enable signal
wire                    en1_pk        ;
wire                    en2_pk        ;

assign binary_g = r_binary_g ;
assign binary_o = r_binary_o ;
assign binary_y = r_binary_y ;
assign binary_py= r_binary_py; 

assign o_rgb    = i_rgb_r;
assign o_hsync  = h_sync_r;
assign o_vsync  = v_sync_r;
assign o_de     = de_r;

assign enable_r = r_enable_r ; 
//assign enable_b = r_enable_b ;
assign enable_g = r_enable_g ;
assign enable_y = r_enable_y ;
assign enable_p = r_enable_p ;
assign enable_n = r_enable_n ;
assign enable_py= r_enable_py;
assign enable_o = r_enable_o ;
assign enable_pk= r_enable_pk;

//wire     [23:0]    en_sum ;
wire     [7:0]     y_temp ;
wire     [7:0]     cb_temp;
wire     [7:0]     cr_temp;
assign   y_temp  =  i_ycbcr[23:16] ;
assign   cb_temp =  i_ycbcr[15: 8] ;
assign   cr_temp =  i_ycbcr[ 7: 0] ;

////////////////////// threshold//////////////////////////////////////
assign en0      =i_ycbcr[23:16] >=Y_TL  && i_ycbcr[23:16] <= Y_TH;
assign en1      =i_ycbcr[15: 8] >=CB_TL && i_ycbcr[15: 8] <= CB_TH;
assign en2      =i_ycbcr[ 7: 0] >=CR_TL && i_ycbcr[ 7: 0] <= CR_TH;
//assign en0_b      =i_ycbcr[23:16] >=Y_TL_B && i_ycbcr[23:16] <= Y_TH_B  ;
//assign en1_b      =i_ycbcr[15: 8] >=CB_TL_B && i_ycbcr[15: 8] <= CB_TH_B;
//assign en2_b      =i_ycbcr[ 7: 0] >=CR_TL_B && i_ycbcr[ 7: 0] <= CR_TH_B;
assign en0_g      =i_ycbcr[23:16] >=Y_TL_G && i_ycbcr[23:16]  <= Y_TH_G;
assign en1_g      =i_ycbcr[15: 8] >=CB_TL_G  && i_ycbcr[15: 8] <= CB_TH_G;
assign en2_g      =i_ycbcr[ 7: 0] >=CR_TL_G  && i_ycbcr[ 7: 0] <= CR_TH_G;
assign en0_y      =i_ycbcr[23:16] >=Y_TL_Y_B && i_ycbcr[23:16]  <= Y_TH_Y_B;
assign en1_y      =i_ycbcr[15: 8] >=CB_TL_Y_B  && i_ycbcr[15: 8] <= CB_TH_Y_B;
assign en2_y      =i_ycbcr[ 7: 0] >=CR_TL_Y_B  && i_ycbcr[ 7: 0] <= CR_TH_Y_B;
//assign en0_y      =i_rgb[23:16] >=R_TL_B && i_rgb[23:16]  <= R_TH_B;
//assign en1_y      =i_rgb[15: 8] >=G_TL_B  && i_rgb[15: 8] <= G_TH_B;
//assign en2_y      =i_rgb[ 7: 0] >=B_TL_B  && i_rgb[ 7: 0] <= B_TH_B;
assign en0_p      =i_ycbcr[23:16] >=Y_TL_P && i_ycbcr[23:16]  <= Y_TH_P;
assign en1_p      =i_ycbcr[15: 8] >=CB_TL_P  && i_ycbcr[15: 8] <= CB_TH_P;
assign en2_p      =i_ycbcr[ 7: 0] >=CR_TL_P  && i_ycbcr[ 7: 0] <= CR_TH_P;
assign en0_n      =i_ycbcr[23:16] >=Y_TL_N && i_ycbcr[23:16]  <= Y_TH_N;
assign en1_n      =i_ycbcr[15: 8] >=CB_TL_N  && i_ycbcr[15: 8] <= CB_TH_N;
assign en2_n      =i_ycbcr[ 7: 0] >=CR_TL_N  && i_ycbcr[ 7: 0] <= CR_TH_N;
assign en0_py     =i_ycbcr[23:16] >=Y_TL_Y_M && i_ycbcr[23:16]  <= Y_TH_Y_M;
assign en1_py     =i_ycbcr[15: 8] >=CB_TL_Y_M  && i_ycbcr[15: 8] <= CB_TH_Y_M;
assign en2_py     =i_ycbcr[ 7: 0] >=CR_TL_Y_M  && i_ycbcr[ 7: 0] <= CR_TH_Y_M;
assign en0_o      =i_ycbcr[23:16] >=Y_TL_Y_O && i_ycbcr[23:16]  <= Y_TH_Y_O;
assign en1_o      =i_ycbcr[15: 8] >=CB_TL_Y_O  && i_ycbcr[15: 8] <= CB_TH_Y_O;
assign en2_o      =i_ycbcr[ 7: 0] >=CR_TL_Y_O  && i_ycbcr[ 7: 0] <= CR_TH_Y_O;
assign en0_pk     =i_ycbcr[23:16] >=Y_TL_PK && i_ycbcr[23:16]  <= Y_TH_PK;
assign en1_pk     =i_ycbcr[15: 8] >=CB_TL_PK  && i_ycbcr[15: 8] <= CB_TH_PK;
assign en2_pk     =i_ycbcr[ 7: 0] >=CR_TL_PK  && i_ycbcr[ 7: 0] <= CR_TH_PK;
//assign en_sum     ={,,en0_y,en1_y,en2_y,en0_p,en1_p,en2_p,en0_n,en1_n,en2_n,en0_py,en1_py,en2_py,en0_o,en1_o,en2_o,en0_pk,en1_pk,en2_pk};

/********************************************************************************************/

/***************************************timing***********************************************/

always @(posedge pixelclk)begin
    h_sync_r<= i_hsync;
    v_sync_r<= i_vsync;
    de_r    <= i_de;
    i_rgb_r <= i_rgb;
end 

reg       v_sync_r_d1    ;
reg       v_sync_r_d2    ;
wire      v_sync_r_neg   ;
wire      v_sync_r_pos   ;

assign    v_sync_r_neg = (!v_sync_r_d1)&v_sync_r_d2;
assign    v_sync_r_pos = v_sync_r_d1&(!v_sync_r_d2);

always @(posedge pixelclk)begin
    v_sync_r_d1<= v_sync_r;
    v_sync_r_d2<= v_sync_r_d1;
end 
/********************************************************************************************/

/***************************************Binarization threshold*******************************/


always @(posedge pixelclk or negedge reset_n) begin
    if(!reset_n)begin 
        binary_r <= 24'd0;
        r_enable_r <= 1'b0;      
    end 
    else if(en0==1'b1 && en1==1'b1 && en2==1'b1) begin 
            r_enable_r <= 1'b1;
            binary_r <= 24'h333333;
        end             		 	
    else begin            
            binary_r <= 24'hffffff;
            r_enable_r <= 1'b0;
        end  
end 

//always @(posedge pixelclk or negedge reset_n) begin
//    if(!reset_n)begin 
//        r_enable_g <= 1'b0;       
//    end              		 	
//    else if(en0_g==1'b1 && en1_g ==1'b1 && en2_g==1'b1)begin 
//            r_enable_g <= 1'b1;        
//    end
//    else begin            
//            r_enable_g <= 1'b0; 
//        end 
//end 


//always @(posedge pixelclk or negedge reset_n) begin
//    if(!reset_n)begin 
//        r_enable_y <= 1'b0;       
//    end 
//    else if(en0_y==1'b1 && en1_y ==1'b1 && en2_y==1'b1)begin 
//            r_enable_y <= 1'b1;  
//    end    
//    else begin            
//            r_enable_y <= 1'b0;
//        end  
//end 

always @(posedge pixelclk or negedge reset_n) begin
    if(!reset_n)begin 
        r_enable_p <= 1'b0;       
    end 
    else if(en0_p==1'b1 && en1_p ==1'b1 && en2_p==1'b1)begin 
            r_enable_p <= 1'b1;  
    end    
    else begin            
            r_enable_p <= 1'b0;
        end  
end

//always @(posedge pixelclk or negedge reset_n) begin
//    if(!reset_n)begin 
//        r_enable_o <= 1'b0;       
//    end 
//    else if(en0_o==1'b1 && en1_o ==1'b1 && en2_o==1'b1)begin 
//            r_enable_o <= 1'b1;  
//    end    
//    else begin            
//            r_enable_o <= 1'b0;
//        end  
//end
always @(posedge pixelclk or negedge reset_n) begin
    if(!reset_n)begin 
        r_binary_g <= 24'd0;
        r_enable_g <= 1'b0;
    end 
    else if(en0_g==1'b1 && en1_g ==1'b1 && en2_g==1'b1)begin 
        r_enable_g <= 1'b1;        
        r_binary_g <= 24'h111111;
    end  
    else begin
        r_binary_g <= 24'd0;
        r_enable_g <= 1'b0;
    end
end 

always @(posedge pixelclk or negedge reset_n) begin
    if(!reset_n)begin 
        r_binary_y <= 24'd0;
        r_enable_y <= 1'b0;
    end 
    else if(en0_y==1'b1 && en1_y ==1'b1 && en2_y==1'b1)begin 
        r_enable_y <= 1'b1;  
        r_binary_y <= 24'h222222;
    end    
    else begin            
        r_binary_y <= 24'd0;
        r_enable_y <= 1'b0;
    end  
end 

always @(posedge pixelclk or negedge reset_n) begin
    if(!reset_n)begin 
        r_binary_o <= 24'd0;
        r_enable_o <= 1'b0;
    end  
    else if(en0_o==1'b1 && en1_o ==1'b1 && en2_o==1'b1)begin 
        r_enable_o <= 1'b1;  
        r_binary_o <= 24'h333333;
    end
    else begin            
        r_binary_o <= 24'd0;
        r_enable_o <= 1'b0;
    end
end 

always @(posedge pixelclk or negedge reset_n) begin
    if(!reset_n)begin 
        r_binary_py <= 24'd0;
        r_enable_py<= 1'b0;
    end 
    else if(en0_py==1'b1 && en1_py ==1'b1 && en2_py==1'b1)begin 
        r_enable_py <= 1'b1;  
        r_binary_py <= 24'h444444;
    end
    else begin            
        r_binary_py <= 24'd0;
        r_enable_py<= 1'b0;
        end 
end 

always @(posedge pixelclk or negedge reset_n) begin
    if(!reset_n)begin 
        r_cnt <= 20'd0;       
    end 
    else if(en0==1'b1 && en1 ==1'b1 && en2==1'b1)begin 
        r_cnt <= r_cnt + 20'd1;       
    end    
    else if (v_sync_r_neg == 1'b1)            
        r_cnt <= 20'd0;      
    else 
        r_cnt <= r_cnt;
end

always @(posedge pixelclk or negedge reset_n) begin
    if(!reset_n)begin 
        p_cnt <= 20'd0;       
    end 
    else if(en0_p==1'b1 && en1_p ==1'b1 && en2_p==1'b1)begin 
        p_cnt <= p_cnt + 20'd1;       
    end    
    else if (v_sync_r_neg == 1'b1)            
        p_cnt <= 20'd0;      
    else 
        p_cnt <= p_cnt;
end

always @(posedge pixelclk or negedge reset_n) begin
    if(!reset_n)begin 
        pk_cnt <= 20'd0;       
    end 
    else if(en0_pk==1'b1 && en1_pk==1'b1 && en2_pk==1'b1)begin 
        pk_cnt <= pk_cnt + 20'd1;       
    end    
    else if (v_sync_r_neg == 1'b1)            
        pk_cnt <= 20'd0;      
    else 
        pk_cnt <= pk_cnt;
end

always @(posedge pixelclk or negedge reset_n) begin
    if(!reset_n)begin 
        g_cnt <= 20'd0;       
    end 
    else if(en0_g==1'b1 && en1_g ==1'b1 && en2_g==1'b1)begin 
        g_cnt <= g_cnt + 20'd1;       
    end    
    else if (v_sync_r_neg == 1'b1)            
        g_cnt <= 20'd0;      
    else 
        g_cnt <= g_cnt;
end

always @(posedge pixelclk or negedge reset_n) begin
    if(!reset_n)begin 
        n_cnt <= 20'd0;       
    end 
    else if(en0_n==1'b1 && en1_n ==1'b1 && en2_n==1'b1)begin 
        n_cnt <= n_cnt + 20'd1;       
    end    
    else if (v_sync_r_neg == 1'b1)            
        n_cnt <= 20'd0;      
    else 
        n_cnt <= n_cnt;
end

always @(posedge pixelclk or negedge reset_n) begin
    if(!reset_n)begin 
        y_cnt <= 20'd0;       
    end 
    else if(en0_y==1'b1 && en1_y ==1'b1 && en2_y==1'b1)begin 
        y_cnt <= y_cnt + 20'd1;       
    end    
    else if (v_sync_r_neg == 1'b1)            
        y_cnt <= 20'd0;      
    else 
        y_cnt <= y_cnt;
end

always @(posedge pixelclk or negedge reset_n) begin
    if(!reset_n)begin 
        o_cnt <= 20'd0;       
    end 
    else if(en0_o==1'b1 && en1_o==1'b1 && en2_o==1'b1)begin 
        o_cnt <= o_cnt + 20'd1;       
    end    
    else if (v_sync_r_neg == 1'b1)            
        o_cnt <= 20'd0;      
    else 
        o_cnt <= o_cnt;
end

always @(posedge pixelclk or negedge reset_n) begin
    if(!reset_n)begin 
        py_cnt <= 20'd0;       
    end 
    else if(en0_py==1'b1 && en1_py==1'b1 && en2_py==1'b1)begin 
        py_cnt <= py_cnt + 20'd1;       
    end    
    else if (v_sync_r_neg == 1'b1)            
        py_cnt <= 20'd0;      
    else 
        py_cnt <= py_cnt;
end

always @(posedge pixelclk or negedge reset_n) begin
    if(!reset_n)
        r_pk_large_o <= 1'b0;       
    else if(v_sync_r_neg == 1'b1 && pk_cnt > o_cnt)
        r_pk_large_o <= 1'b1;       
    else if (v_sync_r_neg == 1'b1 && pk_cnt <= o_cnt)            
        r_pk_large_o <= 1'b0;        
    else 
        r_pk_large_o <= r_pk_large_o;       
end

always @(posedge pixelclk or negedge reset_n) begin
    if(!reset_n)
        r_r_large_py <= 1'b0;       
    else if(v_sync_r_neg == 1'b1 && r_cnt > py_cnt && r_cnt > y_threold)
        r_r_large_py <= 1'b1;       
    else if (v_sync_r_neg == 1'b1 && r_cnt <= py_cnt)            
        r_r_large_py <= 1'b0;        
    else 
        r_r_large_py <= r_r_large_py;       
end

always @(posedge pixelclk or negedge reset_n) begin
    if(!reset_n)
        r_y_large_g <= 1'b0;       
    else if(v_sync_r_neg == 1'b1 && y_cnt > g_cnt && y_cnt > y_threold)
        r_y_large_g <= 1'b1;       
    else if (v_sync_r_neg == 1'b1 && y_cnt <= g_cnt)            
        r_y_large_g <= 1'b0;        
    else 
        r_y_large_g <= r_y_large_g;       
end

always @(posedge pixelclk or negedge reset_n) begin
    if(!reset_n)
        r_p_large_g <= 1'b0;       
    else if(v_sync_r_neg == 1'b1 && p_cnt > g_cnt && p_cnt > y_threold)
        r_p_large_g <= 1'b1;       
    else if (v_sync_r_neg == 1'b1 && p_cnt <= g_cnt)            
        r_p_large_g <= 1'b0;        
    else 
        r_p_large_g <= r_p_large_g;       
end

always @(posedge pixelclk or negedge reset_n) begin
    if(!reset_n)
        r_p_large_o <= 1'b0;       
    else if(v_sync_r_neg == 1'b1 && p_cnt > o_cnt && p_cnt > y_threold)
        r_p_large_o <= 1'b1;       
    else if (v_sync_r_neg == 1'b1 && p_cnt <= o_cnt)            
        r_p_large_o <= 1'b0;        
    else 
        r_p_large_o <= r_p_large_o;       
end

always @(posedge pixelclk or negedge reset_n) begin
    if(!reset_n)
        r_n_large_g <= 1'b0;       
    else if(v_sync_r_neg == 1'b1 && n_cnt > g_cnt && n_cnt > y_threold)
        r_n_large_g <= 1'b1;       
    else if (v_sync_r_neg == 1'b1 && n_cnt <= g_cnt)            
        r_n_large_g <= 1'b0;        
    else 
        r_n_large_g <= r_n_large_g;       
end

always @(posedge pixelclk or negedge reset_n) begin
    if(!reset_n)
        r_r_large_g <= 1'b0;       
    else if(v_sync_r_neg == 1'b1 && r_cnt > g_cnt)
        r_r_large_g <= 1'b1;       
    else if (v_sync_r_neg == 1'b1 && r_cnt <= g_cnt)            
        r_r_large_g <= 1'b0;        
    else 
        r_r_large_g <= r_r_large_g;       
end

always @(posedge pixelclk or negedge reset_n) begin
    if(!reset_n)
        r_pk_large_py <= 1'b0;       
    else if(v_sync_r_neg == 1'b1 && pk_cnt > py_cnt)
        r_pk_large_py <= 1'b1;       
    else if (v_sync_r_neg == 1'b1 && pk_cnt <= py_cnt)            
        r_pk_large_py <= 1'b0;        
    else 
        r_pk_large_py <= r_pk_large_py;       
end

always @(posedge pixelclk or negedge reset_n) begin
    if(!reset_n)
        r_y_large_py <= 1'b0;       
    else if(v_sync_r_neg == 1'b1 && y_cnt > py_cnt)
        r_y_large_py <= 1'b1;       
    else if (v_sync_r_neg == 1'b1 && y_cnt <= py_cnt)            
        r_y_large_py <= 1'b0;        
    else 
        r_y_large_py <= r_y_large_py;       
end


always @(posedge pixelclk or negedge reset_n) begin
    if(!reset_n)
        r_py_large_g <= 1'b0;       
    else if(v_sync_r_neg == 1'b1 && py_cnt > g_cnt && py_cnt > y_threold)
        r_py_large_g <= 1'b1;       
    else if (v_sync_r_neg == 1'b1 && g_cnt <= py_cnt)            
        r_py_large_g <= 1'b0;        
    else 
        r_py_large_g <= r_py_large_g;       
end

always @(posedge pixelclk or negedge reset_n) begin
    if(!reset_n)begin 
        r_enable_n <= 1'b0;       
    end 
    else if(en0_n==1'b1 && en1_n ==1'b1 && en2_n==1'b1)begin 
            r_enable_n <= 1'b1;  
    end    
    else begin            
            r_enable_n <= 1'b0;
        end  
end

always @(posedge pixelclk or negedge reset_n) begin
    if(!reset_n)begin 
        r_enable_pk <= 1'b0;       
    end 
    else if(en0_pk==1'b1 && en1_pk ==1'b1 && en2_pk==1'b1)begin 
            r_enable_pk <= 1'b1;  
    end    
    else begin            
            r_enable_pk <= 1'b0;
        end  
end


//always @(posedge pixelclk or negedge reset_n) begin
//    if(!reset_n)begin 
////        binary_r <= 24'd0;
//          r_enable_n <= 1'b0;
//          r_enable_py<= 1'b0;
//          r_enable_pk<= 1'b0;        
//    end 
//    else begin 
//        if(en0_n==1'b1 && en1_n ==1'b1) begin  //kiwi fruit Y and Cb include mango's Y and Cb
//            if (en2_n==1'b1)
//               r_enable_n <= 1'b1;
//            else if (en0_py==1'b1 && en1_py ==1'b1 && en2_py==1'b1)
//               r_enable_pk<= 1'b1;
//            else begin
//               r_enable_n <= 1'b0; 
//               r_enable_pk<= 1'b0;
//            end              
//        end             		 	
//		else if(en0_pk==1'b1 && en1_pk ==1'b1 && en2_pk==1'b1)begin 
//            r_enable_pk <= 1'b1;        
//		end
//        else begin            
//            r_enable_n <= 1'b0;
//            r_enable_py<= 1'b0;
//            r_enable_pk<= 1'b0;
//        end 
//    end  
//end

//	generate
//	if (P_LOG_ENABLE == 32'd1) begin: log
//		integer THRDSHOLDBIN_file   	;
//		
//		initial begin
////		    BINARIZATION_file  = $fopen ({"D:/FPGA_CODE/Other_work/fruit/Sim/ISP_sim/Data/THRDSHOLDBIN.txt"}   , "w" ) ;
//		    THRDSHOLDBIN_file  = $fopen ({"THRDSHOLDBIN.txt"}   , "w" ) ;
//		end
//		
//		always @ ( posedge pixelclk ) begin
//			if ( de_r ) begin
//		    	$fdisplay (THRDSHOLDBIN_file , "%b", r_binary_op) ;
//			end
//		end		
//	end 
//	endgenerate

endmodule 