IP Generator (Version 2020.3 build 62942)
Check out license ...
Start generating at 2022-05-15 18:47
Instance: ila1 (D:\FPGA_CODE\Other_work\fruit\Prj\isp_ddr3_ov5640_hdmi\ipcore\ila1\ila1.idf)
Model: DebugCore (1.3)
Part: Logos-PGL22G-MBG324--6
Create directory 'rtl' ...
Copy 'rtl\ips_dbc_cfg_reg_file_v1_0.v' to 'rtl' ...
Copy 'rtl\ips_dbc_compare_256b_v1_0.v' to 'rtl' ...
Copy 'rtl\ips_dbc_data_capture_mem_v1_0.v' to 'rtl' ...
Copy 'rtl\ips_dbc_debug_core_v1_3.v' to 'rtl' ...
Copy 'rtl\ips_dbc_hub_decode_v1_2.v' to 'rtl' ...
Copy 'rtl\ips_dbc_rd_addr_gen_v1_3.v' to 'rtl' ...
Copy 'rtl\ips_dbc_storage_condition_v1_3.v' to 'rtl' ...
Copy 'rtl\ips_dbc_storage_qualification_v1_2.v' to 'rtl' ...
Copy 'rtl\ips_dbc_trig_unit_v1_3.v' to 'rtl' ...
Copy 'rtl\ips_dbc_trigger_condition_v1_3.v' to 'rtl' ...
Copy 'rtl\ips_dbc_trigger_output_v1_2.v' to 'rtl' ...
Copy 'ips_dbc_wrapper_v1_3.v.xml' ...
Copy 'ips_dbc_inst.fdc.xml' ...
Compile file 'ips_dbc_wrapper_v1_3.v.xml' to 'ila1.v' ...
Found top module 'ila1' in file 'ila1.v'.
Compile file 'ips_dbc_inst.fdc.xml' to 'ila1.fdc' ...
Create template file 'ila1_tmpl.v' ...
Create template file 'ila1_tmpl.vhdl' ...
There are 12 source files to synthesize.
Synthesis is disabled.
Done: 0 error(s), 0 warning(s)
