@W: MO171 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\encode.v":135:2:135:7|Sequential instance dvi_encoder_m0.encg.c0_q is reduced to a combinational gate by constant propagation. 
@W: MO171 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\encode.v":135:2:135:7|Sequential instance dvi_encoder_m0.encr.c0_q is reduced to a combinational gate by constant propagation. 
@W: MO171 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\encode.v":135:2:135:7|Sequential instance dvi_encoder_m0.encg.c1_q is reduced to a combinational gate by constant propagation. 
@W: MO171 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\encode.v":135:2:135:7|Sequential instance dvi_encoder_m0.encr.c1_q is reduced to a combinational gate by constant propagation. 
@W: FX1172 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\serdes_4b_10to1.v":48:0:48:5|User-specified initial value defined for instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[2:0] is being ignored due to limitations in architecture. 
@W: FX1172 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\serdes_4b_10to1.v":48:0:48:5|User-specified initial value defined for instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_3l[4:0] is being ignored due to limitations in architecture. 
@W: FX1172 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\serdes_4b_10to1.v":48:0:48:5|User-specified initial value defined for instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_3h[4:0] is being ignored due to limitations in architecture. 
@W: FX1172 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\serdes_4b_10to1.v":48:0:48:5|User-specified initial value defined for instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_2l[4:0] is being ignored due to limitations in architecture. 
@W: FX1172 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\serdes_4b_10to1.v":48:0:48:5|User-specified initial value defined for instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_2h[4:0] is being ignored due to limitations in architecture. 
@W: FX1172 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\serdes_4b_10to1.v":48:0:48:5|User-specified initial value defined for instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_1l[4:0] is being ignored due to limitations in architecture. 
@W: FX1172 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\serdes_4b_10to1.v":48:0:48:5|User-specified initial value defined for instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_1h[4:0] is being ignored due to limitations in architecture. 
@W: FX1172 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\serdes_4b_10to1.v":48:0:48:5|User-specified initial value defined for instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_0l[4:0] is being ignored due to limitations in architecture. 
@W: FX1172 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\serdes_4b_10to1.v":48:0:48:5|User-specified initial value defined for instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_0h[4:0] is being ignored due to limitations in architecture. 
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_reset_ctrl.v":141:0:141:5|Removing sequential instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_ddrphy_reset_ctrl.srb_ioclkdiv_rstn because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_ddrphy_reset_ctrl.srb_dqs_rstn. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_reset_ctrl.v":125:0:125:5|Removing sequential instance u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.init_axi_reset2 because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.init_ddrc_rst. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_reset_ctrl.v":125:0:125:5|Removing sequential instance u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.init_axi_reset1 because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.init_ddrc_rst. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_reset_ctrl.v":125:0:125:5|Removing sequential instance u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.init_axi_reset0 because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.init_ddrc_rst. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MT531 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_hmemc_ddrc_top.v":337:9:337:14|Found signal identified as System clock which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc.  Using this clock, which has no specified timing constraint, can prevent conversion of gated or generated clocks and can adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_32i_64o_256\rtl\ipml_sdpram_v1_3_afifo_32i_64o_256.v":825:10:825:21|Found inferred clock pll_50_400|clkout3_inferred_clock which controls 549 sequential elements including frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_sdpram.ADDR_LOOP\[0\]\.DATA_LOOP\[1\]\.U_GTP_DRM18K. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_reset_ctrl.v":52:0:52:5|Found inferred clock pll_50_400|clkout1_inferred_clock which controls 148 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_ddrphy_reset_ctrl.state[10]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":960:6:960:15|Found inferred clock ipsl_phy_io_Z8|IOCLK_DIV_inferred_clock which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1134:5:1134:12|Found inferred clock ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[0] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1956:12:1956:25|Found inferred clock ipsl_phy_io_Z8|ioclk_01_inferred_clock which controls 19 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr36_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1171:13:1171:20|Found inferred clock ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[1] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1211:6:1211:13|Found inferred clock ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[2] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1248:13:1248:20|Found inferred clock ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[3] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1285:13:1285:20|Found inferred clock ipsl_phy_io_Z8|ioclk_02_inferred_clock which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1285:13:1285:20|Found inferred clock ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[4] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1597:12:1597:25|Found inferred clock ipsl_phy_io_Z8|dqs0_clk_r_inferred_clock which controls 10 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr12_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1332:12:1332:24|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[2] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr2_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1597:12:1597:25|Found inferred clock ipsl_phy_io_Z8|dqs_clkw290_0_inferred_clock which controls 9 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr12_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1363:12:1363:24|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[3] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr3_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1586:12:1586:25|Found inferred clock ipsl_phy_io_Z8|dqs_90_0_inferred_clock which controls 8 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr12_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1395:12:1395:24|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[4] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr4_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1426:12:1426:24|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[5] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr5_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1458:12:1458:24|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[6] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr6_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1489:12:1489:24|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[7] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr7_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1502:12:1502:24|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[9] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr9_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1502:12:1502:24|Found inferred clock ipsl_phy_io_Z8|dqs_clkw_0_inferred_clock which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr9_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1534:12:1534:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[10] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr10_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1565:12:1565:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[11] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr11_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1597:12:1597:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[12] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr12_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1700:12:1700:25|Found inferred clock ipsl_phy_io_Z8|dqs_ca_clk_r_01_inferred_clock which controls 9 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1609:12:1609:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[17] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr17_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1700:12:1700:25|Found inferred clock ipsl_phy_io_Z8|dqs_clkw_ca_01_inferred_clock which controls 9 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1621:12:1621:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[18] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr18_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1632:12:1632:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[19] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr19_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1644:12:1644:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[20] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr20_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1655:12:1655:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[21] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr21_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1666:12:1666:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[22] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr22_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1677:12:1677:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[23] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr23_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1689:12:1689:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[24] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr24_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1700:12:1700:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[25] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1733:12:1733:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[27] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr27_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1956:12:1956:25|Found inferred clock ipsl_phy_io_Z8|dqs_90_1_inferred_clock which controls 8 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr36_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1978:12:1978:25|Found inferred clock ipsl_phy_io_Z8|dqs1_clk_r_inferred_clock which controls 10 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1978:12:1978:25|Found inferred clock ipsl_phy_io_Z8|dqs_clkw290_1_inferred_clock which controls 9 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1765:12:1765:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[28] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr28_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1796:12:1796:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[29] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr29_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1809:12:1809:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[31] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr31_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1809:12:1809:25|Found inferred clock ipsl_phy_io_Z8|dqs_clkw_1_inferred_clock which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr31_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1841:12:1841:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[32] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr32_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1872:12:1872:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[33] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr33_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1904:12:1904:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[34] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr34_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1935:12:1935:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[35] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr35_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1967:12:1967:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[36] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr36_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1978:12:1978:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[37] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2126:12:2126:25|Found inferred clock ipsl_phy_io_Z8|dqs_ca_clk_r_03_inferred_clock which controls 12 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1993:12:1993:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[40] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr40_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2126:12:2126:25|Found inferred clock ipsl_phy_io_Z8|dqs_clkw_ca_03_inferred_clock which controls 12 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2006:12:2006:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[41] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr41_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2020:12:2020:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[42] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr42_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2031:12:2031:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[43] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr43_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2045:12:2045:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[44] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr44_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2056:12:2056:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[45] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr45_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2068:12:2068:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[46] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr46_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2078:12:2078:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[47] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr47_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2090:12:2090:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[48] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr48_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2101:12:2101:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[49] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr49_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2114:12:2114:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[51] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr51_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2126:12:2126:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[52] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2187:12:2187:25|Found inferred clock ipsl_phy_io_Z8|dqs_ca_clk_r_04_inferred_clock which controls 5 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2140:12:2140:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[55] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr55_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2187:12:2187:25|Found inferred clock ipsl_phy_io_Z8|dqs_clkw_ca_04_inferred_clock which controls 5 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2152:12:2152:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[56] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr56_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2162:12:2162:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[57] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr57_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2174:12:2174:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[58] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr58_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2187:12:2187:25|Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[59] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":54:0:54:5|Found inferred clock ipsl_ddrphy_dll_update_ctrl|dll_update_n_inferred_clock which controls 9 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.last_dll_step[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\encode.v":108:2:108:7|Found inferred clock video_pll|clkout0_inferred_clock which controls 245 sequential elements including dvi_encoder_m0.encb.n0q_m[3:1]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\serdes_4b_10to1.v":48:0:48:5|Found inferred clock video_pll|clkout1_inferred_clock which controls 59 sequential elements including dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[2:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
