#Build: Fabric Compiler 2020.3, Build 62942, Sep 29 13:34 2020
#Install: D:\pango\PDS_2020.3\bin
#Application name: pds_shell.exe
#OS: Windows 10 10.0.19042
#Hostname: DESKTOP-0NUJMPK
Generated by Fabric Compiler (version 2020.3 build 62942) at Fri May 27 22:56:27 2022
License checkout: fabric_ads
Compiling verification operator library.
Loading technology operator library.
Compiling technology operator library.
Compiling technology operator (valence) library.
I: Enable Verilog2k features and keywords
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/i2c_master/i2c_config.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/i2c_master/i2c_config.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/i2c_master/i2c_config.v(line number: 30)] Analyzing module i2c_config (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/i2c_master/i2c_config.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/i2c_master/i2c_master_bit_ctrl.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/i2c_master/i2c_master_bit_ctrl.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/i2c_master/i2c_master_bit_ctrl.v(line number: 143)] Analyzing module i2c_master_bit_ctrl (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/i2c_master/i2c_master_bit_ctrl.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/i2c_master/i2c_master_byte_ctrl.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/i2c_master/i2c_master_byte_ctrl.v
W: Public-4030: File 'D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/i2c_master/i2c_master_defines.v' has been added. It is skipped.
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/i2c_master/i2c_master_byte_ctrl.v(line number: 75)] Analyzing module i2c_master_byte_ctrl (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/i2c_master/i2c_master_byte_ctrl.v successfully.
W: Public-4030: File 'D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/i2c_master/i2c_master_defines.v' has been added. It is skipped.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/i2c_master/i2c_master_defines.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/i2c_master/i2c_master_defines.v
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/i2c_master/i2c_master_defines.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/i2c_master/i2c_master_top.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/i2c_master/i2c_master_top.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/i2c_master/i2c_master_top.v(line number: 30)] Analyzing module i2c_master_top (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/i2c_master/i2c_master_top.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/i2c_master/timescale.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/i2c_master/timescale.v
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/i2c_master/timescale.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/aq_axi_master.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/aq_axi_master.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/aq_axi_master.v(line number: 39)] Analyzing module aq_axi_master (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/aq_axi_master.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/cmos_8_16bit.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/cmos_8_16bit.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/cmos_8_16bit.v(line number: 30)] Analyzing module cmos_8_16bit (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/cmos_8_16bit.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/cmos_write_req_gen.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/cmos_write_req_gen.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/cmos_write_req_gen.v(line number: 30)] Analyzing module cmos_write_req_gen (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/cmos_write_req_gen.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/color_bar.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/color_bar.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/color_bar.v(line number: 33)] Analyzing module color_bar (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/color_bar.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/frame_fifo_read.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/frame_fifo_read.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/frame_fifo_read.v(line number: 31)] Analyzing module frame_fifo_read (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/frame_fifo_read.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/frame_fifo_write.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/frame_fifo_write.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/frame_fifo_write.v(line number: 31)] Analyzing module frame_fifo_write (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/frame_fifo_write.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/frame_read_write.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/frame_read_write.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/frame_read_write.v(line number: 31)] Analyzing module frame_read_write (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/frame_read_write.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/lut_ov5640_rgb565_1024_768.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/lut_ov5640_rgb565_1024_768.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/lut_ov5640_rgb565_1024_768.v(line number: 30)] Analyzing module lut_ov5640_rgb565_1024_768 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/lut_ov5640_rgb565_1024_768.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 30)] Analyzing module top (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v successfully.
W: Public-4030: File 'D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/video_define.v' has been added. It is skipped.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/video_define.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/video_define.v
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/video_define.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/video_timing_data.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/video_timing_data.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/video_timing_data.v(line number: 30)] Analyzing module video_timing_data (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/video_timing_data.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/dvi_tx/dvi_encoder.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/dvi_tx/dvi_encoder.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/dvi_tx/dvi_encoder.v(line number: 2)] Analyzing module dvi_encoder (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/dvi_tx/dvi_encoder.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/dvi_tx/encode.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/dvi_tx/encode.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/dvi_tx/encode.v(line number: 46)] Analyzing module encode (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/dvi_tx/encode.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/dvi_tx/serdes_4b_10to1.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/dvi_tx/serdes_4b_10to1.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/dvi_tx/serdes_4b_10to1.v(line number: 3)] Analyzing module serdes_4b_10to1 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/dvi_tx/serdes_4b_10to1.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrc_apb_reset_v1_1.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrc_apb_reset_v1_1.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrc_apb_reset_v1_1.v(line number: 17)] Analyzing module ipsl_hmic_h_ddrc_apb_reset_v1_1 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrc_apb_reset_v1_1.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrc_reset_ctrl_v1_1.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrc_reset_ctrl_v1_1.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrc_reset_ctrl_v1_1.v(line number: 17)] Analyzing module ipsl_hmic_h_ddrc_reset_ctrl_v1_1 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrc_reset_ctrl_v1_1.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrc_top_v1_1.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrc_top_v1_1.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrc_top_v1_1.v(line number: 17)] Analyzing module ipsl_hmic_h_ddrc_top_v1_1 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrc_top_v1_1.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrphy_dll_update_ctrl_v1_1.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrphy_dll_update_ctrl_v1_1.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrphy_dll_update_ctrl_v1_1.v(line number: 17)] Analyzing module ipsl_hmic_h_ddrphy_dll_update_ctrl_v1_1 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrphy_dll_update_ctrl_v1_1.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrphy_reset_ctrl_v1_1.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrphy_reset_ctrl_v1_1.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrphy_reset_ctrl_v1_1.v(line number: 17)] Analyzing module ipsl_hmic_h_ddrphy_reset_ctrl_v1_1 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrphy_reset_ctrl_v1_1.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrphy_training_ctrl_v1_1.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrphy_training_ctrl_v1_1.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrphy_training_ctrl_v1_1.v(line number: 17)] Analyzing module ipsl_hmic_h_ddrphy_training_ctrl_v1_1 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrphy_training_ctrl_v1_1.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrphy_update_ctrl_v1_1.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrphy_update_ctrl_v1_1.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrphy_update_ctrl_v1_1.v(line number: 17)] Analyzing module ipsl_hmic_h_ddrphy_update_ctrl_v1_1 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrphy_update_ctrl_v1_1.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_phy_io_v1_1.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_phy_io_v1_1.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_phy_io_v1_1.v(line number: 17)] Analyzing module ipsl_hmic_h_phy_io_v1_1 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_phy_io_v1_1.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_phy_top_v1_1.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_phy_top_v1_1.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_phy_top_v1_1.v(line number: 17)] Analyzing module ipsl_hmic_h_phy_top_v1_1 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_phy_top_v1_1.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 21)] Analyzing module ddr3 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 21)] Analyzing module pll_50_400_v1_1 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/rgb2ycbcr.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/rgb2ycbcr.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/rgb2ycbcr.v(line number: 18)] Analyzing module rgb2ycbcr (library work)
W: Verilog-2006: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/rgb2ycbcr.v(line number: 40)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/rgb2ycbcr.v(line number: 41)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/rgb2ycbcr.v(line number: 42)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/rgb2ycbcr.v(line number: 43)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/rgb2ycbcr.v(line number: 44)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/rgb2ycbcr.v(line number: 45)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/rgb2ycbcr.v(line number: 46)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/rgb2ycbcr.v(line number: 47)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/rgb2ycbcr.v(line number: 48)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/rgb2ycbcr.v(line number: 49)] Ansi_parameter force parameter in body to localparam
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/rgb2ycbcr.v(line number: 203)] System task enable $fdisplay ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/rgb2ycbcr.v(line number: 204)] System task enable $fdisplay ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/rgb2ycbcr.v(line number: 205)] System task enable $fdisplay ignored for synthesis
W: Verilog-2010: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/rgb2ycbcr.v(line number: 194)] Ignoring initial statements expect force and memory $readmemh/$readmemb initialization statements
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/rgb2ycbcr.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/threshold_binary.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/threshold_binary.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/threshold_binary.v(line number: 3)] Analyzing module threshold_binary (library work)
W: Verilog-2006: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/threshold_binary.v(line number: 105)] Ansi_parameter force parameter in body to localparam
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/threshold_binary.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/ISP.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/ISP.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/ISP.v(line number: 10)] Analyzing module ISP (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/ISP.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/ram.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/ram.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/ram.v(line number: 1)] Analyzing module ram (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/ram.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/binarization.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/binarization.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/binarization.v(line number: 5)] Analyzing module binarization (library work)
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/binarization.v(line number: 98)] System task enable $fdisplay ignored for synthesis
W: Verilog-2010: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/binarization.v(line number: 91)] Ignoring initial statements expect force and memory $readmemh/$readmemb initialization statements
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/binarization.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/Type_Distgsh.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/Type_Distgsh.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/Type_Distgsh.v(line number: 3)] Analyzing module Type_Distgsh_single (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/Type_Distgsh.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/Vertical_Projection_sum.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/Vertical_Projection_sum.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/Vertical_Projection_sum.v(line number: 3)] Analyzing module Vertical_Projection_sum (library work)
W: Verilog-2006: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/Vertical_Projection_sum.v(line number: 34)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/Vertical_Projection_sum.v(line number: 35)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/Vertical_Projection_sum.v(line number: 36)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/Vertical_Projection_sum.v(line number: 37)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/Vertical_Projection_sum.v(line number: 38)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/Vertical_Projection_sum.v(line number: 457)] Ansi_parameter force parameter in body to localparam
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/Vertical_Projection_sum.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/dpram.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/dpram.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/dpram.v(line number: 1)] Analyzing module dpram (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/dpram.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/line_shift.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/line_shift.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/line_shift.v(line number: 1)] Analyzing module line_shift (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/line_shift.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/Matrix_3X3.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/Matrix_3X3.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/Matrix_3X3.v(line number: 1)] Analyzing module Matrix_3X3 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/Matrix_3X3.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/VIP_Bit_Dilation_Detector.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/VIP_Bit_Dilation_Detector.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/VIP_Bit_Dilation_Detector.v(line number: 15)] Analyzing module VIP_Bit_Dilation_Detector (library work)
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/VIP_Bit_Dilation_Detector.v(line number: 159)] System task enable $fdisplay ignored for synthesis
W: Verilog-2010: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/VIP_Bit_Dilation_Detector.v(line number: 152)] Ignoring initial statements expect force and memory $readmemh/$readmemb initialization statements
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/VIP_Bit_Dilation_Detector.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/VIP_Bit_Erosion_Detector.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/VIP_Bit_Erosion_Detector.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/VIP_Bit_Erosion_Detector.v(line number: 34)] Analyzing module VIP_Bit_Erosion_Detector (library work)
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/VIP_Bit_Erosion_Detector.v(line number: 179)] System task enable $fdisplay ignored for synthesis
W: Verilog-2010: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/VIP_Bit_Erosion_Detector.v(line number: 172)] Ignoring initial statements expect force and memory $readmemh/$readmemb initialization statements
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/VIP_Bit_Erosion_Detector.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/uart/uart_ctrl.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/uart/uart_ctrl.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/uart/uart_ctrl.v(line number: 11)] Analyzing module uart_ctrl (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/uart/uart_ctrl.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/uart/uart_rx.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/uart/uart_rx.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/uart/uart_rx.v(line number: 29)] Analyzing module uart_rx (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/uart/uart_rx.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/uart/uart_tx.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/uart/uart_tx.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/uart/uart_tx.v(line number: 29)] Analyzing module uart_tx (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/uart/uart_tx.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/div_rill2.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/div_rill2.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/div_rill2.v(line number: 2)] Analyzing module div_rill2 (library work)
W: Verilog-2006: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/div_rill2.v(line number: 13)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/div_rill2.v(line number: 19)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/div_rill2.v(line number: 20)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/div_rill2.v(line number: 21)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/div_rill2.v(line number: 22)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/div_rill2.v(line number: 23)] Ansi_parameter force parameter in body to localparam
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/div_rill2.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/display.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/display.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/display.v(line number: 2)] Analyzing module display (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/display.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/HVCOUNT.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/HVCOUNT.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/HVCOUNT.v(line number: 3)] Analyzing module HVcount (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/HVCOUNT.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/key/ax_debounce.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/key/ax_debounce.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/key/ax_debounce.v(line number: 31)] Analyzing module ax_debounce (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/key/ax_debounce.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/key/count_m10.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/key/count_m10.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/key/count_m10.v(line number: 30)] Analyzing module count_m10 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/key/count_m10.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/key/key_debounce.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/key/key_debounce.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/key/key_debounce.v(line number: 9)] Analyzing module key_debounce (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/key/key_debounce.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/FIFO56x32.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/FIFO56x32.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/FIFO56x32.v(line number: 20)] Analyzing module FIFO56x32 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/FIFO56x32.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/rtl/ipm_distributed_sdpram_v1_2_FIFO56x32.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/rtl/ipm_distributed_sdpram_v1_2_FIFO56x32.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/rtl/ipm_distributed_sdpram_v1_2_FIFO56x32.v(line number: 22)] Analyzing module ipm_distributed_sdpram_v1_2_FIFO56x32 (library work)
W: Verilog-2010: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/rtl/ipm_distributed_sdpram_v1_2_FIFO56x32.v(line number: 59)] Ignoring initial statements expect force and memory $readmemh/$readmemb initialization statements
W: Verilog-2010: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/rtl/ipm_distributed_sdpram_v1_2_FIFO56x32.v(line number: 64)] Ignoring initial statements expect force and memory $readmemh/$readmemb initialization statements
W: Verilog-2010: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/rtl/ipm_distributed_sdpram_v1_2_FIFO56x32.v(line number: 70)] Ignoring initial statements expect force and memory $readmemh/$readmemb initialization statements
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/rtl/ipm_distributed_sdpram_v1_2_FIFO56x32.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/rtl/ipm_distributed_fifo_v1_2_FIFO56x32.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/rtl/ipm_distributed_fifo_v1_2_FIFO56x32.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/rtl/ipm_distributed_fifo_v1_2_FIFO56x32.v(line number: 21)] Analyzing module ipm_distributed_fifo_v1_2_FIFO56x32 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/rtl/ipm_distributed_fifo_v1_2_FIFO56x32.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_fifo_v1_5_afifo_16i_64o_512.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_fifo_v1_5_afifo_16i_64o_512.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_fifo_v1_5_afifo_16i_64o_512.v(line number: 25)] Analyzing module ipml_fifo_v1_5_afifo_16i_64o_512 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_fifo_v1_5_afifo_16i_64o_512.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_fifo_v1_5_afifo_64i_16o_128.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_fifo_v1_5_afifo_64i_16o_128.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_fifo_v1_5_afifo_64i_16o_128.v(line number: 25)] Analyzing module ipml_fifo_v1_5_afifo_64i_16o_128 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_fifo_v1_5_afifo_64i_16o_128.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/afifo_64i_16o_128.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/afifo_64i_16o_128.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/afifo_64i_16o_128.v(line number: 18)] Analyzing module afifo_64i_16o_128 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/afifo_64i_16o_128.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/afifo_16i_64o_512.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/afifo_16i_64o_512.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/afifo_16i_64o_512.v(line number: 18)] Analyzing module afifo_16i_64o_512 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/afifo_16i_64o_512.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 20)] Analyzing module video_pll (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/rtl/ipm_distributed_fifo_ctr_v1_0.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/rtl/ipm_distributed_fifo_ctr_v1_0.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/rtl/ipm_distributed_fifo_ctr_v1_0.v(line number: 18)] Analyzing module ipm_distributed_fifo_ctr_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/rtl/ipm_distributed_fifo_ctr_v1_0.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_fifo_ctrl_v1_3.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_fifo_ctrl_v1_3.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_fifo_ctrl_v1_3.v(line number: 21)] Analyzing module ipml_fifo_ctrl_v1_3 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_fifo_ctrl_v1_3.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 20)] Analyzing module ipml_sdpram_v1_5_afifo_16i_64o_512 (library work)
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 308)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 309)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 312)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 316)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 320)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 324)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 328)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 329)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 332)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 333)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 336)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 337)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 340)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 341)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 344)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 345)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 348)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 349)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 352)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 353)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 356)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 357)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 360)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 361)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 364)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 365)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 368)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 369)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 373)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 374)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 377)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 378)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 382)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 383)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 386)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 387)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 390)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 391)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 394)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 395)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 398)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 399)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 404)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 405)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 408)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 409)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 414)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 415)] System task enable $finish ignored for synthesis
W: Verilog-2010: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 306)] Ignoring initial statements expect force and memory $readmemh/$readmemb initialization statements
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v successfully.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v
I: Verilog-0001: Analyzing file D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v
I: Verilog-0002: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 20)] Analyzing module ipml_sdpram_v1_5_afifo_64i_16o_128 (library work)
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 308)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 309)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 312)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 316)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 320)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 324)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 328)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 329)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 332)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 333)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 336)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 337)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 340)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 341)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 344)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 345)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 348)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 349)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 352)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 353)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 356)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 357)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 360)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 361)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 364)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 365)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 368)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 369)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 373)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 374)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 377)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 378)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 382)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 383)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 386)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 387)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 390)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 391)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 394)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 395)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 398)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 399)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 404)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 405)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 408)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 409)] System task enable $finish ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 414)] System task enable $display ignored for synthesis
W: Verilog-2008: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 415)] System task enable $finish ignored for synthesis
W: Verilog-2010: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 306)] Ignoring initial statements expect force and memory $readmemh/$readmemb initialization statements
Parsing done.
Executing : .rtl_analyze -include_path {D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi} D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v successfully.
Start rtl-elaborate.
I: Module "top" is set as top module.
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 30)] Elaborating module top
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/library/operator/gtp_lib.v(line number: 395)] Elaborating module GTP_CLKBUFG
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 20)] Elaborating module video_pll
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/library/operator/gtp_lib.v(line number: 19818)] Elaborating module GTP_PLL_E1
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 124)] Net clkfb in module video_pll does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 127)] Net pfden in module video_pll does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 128)] Net clkout0_gate in module video_pll does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 129)] Net clkout0_2pad_gate in module video_pll does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 130)] Net clkout1_gate in module video_pll does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 131)] Net clkout2_gate in module video_pll does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 132)] Net clkout3_gate in module video_pll does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 133)] Net clkout4_gate in module video_pll does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 134)] Net clkout5_gate in module video_pll does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 135)] Net dyn_idiv in module video_pll does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 136)] Net dyn_odiv0 in module video_pll does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 137)] Net dyn_odiv1 in module video_pll does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 138)] Net dyn_odiv2 in module video_pll does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 139)] Net dyn_odiv3 in module video_pll does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 140)] Net dyn_odiv4 in module video_pll does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 141)] Net dyn_fdiv in module video_pll does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 142)] Net dyn_duty0 in module video_pll does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 143)] Net dyn_duty1 in module video_pll does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 144)] Net dyn_duty2 in module video_pll does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 145)] Net dyn_duty3 in module video_pll does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 146)] Net dyn_duty4 in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 147)] Net dyn_phase0[0] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 147)] Net dyn_phase0[1] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 147)] Net dyn_phase0[2] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 147)] Net dyn_phase0[3] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 147)] Net dyn_phase0[4] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 147)] Net dyn_phase0[5] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 147)] Net dyn_phase0[6] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 147)] Net dyn_phase0[7] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 147)] Net dyn_phase0[8] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 147)] Net dyn_phase0[9] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 147)] Net dyn_phase0[10] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 147)] Net dyn_phase0[11] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 147)] Net dyn_phase0[12] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 148)] Net dyn_phase1[0] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 148)] Net dyn_phase1[1] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 148)] Net dyn_phase1[2] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 148)] Net dyn_phase1[3] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 148)] Net dyn_phase1[4] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 148)] Net dyn_phase1[5] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 148)] Net dyn_phase1[6] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 148)] Net dyn_phase1[7] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 148)] Net dyn_phase1[8] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 148)] Net dyn_phase1[9] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 148)] Net dyn_phase1[10] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 148)] Net dyn_phase1[11] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 148)] Net dyn_phase1[12] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 149)] Net dyn_phase2[0] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 149)] Net dyn_phase2[1] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 149)] Net dyn_phase2[2] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 149)] Net dyn_phase2[3] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 149)] Net dyn_phase2[4] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 149)] Net dyn_phase2[5] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 149)] Net dyn_phase2[6] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 149)] Net dyn_phase2[7] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 149)] Net dyn_phase2[8] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 149)] Net dyn_phase2[9] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 149)] Net dyn_phase2[10] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 149)] Net dyn_phase2[11] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 149)] Net dyn_phase2[12] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 150)] Net dyn_phase3[0] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 150)] Net dyn_phase3[1] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 150)] Net dyn_phase3[2] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 150)] Net dyn_phase3[3] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 150)] Net dyn_phase3[4] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 150)] Net dyn_phase3[5] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 150)] Net dyn_phase3[6] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 150)] Net dyn_phase3[7] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 150)] Net dyn_phase3[8] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 150)] Net dyn_phase3[9] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 150)] Net dyn_phase3[10] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 150)] Net dyn_phase3[11] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 150)] Net dyn_phase3[12] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 151)] Net dyn_phase4[0] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 151)] Net dyn_phase4[1] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 151)] Net dyn_phase4[2] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 151)] Net dyn_phase4[3] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 151)] Net dyn_phase4[4] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 151)] Net dyn_phase4[5] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 151)] Net dyn_phase4[6] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 151)] Net dyn_phase4[7] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 151)] Net dyn_phase4[8] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 151)] Net dyn_phase4[9] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 151)] Net dyn_phase4[10] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 151)] Net dyn_phase4[11] in module video_pll does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 151)] Net dyn_phase4[12] in module video_pll does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 155)] Net icp_base in module video_pll does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 156)] Net icp_sel in module video_pll does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 157)] Net lpfres_sel in module video_pll does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 158)] Net cripple_sel in module video_pll does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 159)] Net phase_sel in module video_pll does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 160)] Net phase_dir in module video_pll does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 161)] Net phase_step_n in module video_pll does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 162)] Net load_phase in module video_pll does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/video_pll/video_pll.v(line number: 163)] Net dyn_mdiv in module video_pll does not have a driver, tie it to 0
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/ISP.v(line number: 10)] Elaborating module ISP
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/rgb2ycbcr.v(line number: 18)] Elaborating module rgb2ycbcr
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/rgb2ycbcr.v(line number: 76)] Net result_y_18b in module rgb2ycbcr does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/rgb2ycbcr.v(line number: 77)] Net result_cb_18b in module rgb2ycbcr does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/rgb2ycbcr.v(line number: 78)] Net result_cr_18b in module rgb2ycbcr does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/rgb2ycbcr.v(line number: 191)] Net log.rgb2ycbcr_Y_file in module rgb2ycbcr does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/rgb2ycbcr.v(line number: 192)] Net log.rgb2ycbcr_Cr_file in module rgb2ycbcr does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/rgb2ycbcr.v(line number: 193)] Net log.rgb2ycbcr_Cb_file in module rgb2ycbcr does not have a driver, tie it to 0
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/binarization.v(line number: 5)] Elaborating module binarization
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/binarization.v(line number: 89)] Net log.BINARIZATION_file in module binarization does not have a driver, tie it to 0
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/VIP_Bit_Dilation_Detector.v(line number: 15)] Elaborating module VIP_Bit_Dilation_Detector
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/Matrix_3X3.v(line number: 1)] Elaborating module Matrix_3X3
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/line_shift.v(line number: 1)] Elaborating module line_shift
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/dpram.v(line number: 1)] Elaborating module dpram
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/dpram.v(line number: 1)] Elaborating module dpram
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/line_shift.v(line number: 16)] Net ram_rd_addr_d2 in module line_shift does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/line_shift.v(line number: 17)] Net ram_rd_addr_d3 in module line_shift does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/VIP_Bit_Dilation_Detector.v(line number: 150)] Net log.Dilation_file in module VIP_Bit_Dilation_Detector does not have a driver, tie it to 0
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/VIP_Bit_Erosion_Detector.v(line number: 34)] Elaborating module VIP_Bit_Erosion_Detector
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/Matrix_3X3.v(line number: 1)] Elaborating module Matrix_3X3
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/VIP_Bit_Erosion_Detector.v(line number: 170)] Net log.Erosion_file in module VIP_Bit_Erosion_Detector does not have a driver, tie it to 0
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/Vertical_Projection_sum.v(line number: 3)] Elaborating module Vertical_Projection_sum
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/div_rill2.v(line number: 2)] Elaborating module div_rill2
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/ram.v(line number: 1)] Elaborating module ram
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/ram.v(line number: 1)] Elaborating module ram
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/threshold_binary.v(line number: 3)] Elaborating module threshold_binary
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/threshold_binary.v(line number: 126)] Net r_enable_b in module threshold_binary does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/threshold_binary.v(line number: 168)] Net en0_b in module threshold_binary does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/threshold_binary.v(line number: 169)] Net en1_b in module threshold_binary does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/threshold_binary.v(line number: 170)] Net en2_b in module threshold_binary does not have a driver, tie it to 0
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/VIP_Bit_Dilation_Detector.v(line number: 15)] Elaborating module VIP_Bit_Dilation_Detector
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/Matrix_3X3.v(line number: 1)] Elaborating module Matrix_3X3
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/VIP_Bit_Dilation_Detector.v(line number: 150)] Net log.Dilation_file in module VIP_Bit_Dilation_Detector_1 does not have a driver, tie it to 0
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/VIP_Bit_Erosion_Detector.v(line number: 34)] Elaborating module VIP_Bit_Erosion_Detector
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/Matrix_3X3.v(line number: 1)] Elaborating module Matrix_3X3
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/VIP_Bit_Erosion_Detector.v(line number: 170)] Net log.Erosion_file in module VIP_Bit_Erosion_Detector_1 does not have a driver, tie it to 0
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/VIP_Bit_Dilation_Detector.v(line number: 15)] Elaborating module VIP_Bit_Dilation_Detector
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/Matrix_3X3.v(line number: 1)] Elaborating module Matrix_3X3
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/VIP_Bit_Dilation_Detector.v(line number: 150)] Net log.Dilation_file in module VIP_Bit_Dilation_Detector_2 does not have a driver, tie it to 0
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/VIP_Bit_Erosion_Detector.v(line number: 34)] Elaborating module VIP_Bit_Erosion_Detector
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/Matrix_3X3.v(line number: 1)] Elaborating module Matrix_3X3
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/VIP_Bit_Erosion_Detector.v(line number: 170)] Net log.Erosion_file in module VIP_Bit_Erosion_Detector_2 does not have a driver, tie it to 0
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/VIP_Bit_Dilation_Detector.v(line number: 15)] Elaborating module VIP_Bit_Dilation_Detector
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/Matrix_3X3.v(line number: 1)] Elaborating module Matrix_3X3
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/VIP_Bit_Dilation_Detector.v(line number: 150)] Net log.Dilation_file in module VIP_Bit_Dilation_Detector_3 does not have a driver, tie it to 0
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/VIP_Bit_Erosion_Detector.v(line number: 34)] Elaborating module VIP_Bit_Erosion_Detector
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/Matrix_3X3.v(line number: 1)] Elaborating module Matrix_3X3
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/VIP_Bit_Erosion_Detector.v(line number: 170)] Net log.Erosion_file in module VIP_Bit_Erosion_Detector_3 does not have a driver, tie it to 0
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/VIP_Bit_Dilation_Detector.v(line number: 15)] Elaborating module VIP_Bit_Dilation_Detector
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/Matrix_3X3.v(line number: 1)] Elaborating module Matrix_3X3
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/VIP_Bit_Dilation_Detector.v(line number: 150)] Net log.Dilation_file in module VIP_Bit_Dilation_Detector_4 does not have a driver, tie it to 0
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/VIP_Bit_Erosion_Detector.v(line number: 34)] Elaborating module VIP_Bit_Erosion_Detector
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/Matrix_3X3.v(line number: 1)] Elaborating module Matrix_3X3
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/Erosion/VIP_Bit_Erosion_Detector.v(line number: 170)] Net log.Erosion_file in module VIP_Bit_Erosion_Detector_4 does not have a driver, tie it to 0
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/Vertical_Projection_sum.v(line number: 3)] Elaborating module Vertical_Projection_sum
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/Vertical_Projection_sum.v(line number: 3)] Elaborating module Vertical_Projection_sum
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/Vertical_Projection_sum.v(line number: 3)] Elaborating module Vertical_Projection_sum
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/Vertical_Projection_sum.v(line number: 3)] Elaborating module Vertical_Projection_sum
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/Type_Distgsh.v(line number: 3)] Elaborating module Type_Distgsh_single
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/HVCOUNT.v(line number: 3)] Elaborating module HVcount
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/key/key_debounce.v(line number: 9)] Elaborating module key_debounce
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/key/ax_debounce.v(line number: 31)] Elaborating module ax_debounce
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/key/count_m10.v(line number: 30)] Elaborating module count_m10
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/display.v(line number: 2)] Elaborating module display
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/ISP.v(line number: 154)] Give initial value 0 for the no drive pin i_de0 in module instance
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/ISP.v(line number: 99)] Net HV_dout_r in module ISP does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/ISP.v(line number: 100)] Net HV_dout_g in module ISP does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/ISP.v(line number: 101)] Net HV_dout_b in module ISP does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/ISP.v(line number: 280)] Net o_binary_1 in module ISP does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/ISP.v(line number: 953)] Net led_r in module ISP does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/ISP.v(line number: 954)] Net led_r1[0] in module ISP does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/ISP.v(line number: 954)] Net led_r1[1] in module ISP does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/ISP.v(line number: 954)] Net led_r1[2] in module ISP does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/ISP.v(line number: 954)] Net led_r1[3] in module ISP does not have a driver, tie it to 0
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/uart/uart_ctrl.v(line number: 11)] Elaborating module uart_ctrl
W: Verilog-2032: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/uart/uart_ctrl.v(line number: 474)] Assigned initial value to variable type9 that is unassigned but has initial value
W: Verilog-2032: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/uart/uart_ctrl.v(line number: 475)] Assigned initial value to variable type10 that is unassigned but has initial value
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/FIFO56x32.v(line number: 20)] Elaborating module FIFO56x32
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/rtl/ipm_distributed_fifo_v1_2_FIFO56x32.v(line number: 21)] Elaborating module ipm_distributed_fifo_v1_2_FIFO56x32
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/rtl/ipm_distributed_sdpram_v1_2_FIFO56x32.v(line number: 22)] Elaborating module ipm_distributed_sdpram_v1_2_FIFO56x32
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/rtl/ipm_distributed_sdpram_v1_2_FIFO56x32.v(line number: 56)] Net i in module ipm_distributed_sdpram_v1_2_FIFO56x32 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/rtl/ipm_distributed_sdpram_v1_2_FIFO56x32.v(line number: 56)] Net j in module ipm_distributed_sdpram_v1_2_FIFO56x32 does not have a driver, tie it to 0
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/rtl/ipm_distributed_fifo_ctr_v1_0.v(line number: 18)] Elaborating module ipm_distributed_fifo_ctr_v1_0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/rtl/ipm_distributed_fifo_ctr_v1_0.v(line number: 46)] Net wrptr1 in module ipm_distributed_fifo_ctr_v1_0 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/rtl/ipm_distributed_fifo_ctr_v1_0.v(line number: 48)] Net wbin in module ipm_distributed_fifo_ctr_v1_0 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/rtl/ipm_distributed_fifo_ctr_v1_0.v(line number: 57)] Net rwptr1 in module ipm_distributed_fifo_ctr_v1_0 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/rtl/ipm_distributed_fifo_ctr_v1_0.v(line number: 59)] Net rbin in module ipm_distributed_fifo_ctr_v1_0 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/rtl/ipm_distributed_fifo_ctr_v1_0.v(line number: 67)] Net asyn_wfull in module ipm_distributed_fifo_ctr_v1_0 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/rtl/ipm_distributed_fifo_ctr_v1_0.v(line number: 68)] Net asyn_almost_full in module ipm_distributed_fifo_ctr_v1_0 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/rtl/ipm_distributed_fifo_ctr_v1_0.v(line number: 69)] Net asyn_rempty in module ipm_distributed_fifo_ctr_v1_0 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/rtl/ipm_distributed_fifo_ctr_v1_0.v(line number: 70)] Net asyn_almost_empty in module ipm_distributed_fifo_ctr_v1_0 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/rtl/ipm_distributed_fifo_ctr_v1_0.v(line number: 81)] Net ASYN_CTRL.i in module ipm_distributed_fifo_ctr_v1_0 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/FIFO56x32/rtl/ipm_distributed_fifo_ctr_v1_0.v(line number: 131)] Net ASYN_CTRL.j in module ipm_distributed_fifo_ctr_v1_0 does not have a driver, tie it to 0
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/uart/uart_rx.v(line number: 29)] Elaborating module uart_rx
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/uart/uart_tx.v(line number: 29)] Elaborating module uart_tx
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/uart/uart_ctrl.v(line number: 64)] Net tx_str in module uart_ctrl does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/uart/uart_ctrl.v(line number: 67)] Net tx_cnt in module uart_ctrl does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/uart/uart_ctrl.v(line number: 322)] Net blue in module uart_ctrl does not have a driver, tie it to 0
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/dvi_tx/dvi_encoder.v(line number: 2)] Elaborating module dvi_encoder
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/dvi_tx/encode.v(line number: 46)] Elaborating module encode
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/dvi_tx/encode.v(line number: 46)] Elaborating module encode
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/dvi_tx/encode.v(line number: 46)] Elaborating module encode
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/dvi_tx/serdes_4b_10to1.v(line number: 3)] Elaborating module serdes_4b_10to1
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/library/operator/gtp_lib.v(line number: 18517)] Elaborating module GTP_OSERDES
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/library/operator/gtp_lib.v(line number: 18630)] Elaborating module GTP_OUTBUFT
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/i2c_master/i2c_config.v(line number: 30)] Elaborating module i2c_config
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/i2c_master/i2c_master_top.v(line number: 30)] Elaborating module i2c_master_top
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/i2c_master/i2c_master_byte_ctrl.v(line number: 75)] Elaborating module i2c_master_byte_ctrl
W: Sdm-2008: The attribute named enum_state is not legal, then it has no effect, ignore its value.
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/i2c_master/i2c_master_bit_ctrl.v(line number: 143)] Elaborating module i2c_master_bit_ctrl
W: Sdm-2008: The attribute named enum_state is not legal, then it has no effect, ignore its value.
W: Directive full_case is effective
W: Directive full_case is effective
W: Verilog-2036: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/i2c_master/i2c_config.v(line number: 130)] Net i2c_read_req connected to input port of module instance has no driver, tie it to 0
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/lut_ov5640_rgb565_1024_768.v(line number: 30)] Elaborating module lut_ov5640_rgb565_1024_768
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/cmos_8_16bit.v(line number: 30)] Elaborating module cmos_8_16bit
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/cmos_write_req_gen.v(line number: 30)] Elaborating module cmos_write_req_gen
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/video_timing_data.v(line number: 30)] Elaborating module video_timing_data
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/color_bar.v(line number: 33)] Elaborating module color_bar
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/color_bar.v(line number: 174)] Net active_y in module color_bar does not have a driver, tie it to 0
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/frame_read_write.v(line number: 31)] Elaborating module frame_read_write
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/afifo_16i_64o_512.v(line number: 18)] Elaborating module afifo_16i_64o_512
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_fifo_v1_5_afifo_16i_64o_512.v(line number: 25)] Elaborating module ipml_fifo_v1_5_afifo_16i_64o_512
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 20)] Elaborating module ipml_sdpram_v1_5_afifo_16i_64o_512
W: Verilog-2039: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 469)] Repeat multiplier in concatenation evaluates to 0
W: Verilog-2038: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 481)] Case condition never applies
W: Verilog-2038: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 482)] Case condition never applies
W: Verilog-2038: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 483)] Case condition never applies
W: Verilog-2038: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 481)] Case condition never applies
W: Verilog-2038: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 482)] Case condition never applies
W: Verilog-2038: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 483)] Case condition never applies
W: Verilog-2038: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 676)] Case condition never applies
W: Verilog-2038: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 677)] Case condition never applies
W: Verilog-2038: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 678)] Case condition never applies
W: Verilog-2038: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 679)] Case condition never applies
W: Verilog-2038: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 679)] Case condition never applies
W: Verilog-2038: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 680)] Case condition never applies
W: Verilog-2038: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 680)] Case condition never applies
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/library/operator/gtp_lib.v(line number: 1954)] Elaborating module GTP_DRM18K
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 571)] Net gen_j_wd in module ipml_sdpram_v1_5_afifo_16i_64o_512 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 767)] Net DA_bus[8] in module ipml_sdpram_v1_5_afifo_16i_64o_512 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 767)] Net DA_bus[9] in module ipml_sdpram_v1_5_afifo_16i_64o_512 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 767)] Net DA_bus[10] in module ipml_sdpram_v1_5_afifo_16i_64o_512 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 767)] Net DA_bus[11] in module ipml_sdpram_v1_5_afifo_16i_64o_512 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 767)] Net DA_bus[12] in module ipml_sdpram_v1_5_afifo_16i_64o_512 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 767)] Net DA_bus[13] in module ipml_sdpram_v1_5_afifo_16i_64o_512 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 767)] Net DA_bus[14] in module ipml_sdpram_v1_5_afifo_16i_64o_512 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 767)] Net DA_bus[15] in module ipml_sdpram_v1_5_afifo_16i_64o_512 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 767)] Net DA_bus[16] in module ipml_sdpram_v1_5_afifo_16i_64o_512 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 767)] Net DA_bus[17] in module ipml_sdpram_v1_5_afifo_16i_64o_512 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 767)] Net DA_bus[26] in module ipml_sdpram_v1_5_afifo_16i_64o_512 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 767)] Net DA_bus[27] in module ipml_sdpram_v1_5_afifo_16i_64o_512 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 767)] Net DA_bus[28] in module ipml_sdpram_v1_5_afifo_16i_64o_512 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 767)] Net DA_bus[29] in module ipml_sdpram_v1_5_afifo_16i_64o_512 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 767)] Net DA_bus[30] in module ipml_sdpram_v1_5_afifo_16i_64o_512 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 767)] Net DA_bus[31] in module ipml_sdpram_v1_5_afifo_16i_64o_512 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 767)] Net DA_bus[32] in module ipml_sdpram_v1_5_afifo_16i_64o_512 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 767)] Net DA_bus[33] in module ipml_sdpram_v1_5_afifo_16i_64o_512 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 767)] Net DA_bus[34] in module ipml_sdpram_v1_5_afifo_16i_64o_512 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 767)] Net DA_bus[35] in module ipml_sdpram_v1_5_afifo_16i_64o_512 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 768)] Net DB_bus[8] in module ipml_sdpram_v1_5_afifo_16i_64o_512 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 768)] Net DB_bus[17] in module ipml_sdpram_v1_5_afifo_16i_64o_512 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 768)] Net DB_bus[26] in module ipml_sdpram_v1_5_afifo_16i_64o_512 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 768)] Net DB_bus[35] in module ipml_sdpram_v1_5_afifo_16i_64o_512 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_sdpram_v1_5_afifo_16i_64o_512.v(line number: 1084)] Net cs_rd in module ipml_sdpram_v1_5_afifo_16i_64o_512 does not have a driver, tie it to 0
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_fifo_ctrl_v1_3.v(line number: 21)] Elaborating module ipml_fifo_ctrl_v1_3
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_fifo_ctrl_v1_3.v(line number: 73)] Net asyn_almost_full in module ipml_fifo_ctrl_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_fifo_ctrl_v1_3.v(line number: 75)] Net asyn_almost_empty in module ipml_fifo_ctrl_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_fifo_ctrl_v1_3.v(line number: 76)] Net syn_wfull in module ipml_fifo_ctrl_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_fifo_ctrl_v1_3.v(line number: 77)] Net syn_almost_full in module ipml_fifo_ctrl_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_fifo_ctrl_v1_3.v(line number: 78)] Net syn_rempty in module ipml_fifo_ctrl_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_fifo_ctrl_v1_3.v(line number: 79)] Net syn_almost_empty in module ipml_fifo_ctrl_v1_3 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/afifo_16i_64o_512.v(line number: 120)] Net wr_byte_en in module afifo_16i_64o_512 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/afifo_16i_64o_512.v(line number: 128)] Net rd_oce in module afifo_16i_64o_512 does not have a driver, tie it to 0
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/frame_fifo_write.v(line number: 31)] Elaborating module frame_fifo_write
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/afifo_64i_16o_128.v(line number: 18)] Elaborating module afifo_64i_16o_128
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_fifo_v1_5_afifo_64i_16o_128.v(line number: 25)] Elaborating module ipml_fifo_v1_5_afifo_64i_16o_128
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 20)] Elaborating module ipml_sdpram_v1_5_afifo_64i_16o_128
W: Verilog-2039: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 469)] Repeat multiplier in concatenation evaluates to 0
W: Verilog-2038: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 481)] Case condition never applies
W: Verilog-2038: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 482)] Case condition never applies
W: Verilog-2038: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 483)] Case condition never applies
W: Verilog-2038: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 484)] Case condition never applies
W: Verilog-2038: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 484)] Case condition never applies
W: Verilog-2038: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 485)] Case condition never applies
W: Verilog-2038: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 485)] Case condition never applies
W: Verilog-2038: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 481)] Case condition never applies
W: Verilog-2038: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 482)] Case condition never applies
W: Verilog-2038: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 483)] Case condition never applies
W: Verilog-2038: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 484)] Case condition never applies
W: Verilog-2038: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 484)] Case condition never applies
W: Verilog-2038: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 485)] Case condition never applies
W: Verilog-2038: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 485)] Case condition never applies
W: Verilog-2038: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 676)] Case condition never applies
W: Verilog-2038: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 677)] Case condition never applies
W: Verilog-2038: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 678)] Case condition never applies
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 767)] Net DA_bus[8] in module ipml_sdpram_v1_5_afifo_64i_16o_128 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 767)] Net DA_bus[17] in module ipml_sdpram_v1_5_afifo_64i_16o_128 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 767)] Net DA_bus[26] in module ipml_sdpram_v1_5_afifo_64i_16o_128 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 767)] Net DA_bus[35] in module ipml_sdpram_v1_5_afifo_64i_16o_128 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 768)] Net DB_bus[8] in module ipml_sdpram_v1_5_afifo_64i_16o_128 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 768)] Net DB_bus[17] in module ipml_sdpram_v1_5_afifo_64i_16o_128 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 768)] Net DB_bus[26] in module ipml_sdpram_v1_5_afifo_64i_16o_128 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 768)] Net DB_bus[35] in module ipml_sdpram_v1_5_afifo_64i_16o_128 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 1084)] Net cs_rd in module ipml_sdpram_v1_5_afifo_64i_16o_128 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 1098)] Net gen_i_rd in module ipml_sdpram_v1_5_afifo_64i_16o_128 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/rtl/ipml_sdpram_v1_5_afifo_64i_16o_128.v(line number: 1098)] Net gen_j_rd in module ipml_sdpram_v1_5_afifo_64i_16o_128 does not have a driver, tie it to 0
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_fifo_ctrl_v1_3.v(line number: 21)] Elaborating module ipml_fifo_ctrl_v1_3
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_fifo_ctrl_v1_3.v(line number: 73)] Net asyn_almost_full in module ipml_fifo_ctrl_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_fifo_ctrl_v1_3.v(line number: 75)] Net asyn_almost_empty in module ipml_fifo_ctrl_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_fifo_ctrl_v1_3.v(line number: 76)] Net syn_wfull in module ipml_fifo_ctrl_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_fifo_ctrl_v1_3.v(line number: 77)] Net syn_almost_full in module ipml_fifo_ctrl_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_fifo_ctrl_v1_3.v(line number: 78)] Net syn_rempty in module ipml_fifo_ctrl_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_16i_64o_512/rtl/ipml_fifo_ctrl_v1_3.v(line number: 79)] Net syn_almost_empty in module ipml_fifo_ctrl_v1_4 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/afifo_64i_16o_128.v(line number: 120)] Net wr_byte_en in module afifo_64i_16o_128 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/ipcore/afifo_64i_16o_128/afifo_64i_16o_128.v(line number: 128)] Net rd_oce in module afifo_64i_16o_128 does not have a driver, tie it to 0
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/frame_fifo_read.v(line number: 31)] Elaborating module frame_fifo_read
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/frame_read_write.v(line number: 81)] Net wrusedw[9] in module frame_read_write does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/frame_read_write.v(line number: 81)] Net wrusedw[10] in module frame_read_write does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/frame_read_write.v(line number: 81)] Net wrusedw[11] in module frame_read_write does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/frame_read_write.v(line number: 81)] Net wrusedw[12] in module frame_read_write does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/frame_read_write.v(line number: 81)] Net wrusedw[13] in module frame_read_write does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/frame_read_write.v(line number: 81)] Net wrusedw[14] in module frame_read_write does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/frame_read_write.v(line number: 81)] Net wrusedw[15] in module frame_read_write does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/frame_read_write.v(line number: 82)] Net rdusedw[9] in module frame_read_write does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/frame_read_write.v(line number: 82)] Net rdusedw[10] in module frame_read_write does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/frame_read_write.v(line number: 82)] Net rdusedw[11] in module frame_read_write does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/frame_read_write.v(line number: 82)] Net rdusedw[12] in module frame_read_write does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/frame_read_write.v(line number: 82)] Net rdusedw[13] in module frame_read_write does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/frame_read_write.v(line number: 82)] Net rdusedw[14] in module frame_read_write does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/frame_read_write.v(line number: 82)] Net rdusedw[15] in module frame_read_write does not have a driver, tie it to 0
W: Verilog-2019: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 414)] Width mismatch between port read_addr_0 and signal bound to it for instantiated module frame_read_write
W: Verilog-2019: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 414)] Width mismatch between port read_addr_1 and signal bound to it for instantiated module frame_read_write
W: Verilog-2019: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 414)] Width mismatch between port read_addr_2 and signal bound to it for instantiated module frame_read_write
W: Verilog-2019: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 414)] Width mismatch between port read_addr_3 and signal bound to it for instantiated module frame_read_write
W: Verilog-2019: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 414)] Width mismatch between port read_len and signal bound to it for instantiated module frame_read_write
W: Verilog-2019: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 414)] Width mismatch between port write_addr_0 and signal bound to it for instantiated module frame_read_write
W: Verilog-2019: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 414)] Width mismatch between port write_addr_1 and signal bound to it for instantiated module frame_read_write
W: Verilog-2019: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 414)] Width mismatch between port write_addr_2 and signal bound to it for instantiated module frame_read_write
W: Verilog-2019: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 414)] Width mismatch between port write_addr_3 and signal bound to it for instantiated module frame_read_write
W: Verilog-2019: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 414)] Width mismatch between port write_len and signal bound to it for instantiated module frame_read_write
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 21)] Elaborating module ddr3
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 21)] Elaborating module pll_50_400_v1_1
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 136)] Net clkfb in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 139)] Net pfden in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 141)] Net clkout0_2pad_gate in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 142)] Net clkout1_gate in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 143)] Net clkout2_gate in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 144)] Net clkout3_gate in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 145)] Net clkout4_gate in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 146)] Net clkout5_gate in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 147)] Net dyn_idiv in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 148)] Net dyn_odiv0 in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 149)] Net dyn_odiv1 in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 150)] Net dyn_odiv2 in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 151)] Net dyn_odiv3 in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 152)] Net dyn_odiv4 in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 153)] Net dyn_fdiv in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 154)] Net dyn_duty0 in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 155)] Net dyn_duty1 in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 156)] Net dyn_duty2 in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 157)] Net dyn_duty3 in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 158)] Net dyn_duty4 in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 159)] Net dyn_phase0[0] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 159)] Net dyn_phase0[1] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 159)] Net dyn_phase0[2] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 159)] Net dyn_phase0[3] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 159)] Net dyn_phase0[4] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 159)] Net dyn_phase0[5] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 159)] Net dyn_phase0[6] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 159)] Net dyn_phase0[7] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 159)] Net dyn_phase0[8] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 159)] Net dyn_phase0[9] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 159)] Net dyn_phase0[10] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 159)] Net dyn_phase0[11] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 159)] Net dyn_phase0[12] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 160)] Net dyn_phase1[0] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 160)] Net dyn_phase1[1] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 160)] Net dyn_phase1[2] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 160)] Net dyn_phase1[3] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 160)] Net dyn_phase1[4] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 160)] Net dyn_phase1[5] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 160)] Net dyn_phase1[6] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 160)] Net dyn_phase1[7] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 160)] Net dyn_phase1[8] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 160)] Net dyn_phase1[9] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 160)] Net dyn_phase1[10] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 160)] Net dyn_phase1[11] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 160)] Net dyn_phase1[12] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 161)] Net dyn_phase2[0] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 161)] Net dyn_phase2[1] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 161)] Net dyn_phase2[2] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 161)] Net dyn_phase2[3] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 161)] Net dyn_phase2[4] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 161)] Net dyn_phase2[5] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 161)] Net dyn_phase2[6] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 161)] Net dyn_phase2[7] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 161)] Net dyn_phase2[8] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 161)] Net dyn_phase2[9] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 161)] Net dyn_phase2[10] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 161)] Net dyn_phase2[11] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 161)] Net dyn_phase2[12] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 162)] Net dyn_phase3[0] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 162)] Net dyn_phase3[1] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 162)] Net dyn_phase3[2] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 162)] Net dyn_phase3[3] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 162)] Net dyn_phase3[4] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 162)] Net dyn_phase3[5] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 162)] Net dyn_phase3[6] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 162)] Net dyn_phase3[7] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 162)] Net dyn_phase3[8] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 162)] Net dyn_phase3[9] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 162)] Net dyn_phase3[10] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 162)] Net dyn_phase3[11] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 162)] Net dyn_phase3[12] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 163)] Net dyn_phase4[0] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 163)] Net dyn_phase4[1] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 163)] Net dyn_phase4[2] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 163)] Net dyn_phase4[3] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 163)] Net dyn_phase4[4] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 163)] Net dyn_phase4[5] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 163)] Net dyn_phase4[6] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 163)] Net dyn_phase4[7] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 163)] Net dyn_phase4[8] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 163)] Net dyn_phase4[9] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 163)] Net dyn_phase4[10] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 163)] Net dyn_phase4[11] in module pll_50_400_v1_1 does not have a driver, tie it to 0
W: Verilog-2020: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/pll/pll_50_400_v1_1.v(line number: 163)] Net dyn_phase4[12] in module pll_50_400_v1_1 does not have a driver, tie it to 0
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_phy_top_v1_1.v(line number: 17)] Elaborating module ipsl_hmic_h_phy_top_v1_1
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrphy_reset_ctrl_v1_1.v(line number: 17)] Elaborating module ipsl_hmic_h_ddrphy_reset_ctrl_v1_1
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrphy_training_ctrl_v1_1.v(line number: 17)] Elaborating module ipsl_hmic_h_ddrphy_training_ctrl_v1_1
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrphy_dll_update_ctrl_v1_1.v(line number: 17)] Elaborating module ipsl_hmic_h_ddrphy_dll_update_ctrl_v1_1
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrphy_update_ctrl_v1_1.v(line number: 17)] Elaborating module ipsl_hmic_h_ddrphy_update_ctrl_v1_1
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrphy_update_ctrl_v1_1.v(line number: 68)] Net dqsi_dpi_mon_req in module ipsl_hmic_h_ddrphy_update_ctrl_v1_1 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrphy_update_ctrl_v1_1.v(line number: 69)] Net dly_loop_mon_req in module ipsl_hmic_h_ddrphy_update_ctrl_v1_1 does not have a driver, tie it to 0
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_phy_io_v1_1.v(line number: 17)] Elaborating module ipsl_hmic_h_phy_io_v1_1
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/library/operator/gtp_lib.v(line number: 1135)] Elaborating module GTP_DDRPHY
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/library/operator/gtp_lib.v(line number: 17168)] Elaborating module GTP_IOCLKBUF
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/library/operator/gtp_lib.v(line number: 17196)] Elaborating module GTP_IOCLKDIV
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/library/operator/gtp_lib.v(line number: 1737)] Elaborating module GTP_DLL
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/library/operator/gtp_lib.v(line number: 594)] Elaborating module GTP_DDC_E1
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/library/operator/gtp_lib.v(line number: 17029)] Elaborating module GTP_INV
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/library/operator/gtp_lib.v(line number: 17256)] Elaborating module GTP_IODELAY
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/library/operator/gtp_lib.v(line number: 17527)] Elaborating module GTP_ISERDES
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/library/operator/gtp_lib.v(line number: 17006)] Elaborating module GTP_INBUFG
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/library/operator/gtp_lib.v(line number: 18596)] Elaborating module GTP_OUTBUF
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/library/operator/gtp_lib.v(line number: 17037)] Elaborating module GTP_IOBUF
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/library/operator/gtp_lib.v(line number: 17094)] Elaborating module GTP_IOBUFCO
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/library/operator/gtp_lib.v(line number: 18643)] Elaborating module GTP_OUTBUFTCO
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_phy_io_v1_1.v(line number: 319)] Net loop_in_di in module ipsl_hmic_h_phy_io_v1_1 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_phy_io_v1_1.v(line number: 320)] Net loop_in_do in module ipsl_hmic_h_phy_io_v1_1 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_phy_io_v1_1.v(line number: 321)] Net loop_in_to in module ipsl_hmic_h_phy_io_v1_1 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_phy_io_v1_1.v(line number: 322)] Net loop_out_di in module ipsl_hmic_h_phy_io_v1_1 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_phy_io_v1_1.v(line number: 323)] Net loop_out_do in module ipsl_hmic_h_phy_io_v1_1 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_phy_io_v1_1.v(line number: 324)] Net loop_out_to in module ipsl_hmic_h_phy_io_v1_1 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_phy_io_v1_1.v(line number: 360)] Net loop_in_di_h in module ipsl_hmic_h_phy_io_v1_1 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_phy_io_v1_1.v(line number: 361)] Net loop_in_do_h in module ipsl_hmic_h_phy_io_v1_1 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_phy_io_v1_1.v(line number: 362)] Net loop_in_to_h in module ipsl_hmic_h_phy_io_v1_1 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_phy_io_v1_1.v(line number: 363)] Net loop_out_di_h in module ipsl_hmic_h_phy_io_v1_1 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_phy_io_v1_1.v(line number: 364)] Net loop_out_do_h in module ipsl_hmic_h_phy_io_v1_1 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_phy_io_v1_1.v(line number: 365)] Net loop_out_to_h in module ipsl_hmic_h_phy_io_v1_1 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_phy_io_v1_1.v(line number: 373)] Net resetn_do in module ipsl_hmic_h_phy_io_v1_1 does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_phy_io_v1_1.v(line number: 374)] Net resetn_to in module ipsl_hmic_h_phy_io_v1_1 does not have a driver, tie it to 0
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_phy_top_v1_1.v(line number: 302)] Give initial value 0 for the no drive pin srb_core_clk in module instance
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_phy_top_v1_1.v(line number: 171)] Net update_start in module ipsl_hmic_h_phy_top_v1_1 does not have a driver, tie it to 0
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrc_top_v1_1.v(line number: 17)] Elaborating module ipsl_hmic_h_ddrc_top_v1_1
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrc_reset_ctrl_v1_1.v(line number: 17)] Elaborating module ipsl_hmic_h_ddrc_reset_ctrl_v1_1
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/rtl/ipsl_hmic_h_ddrc_apb_reset_v1_1.v(line number: 17)] Elaborating module ipsl_hmic_h_ddrc_apb_reset_v1_1
I: Verilog-0003: [D:/pango/PDS_2020.3/arch/vendor/pango/library/operator/gtp_lib.v(line number: 689)] Elaborating module GTP_DDRC
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin aclk_0 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin awid_0 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin awaddr_0 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin awlen_0 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin awsize_0 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin awburst_0 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin awlock_0 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin awvalid_0 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin awurgent_0 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin awpoison_0 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin wdata_0 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin wstrb_0 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin wlast_0 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin wvalid_0 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin bready_0 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin arid_0 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin araddr_0 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin arlen_0 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin arsize_0 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin arburst_0 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin arlock_0 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin arvalid_0 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin arpoison_0 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin rready_0 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin arurgent_0 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin aclk_2 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin awid_2 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin awaddr_2 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin awlen_2 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin awsize_2 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin awburst_2 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin awlock_2 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin awvalid_2 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin awurgent_2 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin awpoison_2 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin wdata_2 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin wstrb_2 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin wlast_2 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin wvalid_2 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin bready_2 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin arid_2 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin araddr_2 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin arlen_2 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin arsize_2 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin arburst_2 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin arlock_2 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin arvalid_2 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin arpoison_2 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin rready_2 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin arurgent_2 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin csysreq_0 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin csysreq_2 in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin paddr in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin pwdata in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin pwrite in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin penable in module instance
W: Verilog-2023: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ddr3/ddr3.v(line number: 596)] Give initial value 0 for the no drive pin psel in module instance
W: Verilog-2019: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 461)] Width mismatch between port ddrc_rst and signal bound to it for instantiated module ddr3
W: Verilog-2019: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 461)] Width mismatch between port areset_1 and signal bound to it for instantiated module ddr3
W: Verilog-2019: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 461)] Width mismatch between port awid_1 and signal bound to it for instantiated module ddr3
W: Verilog-2019: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 461)] Width mismatch between port awaddr_1 and signal bound to it for instantiated module ddr3
W: Verilog-2019: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 461)] Width mismatch between port bid_1 and signal bound to it for instantiated module ddr3
W: Verilog-2019: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 461)] Width mismatch between port arid_1 and signal bound to it for instantiated module ddr3
W: Verilog-2019: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 461)] Width mismatch between port araddr_1 and signal bound to it for instantiated module ddr3
W: Verilog-2019: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 461)] Width mismatch between port arlock_1 and signal bound to it for instantiated module ddr3
W: Verilog-2019: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 461)] Width mismatch between port rid_1 and signal bound to it for instantiated module ddr3
I: Verilog-0003: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/aq_axi_master.v(line number: 39)] Elaborating module aq_axi_master
W: Verilog-2019: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 546)] Width mismatch between port M_AXI_AWID and signal bound to it for instantiated module aq_axi_master
W: Verilog-2019: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 546)] Width mismatch between port M_AXI_AWADDR and signal bound to it for instantiated module aq_axi_master
W: Verilog-2019: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 546)] Width mismatch between port M_AXI_BID and signal bound to it for instantiated module aq_axi_master
W: Verilog-2019: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 546)] Width mismatch between port M_AXI_ARID and signal bound to it for instantiated module aq_axi_master
W: Verilog-2019: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 546)] Width mismatch between port M_AXI_ARADDR and signal bound to it for instantiated module aq_axi_master
W: Verilog-2019: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 546)] Width mismatch between port M_AXI_RID and signal bound to it for instantiated module aq_axi_master
W: Verilog-2019: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 546)] Width mismatch between port WR_ADRS and signal bound to it for instantiated module aq_axi_master
W: Verilog-2019: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 546)] Width mismatch between port WR_LEN and signal bound to it for instantiated module aq_axi_master
W: Verilog-2019: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 546)] Width mismatch between port RD_ADRS and signal bound to it for instantiated module aq_axi_master
W: Verilog-2019: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 546)] Width mismatch between port RD_LEN and signal bound to it for instantiated module aq_axi_master
W: Verilog-2036: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 262)] Net red_en connected to input port of module instance has no driver, tie it to 0
W: Verilog-2036: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 262)] Net grenn_en connected to input port of module instance has no driver, tie it to 0
W: Verilog-2036: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 262)] Net blue_en connected to input port of module instance has no driver, tie it to 0
W: Verilog-2036: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 546)] Net s00_axi_buser connected to input port of module instance has no driver, tie it to 0
W: Verilog-2036: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 546)] Net s00_axi_ruser connected to input port of module instance has no driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 75)] Net button_negedge_key3 in module top does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 76)] Net led_eeprom in module top does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 77)] Net read_data_eep in module top does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 115)] Net ui_clk_sync_rst in module top does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 116)] Net init_calib_complete in module top does not have a driver, tie it to 0
W: Verilog-2021: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/sources_1/top.v(line number: 164)] Net clk_200MHz in module top does not have a driver, tie it to 0
Executing : rtl-elaborate successfully.
Start rtl-prep.
Executing : rtl-prep successfully.
Start rtl-infer.
W: Sdm-2005: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/ISP.v(line number: 56)] No value assigned under clock for signal THRESHOLD, possible generate latch.
W: Sdm-2004: [D:/FPGA_CODE/Other_work/fruit/Prj/isp_ddr3_ov5640_hdmi/source/ISP/ISP.v(line number: 56)] Latch is generated for signal THRESHOLD, possible missing assignment in an if or case statement.
I: Removed inst v_we that is redundant to h_we.
I: Removed inst v_di that is redundant to h_di.
I: Sdm-0001: Found Ram mem, depth=1024, width=1.
I: Removed inst srb_ioclkdiv_rstn that is redundant to srb_dqs_rstn.
I: Removed inst init_ddrc_rst that is redundant to init_axi_reset0.
I: Removed inst init_axi_reset1 that is redundant to init_axi_reset0.
I: Removed inst init_axi_reset2 that is redundant to init_axi_reset0.
I: Sdm-0001: Found Ram mem, depth=64, width=56.
I: Sdm-0001: Found Ram ram, depth=1024, width=8.
Executing : rtl-infer successfully.
Start rtl-control-opt.
Executing : rtl-control-opt successfully.
Start rtl-data-opt.
Executing : rtl-data-opt successfully.
Start FSM inference.
I: FSM stage[5:0]_fsm[5:0] inferred.
I: FSM VSTATE[2:0]_fsm[2:0] inferred.
I: FSM HSTATE[2:0]_fsm[2:0] inferred.
I: FSM status[5:0]_fsm[5:0] inferred.
I: FSM RSTATE[8:0]_fsm[8:0] inferred.
I: FSM state[2:0]_fsm[2:0] inferred.
I: FSM state[2:0]_fsm[2:0] inferred.
I: FSM state[2:0]_fsm[2:0] inferred.
I: FSM c_state[4:0]_fsm[4:0] inferred.
I: FSM c_state[17:0]_fsm[17:0] inferred.
I: FSM state[3:0]_fsm[3:0] inferred.
I: FSM state[3:0]_fsm[3:0] inferred.
I: FSM state[3:0]_fsm[3:0] inferred.
I: FSM state[1:0]_fsm[1:0] inferred.
I: FSM state[1:0]_fsm[1:0] inferred.
I: FSM wr_state[2:0]_fsm[2:0] inferred.
I: FSM rd_state[2:0]_fsm[2:0] inferred.
Executing : FSM inference successfully.
Start sdm2adm.
I: Constant propagation done on N309_1 (bmsWIDEMUX).
I: Constant propagation done on N291_1 (bmsWIDEMUX).
I: Constant propagation done on N327_1 (bmsWIDEMUX).
I: Constant propagation done on N261 (bmsWIDEMUX).
I: Constant propagation done on N268 (bmsWIDEMUX).
I: Constant propagation done on N7_8 (bmsREDXOR).
I: Constant propagation done on N106 (bmsREDXOR).
I: Constant propagation done on N49 (bmsREDXOR).
I: Constant propagation done on N59 (bmsREDXOR).
I: Constant propagation done on N39 (bmsREDXOR).
W: Adm-4021: The attribute 'PAP_PRESERVE' of object 'stage[5:0]_fsm[5:0]' is overwritten by new value.
Executing : sdm2adm successfully.
Saving design to DB.
Action compile: Real time elapsed is 6.000 sec
Action compile: CPU time elapsed is 3.813 sec
Current time: Fri May 27 22:56:31 2022
Action compile: Peak memory pool usage is 108,498,944 bytes
