//////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2014 PANGO MICROSYSTEMS, INC
// ALL RIGHTS REVERVED.
//
// THE SOURCE CODE CONTAINED HEREIN IS PROPRIETARY TO PANGO MICROSYSTEMS, INC.
// IT SHALL NOT BE REPRODUCED OR DISCLOSED IN WHOLE OR IN PART OR USED BY
// PARTIES WITHOUT WRITTEN AUTHORIZATION FROM THE OWNER.
//
//////////////////////////////////////////////////////////////////////////////
//the jtag_hub module, it controls to select which debug_core and sub module
//note that one FPGA only support one jtag_hub
//
module ips_jtag_hub_v1_2
 #(
   parameter  CTRL_PORT_NUM = 1     //@IPC int 1,15           //the number of usr_app connect with jtag_hub  
 )
 (
   // for JTAG_interface                        
   input            tdi_in,                    //TDI for user data register;
   output           tdo_out,                   //TDO for user data register 
   input            reset_dr,	                 //active high reset when TAP state in e_TEST_LOGIC_RESET state
   input            shift_in,	                 //TAP state in e_SHIFT_DR
   input            update_in,                 //TAP state in e_UPDATE_DR
   input            capture_in,                //TAP state in e_CAPTURE_DR
   input            sel_in,                    //user data register is selected
   input            drck_in,                   //TCK for user data register
   input            h_rstn ,                   //hw reset from user logic device, active low.    
  // for user_app interface(debug_core,etc)
   output           drck_o,                    //transfer TCK to each user_app
   output           conf_tdi,                  //transfer TDI to each user_app
   output reg [15:0]conf_sel,                  //select config module which indicated by ID  
   output reg [4:0] id_o,                      //ID number indication
   output           capt_o,                    //capture
   output           shift_d,                    //shift_in delay 1 clk
   input     [15:0] hub_tdo                    //read back signal from each user_app

 );  
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="default"
`pragma protect author_info="default"
`pragma protect encrypt_agent="Synplify encryptP1735.pl"
`pragma protect encrypt_agent_info="Synplify encryptP1735.pl Version 1.1"

`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
`pragma protect key_keyowner="Synplicity", key_keyname="SYNP15_1", key_method="rsa"
`pragma protect key_block
BEIaFyRKTrBmSBJTu9yfddPBf03viRoaxqlrr0CRsEW+bzQT4fmPeJeTIV53vyGu/OF60ClCcVGk
rTDOVV8KP5HpOEM7uago4t6lrfhCyWCpWcToQv9bckZaTrld+tV5vtt35Jd7Iv8A7w2JOMWGnGIy
4W7ZSCZ/8Ynta9Nt1caspGk4Vkkpc3+oy7v3wt8Myu9K90IfHj9fPlOXdOxTSmZFytKrwsFDevU8
oIeGOn1b2mnEaUkPNsm+ulEn5dsD6RomPiXKUezBBaKSwUDOPpbwvIJPAJT28U9HsvqC1hGDnGE6
6gjDYY7yZi/M0rStoVMhU/XwtIJxNFjJJqtMWA==

`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
`pragma protect key_keyowner="Pango Microsystems", key_keyname="PANGO_18", key_method="rsa"
`pragma protect key_block
vuDp3DVgyiP2eInOjAMo7cR01xUGIg1Ix1e2snzoxgx0Ii3vowNVrv6EdE9GRRm/ry5Q4g4CFpjL
8PmcdJABNcB/zZAOymVldhwjyHANw3GCjOfSjzrgcj+49a09WZwHXa5JJTjOIWS/56gkxebUzkmC
jsR+uV7v/Nm1D+uVt4rplyeQpQshswUwJkSW8GMorCkZSTz4qkLyAn8ZGs/RFayHXniNJVSwEhTF
ZRGK1kKyBYy9Qd1qlzAQRZBrSAAZ2PuCqQOwRplawGl5Ry8rts/sizsR2/dTCjU7WnYzWosx5iIz
+aL4DZBhNRNvZGJkYxYz+gAWrsSOZZ/jJ2OjSQ==

`pragma protect data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=10928)
`pragma protect data_block
[encoded data, 14516 characters]
wecLB/SOswGBlB+wo1lt7EGN2/JsDXs3LnKumLdVplpaJr7m4NDnm2w=

`pragma protect end_protected

endmodule
