#Build: Synplify Pro (R) P-2019.03P-Beta2, Build 3717R, Feb 25 2019
#install: C:\pango\PDS_2019.1-patch2\syn
#OS: Windows 7 6.1
#Hostname: ALINX000007-PC

# Tue May  7 09:59:59 2019

#Implementation: synplify_impl


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03P-Beta2
Install: C:\pango\PDS_2019.1-patch2\syn
OS: Windows 6.1

Hostname: ALINX000007-PC

Implementation : synplify_impl
Synopsys HDL Compiler, Version comp2019q1p1, Build 007R, Built Feb 26 2019 11:45:06

@N|Running in 64-bit mode
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03P-Beta2
Install: C:\pango\PDS_2019.1-patch2\syn
OS: Windows 6.1

Hostname: ALINX000007-PC

Implementation : synplify_impl
Synopsys Verilog Compiler, Version comp2019q1p1, Build 007R, Built Feb 26 2019 11:45:06

@N|Running in 64-bit mode
@I::"C:\pango\PDS_2019.1-patch2\syn\lib\generic\logos.v" (library work)
@I::"C:\pango\PDS_2019.1-patch2\syn\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\pango\PDS_2019.1-patch2\syn\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\pango\PDS_2019.1-patch2\syn\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\pango\PDS_2019.1-patch2\syn\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_main_ctrl.v" (library work)
@W: CG1337 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_main_ctrl.v":88:7:88:17|Net prbs_clk_en is not declared.
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_apb_reset.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_reset_ctrl.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_dll_update_ctrl.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_reset_ctrl.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_training_ctrl.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_hmemc_ddrc_top.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_hmemc_phy_top.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v" (library work)
@W: CG1337 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":260:7:260:9|Net err is not declared.
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\ipsl_hmemc_top_test.v" (library work)
Verilog syntax check successful!
Selecting top level module ipsl_hmemc_top_test
@N: CG364 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":11:7:11:19|Synthesizing module prbs31_128bit in library work.

	PRBS_INIT=128'b00010010001101000101011001111000100110101011110011011110111100001000011010000110001000000001011000000111000001110011001101101010
	PRBS_GEN_EN=1'b1
   Generated name = prbs31_128bit_1_Z1
Running optimization stage 1 on prbs31_128bit_1_Z1 .......
@N: CG364 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_main_ctrl.v":7:7:7:20|Synthesizing module test_main_ctrl in library work.

	CTRL_ADDR_WIDTH=32'b00000000000000000000000000011100
	MEM_DQ_WIDTH=32'b00000000000000000000000000010000
	MEM_SPACE_AW=32'b00000000000000000000000000011100
	E_IDLE=32'b00000000000000000000000000000000
	E_INIT=32'b00000000000000000000000000000001
	E_WR=32'b00000000000000000000000000000010
	E_RD=32'b00000000000000000000000000000011
	E_END=32'b00000000000000000000000000000100
   Generated name = test_main_ctrl_28s_16s_28s_0s_1s_2s_3s_4s
Running optimization stage 1 on test_main_ctrl_28s_16s_28s_0s_1s_2s_3s_4s .......
@N: CG364 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":2:7:2:24|Synthesizing module test_wr_ctrl_64bit in library work.

	CTRL_ADDR_WIDTH=32'b00000000000000000000000000011100
	MEM_DQ_WIDTH=32'b00000000000000000000000000010000
	MEM_COL_ADDR_WIDTH=32'b00000000000000000000000000001010
	MEM_SPACE_AW=32'b00000000000000000000000000011100
	DQ_NUM=32'b00000000000000000000000000000001
	ADDR_NUM_BIT=32'b00000000000000000000000000000011
	AXI_ADDR_MAX=32'b01000000000000000000000000000000
	ADDR_MAX=32'b00100000000000000000000000000000
	E_IDLE=32'b00000000000000000000000000000000
	E_WR=32'b00000000000000000000000000000001
	E_END=32'b00000000000000000000000000000010
   Generated name = test_wr_ctrl_64bit_Z2
Running optimization stage 1 on test_wr_ctrl_64bit_Z2 .......
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Optimizing register bit axi_awlen[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Optimizing register bit axi_awlen[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Optimizing register bit axi_awlen[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Optimizing register bit axi_awlen[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Pruning register bits 7 to 4 of axi_awlen[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@N: CG364 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":4:7:4:24|Synthesizing module test_rd_ctrl_64bit in library work.

	CTRL_ADDR_WIDTH=32'b00000000000000000000000000011100
	MEM_DQ_WIDTH=32'b00000000000000000000000000010000
	MEM_COL_ADDR_WIDTH=32'b00000000000000000000000000001010
	MEM_SPACE_AW=32'b00000000000000000000000000011100
	DQ_NUM=32'b00000000000000000000000000000001
	ADDR_NUM_BIT=32'b00000000000000000000000000000011
	E_IDLE=32'b00000000000000000000000000000000
	E_RD=32'b00000000000000000000000000000001
	E_END=32'b00000000000000000000000000000010
   Generated name = test_rd_ctrl_64bit_28s_16s_10s_28s_1s_3s_0s_1s_2s
@N: CG179 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":284:23:284:29|Removing redundant assignment.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":61:24:61:31|Removing wire rd_data4, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":62:24:62:31|Removing wire rd_data5, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":63:24:63:31|Removing wire rd_data6, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":64:24:64:31|Removing wire rd_data7, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":70:13:70:22|Removing wire addr_4_mux, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":71:13:71:22|Removing wire addr_5_mux, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":72:13:72:22|Removing wire addr_6_mux, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":73:13:73:22|Removing wire addr_7_mux, as there is no assignment to it.
Running optimization stage 1 on test_rd_ctrl_64bit_28s_16s_10s_28s_1s_3s_0s_1s_2s .......
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":94:0:94:5|Optimizing register bit axi_araddr[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":94:0:94:5|Optimizing register bit axi_araddr[29] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":94:0:94:5|Optimizing register bit axi_araddr[30] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":94:0:94:5|Optimizing register bit axi_araddr[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":94:0:94:5|Optimizing register bit axi_arid[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":94:0:94:5|Optimizing register bit axi_arid[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":94:0:94:5|Optimizing register bit axi_arid[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":94:0:94:5|Optimizing register bit axi_arid[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":94:0:94:5|Optimizing register bit axi_arlen[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":94:0:94:5|Optimizing register bit axi_arlen[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":94:0:94:5|Optimizing register bit axi_arlen[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":94:0:94:5|Optimizing register bit axi_arlen[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":94:0:94:5|Pruning register bits 7 to 4 of axi_arid[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":94:0:94:5|Pruning register bits 7 to 4 of axi_arlen[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":94:0:94:5|Pruning register bits 31 to 29 of axi_araddr[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL260 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":94:0:94:5|Pruning register bit 0 of axi_araddr[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@N: CG364 :"C:\pango\PDS_2019.1-patch2\syn\lib\generic\logos.v":2251:7:2251:16|Synthesizing module GTP_PLL_E1 in library work.
Running optimization stage 1 on GTP_PLL_E1 .......
@N: CG364 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":5:7:5:16|Synthesizing module pll_50_400 in library work.
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":259:14:259:14|Input DUTYF on instance u_pll_e1 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":265:15:265:15|Input PHASEF on instance u_pll_e1 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":271:16:271:16|Input CPHASEF on instance u_pll_e1 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":120:9:120:13|Removing wire clkfb, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":123:9:123:13|Removing wire pfden, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":125:9:125:25|Removing wire clkout0_2pad_gate, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":126:9:126:20|Removing wire clkout1_gate, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":127:9:127:20|Removing wire clkout2_gate, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":128:9:128:20|Removing wire clkout3_gate, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":129:9:129:20|Removing wire clkout4_gate, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":130:9:130:20|Removing wire clkout5_gate, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":131:15:131:22|Removing wire dyn_idiv, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":132:15:132:23|Removing wire dyn_odiv0, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":133:15:133:23|Removing wire dyn_odiv1, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":134:15:134:23|Removing wire dyn_odiv2, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":135:15:135:23|Removing wire dyn_odiv3, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":136:15:136:23|Removing wire dyn_odiv4, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":137:15:137:22|Removing wire dyn_fdiv, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":138:15:138:23|Removing wire dyn_duty0, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":139:15:139:23|Removing wire dyn_duty1, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":140:15:140:23|Removing wire dyn_duty2, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":141:15:141:23|Removing wire dyn_duty3, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":142:15:142:23|Removing wire dyn_duty4, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":143:16:143:25|Removing wire dyn_phase0, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":144:16:144:25|Removing wire dyn_phase1, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":145:16:145:25|Removing wire dyn_phase2, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":146:16:146:25|Removing wire dyn_phase3, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":147:16:147:25|Removing wire dyn_phase4, as there is no assignment to it.
Running optimization stage 1 on pll_50_400 .......
@N: CG364 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_reset_ctrl.v":1:7:1:28|Synthesizing module ipsl_ddrphy_reset_ctrl in library work.
Running optimization stage 1 on ipsl_ddrphy_reset_ctrl .......
@N: CG364 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_training_ctrl.v":1:7:1:31|Synthesizing module ipsl_ddrphy_training_ctrl in library work.
@N: CG179 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_training_ctrl.v":34:37:34:61|Removing redundant assignment.
Running optimization stage 1 on ipsl_ddrphy_training_ctrl .......
@N: CG364 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_dll_update_ctrl.v":1:7:1:33|Synthesizing module ipsl_ddrphy_dll_update_ctrl in library work.
Running optimization stage 1 on ipsl_ddrphy_dll_update_ctrl .......
@N: CG364 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":1:7:1:29|Synthesizing module ipsl_ddrphy_update_ctrl in library work.

	DATA_WIDTH=40'b0011000100110110010000100100100101010100
	DLL_OFFSET=32'b00000000000000000000000000000010
	IDLE=32'b00000000000000000000000000000000
	REQ=32'b00000000000000000000000000000001
	UPDATE=32'b00000000000000000000000000000010
	WAIT_END=32'b00000000000000000000000000000011
	DQSH_REQ_EN=1'b1
   Generated name = ipsl_ddrphy_update_ctrl_16BIT_2s_0s_1s_2s_3s_1
@W: CG133 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":44:4:44:19|Object dqsi_dpi_mon_req is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":45:4:45:19|Object dly_loop_mon_req is declared but not assigned. Either assign a value or remove the declaration.
Running optimization stage 1 on ipsl_ddrphy_update_ctrl_16BIT_2s_0s_1s_2s_3s_1 .......
@N: CG364 :"C:\pango\PDS_2019.1-patch2\syn\lib\generic\logos.v":1316:7:1316:13|Synthesizing module GTP_DLL in library work.
Running optimization stage 1 on GTP_DLL .......
@N: CG364 :"C:\pango\PDS_2019.1-patch2\syn\lib\generic\logos.v":696:7:696:16|Synthesizing module GTP_DDRPHY in library work.
Running optimization stage 1 on GTP_DDRPHY .......
@N: CG364 :"C:\pango\PDS_2019.1-patch2\syn\lib\generic\logos.v":1737:7:1737:18|Synthesizing module GTP_IOCLKBUF in library work.
Running optimization stage 1 on GTP_IOCLKBUF .......
@N: CG364 :"C:\pango\PDS_2019.1-patch2\syn\lib\generic\logos.v":1766:7:1766:18|Synthesizing module GTP_IOCLKDIV in library work.
Running optimization stage 1 on GTP_IOCLKDIV .......
@N: CG364 :"C:\pango\PDS_2019.1-patch2\syn\lib\generic\logos.v":195:7:195:16|Synthesizing module GTP_DDC_E1 in library work.
Running optimization stage 1 on GTP_DDC_E1 .......
@N: CG364 :"C:\pango\PDS_2019.1-patch2\syn\lib\generic\logos.v":2154:7:2154:17|Synthesizing module GTP_OSERDES in library work.
Running optimization stage 1 on GTP_OSERDES .......
@N: CG364 :"C:\pango\PDS_2019.1-patch2\syn\lib\generic\logos.v":1779:7:1779:17|Synthesizing module GTP_IODELAY in library work.
Running optimization stage 1 on GTP_IODELAY .......
@N: CG364 :"C:\pango\PDS_2019.1-patch2\syn\lib\generic\logos.v":1819:7:1819:17|Synthesizing module GTP_ISERDES in library work.
Running optimization stage 1 on GTP_ISERDES .......
@N: CG364 :"C:\pango\PDS_2019.1-patch2\syn\lib\generic\logos.v":1612:7:1612:16|Synthesizing module GTP_INBUFG in library work.
Running optimization stage 1 on GTP_INBUFG .......
@N: CG364 :"C:\pango\PDS_2019.1-patch2\syn\lib\generic\logos.v":2175:7:2175:16|Synthesizing module GTP_OUTBUF in library work.
Running optimization stage 1 on GTP_OUTBUF .......
@N: CG364 :"C:\pango\PDS_2019.1-patch2\syn\lib\generic\logos.v":2212:7:2212:17|Synthesizing module GTP_OUTBUFT in library work.
Running optimization stage 1 on GTP_OUTBUFT .......
@N: CG364 :"C:\pango\PDS_2019.1-patch2\syn\lib\generic\logos.v":1645:7:1645:15|Synthesizing module GTP_IOBUF in library work.
Running optimization stage 1 on GTP_IOBUF .......
@N: CG364 :"C:\pango\PDS_2019.1-patch2\syn\lib\generic\logos.v":2226:7:2226:19|Synthesizing module GTP_OUTBUFTCO in library work.
Running optimization stage 1 on GTP_OUTBUFTCO .......
@N: CG364 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":27:7:27:17|Synthesizing module ipsl_phy_io in library work.

	DQS_GATE_LOOP=32'b01010100010100100101010101000101
	R_EXTEND=40'b0100011001000001010011000101001101000101
	CORE_CLK_SEL=1'b0
	TEST_PATTERN2=32'b01111111011111110111111101111111
	TEST_PATTERN3=32'b01010000101111000101000010111100
	T200US=32'b00000000000000001001110001000000
	MR0_DDR3=16'b0001010100100000
	MR1_DDR3=16'b0000000000010100
	MR2_DDR3=16'b0000000000000000
	MR3_DDR3=16'b0000000000000000
	MR_DDR2=16'b0000101101010011
	EMR1_DDR2=16'b0000000000011100
	EMR2_DDR2=16'b0000000000000000
	EMR3_DDR2=16'b0000000000000000
	MR_LPDDR=16'b0000000000110011
	EMR_LPDDR=16'b0000000000000000
	TMRD=32'b00000000000000000000000000000010
	TMOD=32'b00000000000000000000000000000110
	TZQINIT=32'b00000000000000000000000100000000
	TXPR=32'b00000000000000000000000000111110
	TRP=32'b00000000000000000000000000000011
	TRFC=32'b00000000000000000000000000111100
	WL_EN=32'b01010100010100100101010101000101
	DDR_TYPE=32'b01000100010001000101001000110011
	DATA_WIDTH=40'b0011000100110110010000100100100101010100
	DQS_GATE_MODE=2'b01
	WRDATA_PATH_ADJ=40'b0100011001000001010011000101001101000101
	CTRL_PATH_ADJ=40'b0100011001000001010011000101001101000101
	WL_MAX_STEP=8'b11111111
	WL_MAX_CHECK=5'b11111
	MAN_WRLVL_DQS_L=40'b0100011001000001010011000101001101000101
	MAN_WRLVL_DQS_H=40'b0100011001000001010011000101001101000101
	WL_CTRL_L=3'b001
	WL_CTRL_H=3'b001
	INIT_READ_CLK_CTRL=2'b11
	INIT_READ_CLK_CTRL_H=2'b11
	INIT_SLIP_STEP=4'b0111
	INIT_SLIP_STEP_H=4'b0111
	FORCE_READ_CLK_CTRL_L=40'b0100011001000001010011000101001101000101
	FORCE_READ_CLK_CTRL_H=40'b0100011001000001010011000101001101000101
	STOP_WITH_ERROR=40'b0100011001000001010011000101001101000101
	DQGT_DEBUG=1'b0
	WRITE_DEBUG=1'b0
	RDEL_ADJ_MAX_RANG=5'b11111
	MIN_DQSI_WIN=4'b0110
	INIT_SAMP_POSITION=8'b00000000
	INIT_SAMP_POSITION_H=8'b00000000
	FORCE_SAMP_POSITION_L=40'b0100011001000001010011000101001101000101
	FORCE_SAMP_POSITION_H=40'b0100011001000001010011000101001101000101
	RDEL_RD_CNT=19'b0000000000001000000
	T400NS=32'b00000000000000000000000001010000
	T_LPDDR=9'b000000000
	REF_CNT=8'b00110100
	APB_VLD=40'b0100011001000001010011000101001101000101
	TEST_PATTERN1=128'b00000000000000001111111111111111000000000000000011111111111111110000000000000000111111111111111100000000000000001111111111111111
	TRAIN_RST_TYPE=32'b01010100010100100101010101000101
	TXS=8'b00111110
	WL_SETTING=1'b0
	WCLK_DEL_SEL=1'b0
	INIT_WRLVL_STEP_L=8'b00000000
	INIT_WRLVL_STEP_H=8'b00000000
   Generated name = ipsl_phy_io_Z3
@N: CG364 :"C:\pango\PDS_2019.1-patch2\syn\lib\generic\logos.v":1636:7:1636:13|Synthesizing module GTP_INV in library work.
Running optimization stage 1 on GTP_INV .......
@N: CG364 :"C:\pango\PDS_2019.1-patch2\syn\lib\generic\logos.v":1661:7:1661:17|Synthesizing module GTP_IOBUFCO in library work.
Running optimization stage 1 on GTP_IOBUFCO .......
@W: CS263 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1147:42:1147:52|Port-width mismatch for port DQS_DRIFT. The port definition is 2 bits, but the actual port connection bit width is 1. Adjust either the definition or the instantiation of this port.
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1199:41:1199:41|Input DQSI on instance dqs1_dut is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1200:41:1200:41|Input GATE_IN on instance dqs1_dut is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CS263 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1224:42:1224:52|Port-width mismatch for port DQS_DRIFT. The port definition is 2 bits, but the actual port connection bit width is 1. Adjust either the definition or the instantiation of this port.
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1276:41:1276:41|Input DQSI on instance dqs3_dut is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1277:41:1277:41|Input GATE_IN on instance dqs3_dut is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1313:41:1313:41|Input DQSI on instance dqs4_dut is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1314:41:1314:41|Input GATE_IN on instance dqs4_dut is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":100:41:100:47|Removing wire PSLVERR, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":174:41:174:51|Removing wire DQS_DRIFT_L, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":175:41:175:51|Removing wire DQS_DRIFT_H, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":330:28:330:37|Removing wire loop_in_di, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":331:28:331:37|Removing wire loop_in_do, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":332:28:332:37|Removing wire loop_in_to, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":333:28:333:38|Removing wire loop_out_di, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":334:28:334:38|Removing wire loop_out_do, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":335:28:335:38|Removing wire loop_out_to, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":371:28:371:39|Removing wire loop_in_di_h, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":372:28:372:39|Removing wire loop_in_do_h, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":373:28:373:39|Removing wire loop_in_to_h, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":374:28:374:40|Removing wire loop_out_di_h, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":375:28:375:40|Removing wire loop_out_do_h, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":376:28:376:40|Removing wire loop_out_to_h, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":384:28:384:36|Removing wire resetn_do, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":385:28:385:36|Removing wire resetn_to, as there is no assignment to it.
Running optimization stage 1 on ipsl_phy_io_Z3 .......
@W: CL318 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":100:41:100:47|*Output PSLVERR has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":174:41:174:51|*Output DQS_DRIFT_L has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":175:41:175:51|*Output DQS_DRIFT_H has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL168 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1324:18:1324:24|Removing instance gtp_int_dut[54].inv_dut because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1324:18:1324:24|Removing instance gtp_int_dut[53].inv_dut because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1324:18:1324:24|Removing instance gtp_int_dut[50].inv_dut because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1324:18:1324:24|Removing instance gtp_int_dut[39].inv_dut because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1324:18:1324:24|Removing instance gtp_int_dut[38].inv_dut because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1324:18:1324:24|Removing instance gtp_int_dut[30].inv_dut because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1324:18:1324:24|Removing instance gtp_int_dut[26].inv_dut because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1324:18:1324:24|Removing instance gtp_int_dut[16].inv_dut because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1324:18:1324:24|Removing instance gtp_int_dut[15].inv_dut because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1324:18:1324:24|Removing instance gtp_int_dut[14].inv_dut because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1324:18:1324:24|Removing instance gtp_int_dut[13].inv_dut because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1324:18:1324:24|Removing instance gtp_int_dut[8].inv_dut because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1324:18:1324:24|Removing instance gtp_int_dut[1].inv_dut because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1324:18:1324:24|Removing instance gtp_int_dut[0].inv_dut because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N: CG364 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_hmemc_phy_top.v":1:7:1:24|Synthesizing module ipsl_hmemc_phy_top in library work.

	DQS_GATE_LOOP=32'b01010100010100100101010101000101
	R_EXTEND=40'b0100011001000001010011000101001101000101
	CORE_CLK_SEL=1'b0
	TEST_PATTERN2=32'b01111111011111110111111101111111
	TEST_PATTERN3=32'b01010000101111000101000010111100
	T200US=32'b00000000000000001001110001000000
	MR0_DDR3=16'b0001010100100000
	MR1_DDR3=16'b0000000000010100
	MR2_DDR3=16'b0000000000000000
	MR3_DDR3=16'b0000000000000000
	MR_DDR2=16'b0000101101010011
	EMR1_DDR2=16'b0000000000011100
	EMR2_DDR2=16'b0000000000000000
	EMR3_DDR2=16'b0000000000000000
	MR_LPDDR=16'b0000000000110011
	EMR_LPDDR=16'b0000000000000000
	PHY_TMRD=32'b00000000000000000000000000000010
	PHY_TMOD=32'b00000000000000000000000000000110
	PHY_TZQINIT=32'b00000000000000000000000100000000
	PHY_TXPR=32'b00000000000000000000000000111110
	PHY_TRP=32'b00000000000000000000000000000011
	PHY_TRFC=32'b00000000000000000000000000111100
	WL_EN=32'b01010100010100100101010101000101
	DDR_TYPE=32'b01000100010001000101001000110011
	DATA_WIDTH=40'b0011000100110110010000100100100101010100
	DQS_GATE_MODE=2'b01
	WRDATA_PATH_ADJ=40'b0100011001000001010011000101001101000101
	CTRL_PATH_ADJ=40'b0100011001000001010011000101001101000101
	WL_MAX_STEP=8'b11111111
	WL_MAX_CHECK=5'b11111
	MAN_WRLVL_DQS_L=40'b0100011001000001010011000101001101000101
	MAN_WRLVL_DQS_H=40'b0100011001000001010011000101001101000101
	WL_CTRL_L=3'b001
	WL_CTRL_H=3'b001
	INIT_READ_CLK_CTRL=2'b11
	INIT_READ_CLK_CTRL_H=2'b11
	INIT_SLIP_STEP=4'b0111
	INIT_SLIP_STEP_H=4'b0111
	FORCE_READ_CLK_CTRL_L=40'b0100011001000001010011000101001101000101
	FORCE_READ_CLK_CTRL_H=40'b0100011001000001010011000101001101000101
	STOP_WITH_ERROR=40'b0100011001000001010011000101001101000101
	DQGT_DEBUG=1'b0
	WRITE_DEBUG=1'b0
	RDEL_ADJ_MAX_RANG=5'b11111
	MIN_DQSI_WIN=4'b0110
	INIT_SAMP_POSITION=8'b00000000
	INIT_SAMP_POSITION_H=8'b00000000
	FORCE_SAMP_POSITION_L=40'b0100011001000001010011000101001101000101
	FORCE_SAMP_POSITION_H=40'b0100011001000001010011000101001101000101
	RDEL_RD_CNT=19'b0000000000001000000
	T400NS=32'b00000000000000000000000001010000
	T_LPDDR=9'b000000000
	REF_CNT=8'b00110100
	APB_VLD=40'b0100011001000001010011000101001101000101
	TEST_PATTERN1=128'b00000000000000001111111111111111000000000000000011111111111111110000000000000000111111111111111100000000000000001111111111111111
	TRAIN_RST_TYPE=32'b01010100010100100101010101000101
	PHY_TXS=8'b00111110
	WL_SETTING=1'b0
	WCLK_DEL_SEL=1'b0
	INIT_WRLVL_STEP_L=8'b00000000
	INIT_WRLVL_STEP_H=8'b00000000
	UPDATE_MASK=3'b000
   Generated name = ipsl_hmemc_phy_top_Z4
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_hmemc_phy_top.v":294:46:294:46|Input SRB_CORE_CLK on instance u_ipsl_phy_io is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_hmemc_phy_top.v":155:15:155:26|Removing wire update_start, as there is no assignment to it.
Running optimization stage 1 on ipsl_hmemc_phy_top_Z4 .......
@N: CG364 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_apb_reset.v":1:7:1:25|Synthesizing module ipsl_ddrc_apb_reset in library work.

	TRFC_MIN=10'b0000111100
	TREFI=12'b000000110000
	T_MRD=6'b000010
	T_MOD=10'b0000000110
	DDR_TYPE=32'b01000100010001000101001000110011
	MR=16'b0001010100100000
	EMR=16'b0000000000010100
	EMR2=16'b0000000000000000
	EMR3=16'b0000000000000000
	WR2PRE=7'b0001010
	T_FAW=6'b001001
	T_RAS_MAX=7'b1111111
	T_RAS_MIN=6'b001000
	T_XP=5'b00010
	RD2PRE=6'b000100
	T_RC=7'b0001010
	WL=6'b000101
	RL=6'b000101
	RD2WR=6'b000100
	WR2RD=6'b000110
	T_RCD=5'b00001
	T_CCD=4'b0010
	T_RRD=4'b0010
	T_RP=5'b00011
	T_CKSRX=4'b0100
	T_CKSRE=4'b0110
	T_CKESR=6'b000011
	T_CKE=5'b00010
	DFI_T_RDDATA_EN=7'b0000100
	DFI_TPHY_WRLAT=6'b001001
	DATA_BUS_WIDTH=2'b00
	ADDRESS_MAPPING_SEL=32'b00000000000000000000000000000000
	MEM_ROW_ADDRESS=32'b00000000000000000000000000001111
	MEM_COLUMN_ADDRESS=32'b00000000000000000000000000001010
	MEM_BANK_ADDRESS=32'b00000000000000000000000000000011
	addrmap_bank_b0=8'b00001000
	addrmap_bank_b1=8'b00001000
	addrmap_bank_b2=8'b00001000
	addrmap_col_b2=8'b00000000
	addrmap_col_b3=8'b00000000
	addrmap_col_b4=8'b00000000
	addrmap_col_b5=8'b00000000
	addrmap_col_b6=8'b00000000
	addrmap_col_b7=8'b00000000
	addrmap_col_b8=8'b00000000
	addrmap_col_b9=8'b00000000
	addrmap_col_b10=8'b00011111
	addrmap_col_b11=8'b00011111
	addrmap_row_b0=8'b00000111
	addrmap_row_b1=8'b00000111
	addrmap_row_b2=8'b00000111
	addrmap_row_b3=8'b00000111
	addrmap_row_b4=8'b00000111
	addrmap_row_b5=8'b00000111
	addrmap_row_b6=8'b00000111
	addrmap_row_b7=8'b00000111
	addrmap_row_b8=8'b00000111
	addrmap_row_b9=8'b00000111
	addrmap_row_b10=8'b00000111
	addrmap_row_b11=8'b00000111
	addrmap_row_b12=8'b00000111
	addrmap_row_b13=8'b00000111
	addrmap_row_b14=8'b00000111
	addrmap_row_b15=8'b00011111
   Generated name = ipsl_ddrc_apb_reset_Z5
Running optimization stage 1 on ipsl_ddrc_apb_reset_Z5 .......
@N: CG364 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_reset_ctrl.v":2:7:2:26|Synthesizing module ipsl_ddrc_reset_ctrl in library work.

	TRFC_MIN=10'b0000111100
	TREFI=12'b000000110000
	T_MRD=6'b000010
	T_MOD=10'b0000000110
	DDR_TYPE=32'b01000100010001000101001000110011
	MR=16'b0001010100100000
	EMR=16'b0000000000010100
	EMR2=16'b0000000000000000
	EMR3=16'b0000000000000000
	WR2PRE=7'b0001010
	T_FAW=6'b001001
	T_RAS_MAX=7'b1111111
	T_RAS_MIN=6'b001000
	T_XP=5'b00010
	RD2PRE=6'b000100
	T_RC=7'b0001010
	WL=6'b000101
	RL=6'b000101
	RD2WR=6'b000100
	WR2RD=6'b000110
	T_RCD=5'b00001
	T_CCD=4'b0010
	T_RRD=4'b0010
	T_RP=5'b00011
	T_CKSRX=4'b0100
	T_CKSRE=4'b0110
	T_CKESR=6'b000011
	T_CKE=5'b00010
	DFI_T_RDDATA_EN=7'b0000100
	DFI_TPHY_WRLAT=6'b001001
	DATA_BUS_WIDTH=2'b00
	ADDRESS_MAPPING_SEL=32'b00000000000000000000000000000000
	MEM_ROW_ADDRESS=32'b00000000000000000000000000001111
	MEM_COLUMN_ADDRESS=32'b00000000000000000000000000001010
	MEM_BANK_ADDRESS=32'b00000000000000000000000000000011
   Generated name = ipsl_ddrc_reset_ctrl_Z6
@N: CG179 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_reset_ctrl.v":93:15:93:21|Removing redundant assignment.
@N: CG179 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_reset_ctrl.v":122:20:122:31|Removing redundant assignment.
Running optimization stage 1 on ipsl_ddrc_reset_ctrl_Z6 .......
@N: CG364 :"C:\pango\PDS_2019.1-patch2\syn\lib\generic\logos.v":248:7:248:14|Synthesizing module GTP_DDRC in library work.
Running optimization stage 1 on GTP_DDRC .......
@N: CG364 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_hmemc_ddrc_top.v":1:7:1:25|Synthesizing module ipsl_hmemc_ddrc_top in library work.

	TRFC_MIN=10'b0000111100
	TREFI=12'b000000110000
	T_MRD=6'b000010
	T_MOD=10'b0000000110
	DDR_TYPE=32'b01000100010001000101001000110011
	MR=16'b0001010100100000
	EMR=16'b0000000000010100
	EMR2=16'b0000000000000000
	EMR3=16'b0000000000000000
	WR2PRE=7'b0001010
	T_FAW=6'b001001
	T_RAS_MAX=7'b1111111
	T_RAS_MIN=6'b001000
	T_XP=5'b00010
	RD2PRE=6'b000100
	T_RC=7'b0001010
	WL=6'b000101
	RL=6'b000101
	RD2WR=6'b000100
	WR2RD=6'b000110
	T_RCD=5'b00001
	T_CCD=4'b0010
	T_RRD=4'b0010
	T_RP=5'b00011
	T_CKSRX=4'b0100
	T_CKSRE=4'b0110
	T_CKESR=6'b000011
	T_CKE=5'b00010
	DFI_T_RDDATA_EN=7'b0000100
	DFI_TPHY_WRLAT=6'b001001
	DATA_BUS_WIDTH=2'b00
	ADDRESS_MAPPING_SEL=32'b00000000000000000000000000000000
	MEM_ROW_ADDRESS=32'b00000000000000000000000000001111
	MEM_COLUMN_ADDRESS=32'b00000000000000000000000000001010
	MEM_BANK_ADDRESS=32'b00000000000000000000000000000011
   Generated name = ipsl_hmemc_ddrc_top_Z7
Running optimization stage 1 on ipsl_hmemc_ddrc_top_Z7 .......
@N: CG364 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":10:7:10:10|Synthesizing module ddr3 in library work.
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":596:38:596:38|Input aclk_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":597:38:597:38|Input awid_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":598:38:598:38|Input awaddr_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":599:38:599:38|Input awlen_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":600:38:600:38|Input awsize_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":601:38:601:38|Input awburst_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":602:38:602:38|Input awlock_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":603:38:603:38|Input awvalid_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":605:38:605:38|Input awurgent_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":606:38:606:38|Input awpoison_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":607:38:607:38|Input wdata_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":608:38:608:38|Input wstrb_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":609:38:609:38|Input wlast_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":610:38:610:38|Input wvalid_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":615:38:615:38|Input bready_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":616:38:616:38|Input arid_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":617:38:617:38|Input araddr_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":618:38:618:38|Input arlen_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":619:38:619:38|Input arsize_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":620:38:620:38|Input arburst_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":621:38:621:38|Input arlock_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":622:38:622:38|Input arvalid_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":624:38:624:38|Input arurgent_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":625:38:625:38|Input arpoison_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":631:38:631:38|Input rready_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":638:38:638:38|Input csysreq_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":690:38:690:38|Input aclk_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":691:38:691:38|Input awid_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":692:38:692:38|Input awaddr_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":693:38:693:38|Input awlen_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":694:38:694:38|Input awsize_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":695:38:695:38|Input awburst_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":696:38:696:38|Input awlock_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":697:38:697:38|Input awvalid_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":699:38:699:38|Input awurgent_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":700:38:700:38|Input awpoison_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":701:38:701:38|Input wdata_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":702:38:702:38|Input wstrb_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":703:38:703:38|Input wlast_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":704:38:704:38|Input wvalid_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":709:38:709:38|Input bready_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":710:38:710:38|Input arid_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":711:38:711:38|Input araddr_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":712:38:712:38|Input arlen_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":713:38:713:38|Input arsize_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":714:38:714:38|Input arburst_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":715:38:715:38|Input arlock_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":716:38:716:38|Input arvalid_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":718:38:718:38|Input arurgent_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":719:38:719:38|Input arpoison_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":725:38:725:38|Input rready_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":733:38:733:38|Input csysreq_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":783:38:783:38|Input paddr on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":784:38:784:38|Input pwdata on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":785:38:785:38|Input pwrite on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":786:38:786:38|Input penable on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v":788:38:788:38|Input psel on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
Running optimization stage 1 on ddr3 .......
@N: CG364 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\ipsl_hmemc_top_test.v":5:7:5:25|Synthesizing module ipsl_hmemc_top_test in library work.
@W: CS263 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\ipsl_hmemc_top_test.v":241:23:241:23|Port-width mismatch for port ddrc_rst. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
@W: CS263 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\ipsl_hmemc_top_test.v":243:23:243:23|Port-width mismatch for port areset_1. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\ipsl_hmemc_top_test.v":52:13:52:49|Removing wire ddrphy_dbg, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\ipsl_hmemc_top_test.v":98:22:98:32|Removing wire axi_csysreq, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\ipsl_hmemc_top_test.v":99:22:99:32|Removing wire axi_csysack, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\ipsl_hmemc_top_test.v":100:22:100:32|Removing wire axi_cactive, as there is no assignment to it.
@W: CG360 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\ipsl_hmemc_top_test.v":102:22:102:29|Removing wire pll_pclk, as there is no assignment to it.
Running optimization stage 1 on ipsl_hmemc_top_test .......
Running optimization stage 2 on ipsl_hmemc_top_test .......
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\ipsl_hmemc_top_test.v":116:0:116:5|Optimizing register bit cnt[25] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\ipsl_hmemc_top_test.v":116:0:116:5|Optimizing register bit cnt[26] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\ipsl_hmemc_top_test.v":116:0:116:5|Pruning register bits 26 to 25 of cnt[26:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
Running optimization stage 2 on ddr3 .......
Running optimization stage 2 on ipsl_hmemc_ddrc_top_Z7 .......
@N: CL159 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_hmemc_ddrc_top.v":215:25:215:33|Input dfi_error is unused.
@N: CL159 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_hmemc_ddrc_top.v":216:25:216:38|Input dfi_error_info is unused.
Running optimization stage 2 on GTP_DDRC .......
Running optimization stage 2 on ipsl_ddrc_reset_ctrl_Z6 .......
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_reset_ctrl.v":86:0:86:5|Optimizing register bit rst_cnt[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_reset_ctrl.v":86:0:86:5|Optimizing register bit rst_cnt[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_reset_ctrl.v":86:0:86:5|Optimizing register bit rst_cnt[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_reset_ctrl.v":113:0:113:5|Optimizing register bit ddrc_rst_cnt[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_reset_ctrl.v":113:0:113:5|Optimizing register bit ddrc_rst_cnt[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_reset_ctrl.v":113:0:113:5|Optimizing register bit ddrc_rst_cnt[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_reset_ctrl.v":113:0:113:5|Pruning register bits 7 to 5 of ddrc_rst_cnt[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_reset_ctrl.v":86:0:86:5|Pruning register bits 7 to 5 of rst_cnt[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
Running optimization stage 2 on ipsl_ddrc_apb_reset_Z5 .......
@W: CL246 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_apb_reset.v":47:23:47:28|Input port bits 31 to 2 of prdata[31:0] are unused. Assign logic for all port bits or change the input port size.
Running optimization stage 2 on ipsl_hmemc_phy_top_Z4 .......
Running optimization stage 2 on GTP_IOBUFCO .......
Running optimization stage 2 on GTP_INV .......
Running optimization stage 2 on ipsl_phy_io_Z3 .......
@N: CL159 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":90:41:90:52|Input SRB_CORE_CLK is unused.
Running optimization stage 2 on GTP_OUTBUFTCO .......
Running optimization stage 2 on GTP_IOBUF .......
Running optimization stage 2 on GTP_OUTBUFT .......
Running optimization stage 2 on GTP_OUTBUF .......
Running optimization stage 2 on GTP_INBUFG .......
Running optimization stage 2 on GTP_ISERDES .......
Running optimization stage 2 on GTP_IODELAY .......
Running optimization stage 2 on GTP_OSERDES .......
Running optimization stage 2 on GTP_DDC_E1 .......
Running optimization stage 2 on GTP_IOCLKDIV .......
Running optimization stage 2 on GTP_IOCLKBUF .......
Running optimization stage 2 on GTP_DDRPHY .......
Running optimization stage 2 on GTP_DLL .......
Running optimization stage 2 on ipsl_ddrphy_update_ctrl_16BIT_2s_0s_1s_2s_3s_1 .......
@N: CL201 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":293:0:293:5|Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 2 reachable states with original encodings of:
   00
   10
@W: CL247 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":12:13:12:23|Input port bit 2 of update_mask[2:0] is unused

Running optimization stage 2 on ipsl_ddrphy_dll_update_ctrl .......
@N: CL201 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_dll_update_ctrl.v":36:0:36:5|Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
Running optimization stage 2 on ipsl_ddrphy_training_ctrl .......
Running optimization stage 2 on ipsl_ddrphy_reset_ctrl .......
@N: CL201 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_reset_ctrl.v":52:0:52:5|Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 11 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
   1001
   1010
Running optimization stage 2 on pll_50_400 .......
@W: CL156 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":120:9:120:13|*Input clkfb to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":123:9:123:13|*Input pfden to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":125:9:125:25|*Input clkout0_2pad_gate to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":126:9:126:20|*Input clkout1_gate to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":127:9:127:20|*Input clkout2_gate to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":128:9:128:20|*Input clkout3_gate to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":129:9:129:20|*Input clkout4_gate to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":130:9:130:20|*Input clkout5_gate to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":131:15:131:22|*Input dyn_idiv[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":132:15:132:23|*Input dyn_odiv0[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":133:15:133:23|*Input dyn_odiv1[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":134:15:134:23|*Input dyn_odiv2[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":135:15:135:23|*Input dyn_odiv3[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":136:15:136:23|*Input dyn_odiv4[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":137:15:137:22|*Input dyn_fdiv[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":138:15:138:23|*Input dyn_duty0[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":139:15:139:23|*Input dyn_duty1[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":140:15:140:23|*Input dyn_duty2[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":141:15:141:23|*Input dyn_duty3[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":142:15:142:23|*Input dyn_duty4[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":143:16:143:25|*Input dyn_phase0[2:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":144:16:144:25|*Input dyn_phase1[2:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":145:16:145:25|*Input dyn_phase2[2:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":146:16:146:25|*Input dyn_phase3[2:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":147:16:147:25|*Input dyn_phase4[2:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":143:16:143:25|*Input dyn_phase0[12:3] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":144:16:144:25|*Input dyn_phase1[12:3] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":145:16:145:25|*Input dyn_phase2[12:3] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":146:16:146:25|*Input dyn_phase3[12:3] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v":147:16:147:25|*Input dyn_phase4[12:3] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
Running optimization stage 2 on GTP_PLL_E1 .......
Running optimization stage 2 on test_rd_ctrl_64bit_28s_16s_10s_28s_1s_3s_0s_1s_2s .......
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":147:0:147:5|Optimizing register bit cnt_len[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":147:0:147:5|Optimizing register bit cnt_len[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":147:0:147:5|Optimizing register bit cnt_len[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":147:0:147:5|Pruning register bits 7 to 5 of cnt_len[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@N: CL201 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":94:0:94:5|Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 3 reachable states with original encodings of:
   000
   001
   010
@N: CL159 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":36:24:36:30|Input axi_rid is unused.
@N: CL159 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":37:24:37:32|Input axi_rlast is unused.
@N: CL159 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":40:24:40:32|Input axi_rresp is unused.
Running optimization stage 2 on test_wr_ctrl_64bit_Z2 .......
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":164:0:164:5|Optimizing register bit init_addr[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":164:0:164:5|Optimizing register bit init_addr[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":164:0:164:5|Optimizing register bit init_addr[30] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":164:0:164:5|Optimizing register bit init_addr[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Optimizing register bit axi_awaddr[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Optimizing register bit axi_awaddr[30] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Optimizing register bit axi_awaddr[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":164:0:164:5|Optimizing register bit cnt_len[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":164:0:164:5|Optimizing register bit cnt_len[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":164:0:164:5|Optimizing register bit cnt_len[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":164:0:164:5|Pruning register bits 7 to 5 of cnt_len[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Pruning register bits 31 to 30 of axi_awaddr[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL260 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Pruning register bit 0 of axi_awaddr[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL279 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":164:0:164:5|Pruning register bits 31 to 30 of init_addr[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":164:0:164:5|Pruning register bits 1 to 0 of init_addr[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@N: CL201 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 3 reachable states with original encodings of:
   0000
   0001
   0010
@N: CL159 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":40:41:40:47|Input axi_bid is unused.
@N: CL159 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":41:41:41:49|Input axi_bresp is unused.
@N: CL159 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":42:41:42:50|Input axi_bvalid is unused.
Running optimization stage 2 on test_main_ctrl_28s_16s_28s_0s_1s_2s_3s_4s .......
@N: CL201 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_main_ctrl.v":38:0:38:5|Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 5 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
Running optimization stage 2 on prbs31_128bit_1_Z1 .......
@N: CL159 :"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":20:14:20:16|Input din is unused.

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
@L: D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\synthesize\synplify_impl\synwork\layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 100MB peak: 108MB)

Process took 0h:00m:03s realtime, 0h:00m:03s cputime

Process completed successfully.
# Tue May  7 10:00:02 2019

###########################################################]
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03P-Beta2
Install: C:\pango\PDS_2019.1-patch2\syn
OS: Windows 6.1

Hostname: ALINX000007-PC

Implementation : synplify_impl
Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 007R, Built Feb 26 2019 11:45:06

@N|Running in 64-bit mode

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 93MB peak: 93MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue May  7 10:00:02 2019

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\synthesize\synplify_impl\synwork\synplify_comp.rt.csv

@END

At c_hdl Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 18MB peak: 18MB)

Process took 0h:00m:03s realtime, 0h:00m:03s cputime

Process completed successfully.
# Tue May  7 10:00:02 2019

###########################################################]
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03P-Beta2
Install: C:\pango\PDS_2019.1-patch2\syn
OS: Windows 6.1

Hostname: ALINX000007-PC

Implementation : synplify_impl
Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 007R, Built Feb 26 2019 11:45:06

@N|Running in 64-bit mode

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 95MB peak: 95MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue May  7 10:00:03 2019

###########################################################]
Premap Report

# Tue May  7 10:00:04 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03P-Beta2
Install: C:\pango\PDS_2019.1-patch2\syn
OS: Windows 6.1

Hostname: ALINX000007-PC

Implementation : synplify_impl
Synopsys Generic Technology Pre-mapping, Version map2019q1p1, Build 1238R, Built Mar 15 2019 09:38:46


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

Reading constraint file: D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\ddr_324_left.fdc
@L: D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\synthesize\synplify_impl\synplify_scck.rpt 
Printing clock  summary report in "D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\synthesize\synplify_impl\synplify_scck.rpt" file 
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 136MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 136MB)

Adding property PAP_IO_DIRECTION, value "Input", to port resetn
Adding property PAP_IO_LOC, value "B3", to port resetn
Adding property PAP_IO_VCCIO, value 3.3, to port resetn
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port resetn
Adding property PAP_IO_PULLUP, value "TRUE", to port resetn
Adding property PAP_IO_HYS_DRIVE_MODE, value "NOHYS", to port resetn
Adding property PAP_IO_DIRECTION, value "Input", to port pll_refclk_in
Adding property PAP_IO_LOC, value "B5", to port pll_refclk_in
Adding property PAP_IO_VCCIO, value 3.3, to port pll_refclk_in
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port pll_refclk_in
Adding property PAP_IO_UNUSED, value "TRUE", to port pll_refclk_in
Adding property PAP_IO_HYS_DRIVE_MODE, value "NOHYS", to port pll_refclk_in
Adding property PAP_IO_DIRECTION, value "Output", to port clk_led
Adding property PAP_IO_LOC, value "A3", to port clk_led
Adding property PAP_IO_VCCIO, value 3.3, to port clk_led
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port clk_led
Adding property PAP_IO_SLEW, value "FAST", to port clk_led
Adding property PAP_IO_DRIVE, value 4, to port clk_led
Adding property PAP_IO_PULLUP, value "TRUE", to port clk_led
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port clk_led
Adding property PAP_IO_DIRECTION, value "Output", to port pll_lock
Adding property PAP_IO_LOC, value "B4", to port pll_lock
Adding property PAP_IO_VCCIO, value 3.3, to port pll_lock
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port pll_lock
Adding property PAP_IO_SLEW, value "FAST", to port pll_lock
Adding property PAP_IO_DRIVE, value 4, to port pll_lock
Adding property PAP_IO_PULLUP, value "TRUE", to port pll_lock
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port pll_lock
Adding property PAP_IO_DIRECTION, value "Output", to port ddr_init_done
Adding property PAP_IO_LOC, value "B2", to port ddr_init_done
Adding property PAP_IO_VCCIO, value 3.3, to port ddr_init_done
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port ddr_init_done
Adding property PAP_IO_SLEW, value "FAST", to port ddr_init_done
Adding property PAP_IO_DRIVE, value 4, to port ddr_init_done
Adding property PAP_IO_PULLUP, value "TRUE", to port ddr_init_done
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port ddr_init_done
Adding property PAP_IO_DIRECTION, value "Output", to port ddrphy_rst_done
Adding property PAP_IO_LOC, value "A2", to port ddrphy_rst_done
Adding property PAP_IO_VCCIO, value 3.3, to port ddrphy_rst_done
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port ddrphy_rst_done
Adding property PAP_IO_SLEW, value "FAST", to port ddrphy_rst_done
Adding property PAP_IO_DRIVE, value 4, to port ddrphy_rst_done
Adding property PAP_IO_PULLUP, value "TRUE", to port ddrphy_rst_done
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port ddrphy_rst_done
Adding property PAP_IO_DIRECTION, value "Input", to port pad_loop_in
Adding property PAP_IO_LOC, value "P7", to port pad_loop_in
Adding property PAP_IO_VCCIO, value 1.5, to port pad_loop_in
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_loop_in
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_loop_in
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_loop_in
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_loop_in
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_loop_in
Adding property PAP_IO_DIRECTION, value "Input", to port pad_loop_in_h
Adding property PAP_IO_LOC, value "V4", to port pad_loop_in_h
Adding property PAP_IO_VCCIO, value 1.5, to port pad_loop_in_h
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_loop_in_h
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_loop_in_h
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_loop_in_h
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_loop_in_h
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_loop_in_h
Adding property PAP_IO_DIRECTION, value "Output", to port pad_rstn_ch0
Adding property PAP_IO_LOC, value "M2", to port pad_rstn_ch0
Adding property PAP_IO_VCCIO, value 1.5, to port pad_rstn_ch0
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_rstn_ch0
Adding property PAP_IO_SLEW, value "FAST", to port pad_rstn_ch0
Adding property PAP_IO_DRIVE, value 7.5, to port pad_rstn_ch0
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_rstn_ch0
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ddr_clk_w
Adding property PAP_IO_LOC, value "U3", to port pad_ddr_clk_w
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ddr_clk_w
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_ddr_clk_w
Adding property PAP_IO_SLEW, value "FAST", to port pad_ddr_clk_w
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ddr_clk_w
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ddr_clk_w
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ddr_clkn_w
Adding property PAP_IO_LOC, value "V3", to port pad_ddr_clkn_w
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ddr_clkn_w
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_ddr_clkn_w
Adding property PAP_IO_SLEW, value "FAST", to port pad_ddr_clkn_w
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ddr_clkn_w
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ddr_clkn_w
Adding property PAP_IO_DIRECTION, value "Output", to port pad_csn_ch0
Adding property PAP_IO_LOC, value "R1", to port pad_csn_ch0
Adding property PAP_IO_VCCIO, value 1.5, to port pad_csn_ch0
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_csn_ch0
Adding property PAP_IO_SLEW, value "FAST", to port pad_csn_ch0
Adding property PAP_IO_DRIVE, value 7.5, to port pad_csn_ch0
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_csn_ch0
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[0]
Adding property PAP_IO_LOC, value "M4", to port pad_addr_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[10]
Adding property PAP_IO_LOC, value "M6", to port pad_addr_ch0[10]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[10]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[10]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[10]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[10]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[10]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[11]
Adding property PAP_IO_LOC, value "L1", to port pad_addr_ch0[11]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[11]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[11]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[11]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[11]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[11]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[12]
Adding property PAP_IO_LOC, value "K2", to port pad_addr_ch0[12]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[12]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[12]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[12]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[12]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[12]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[13]
Adding property PAP_IO_LOC, value "K1", to port pad_addr_ch0[13]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[13]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[13]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[13]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[13]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[13]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[14]
Adding property PAP_IO_LOC, value "J2", to port pad_addr_ch0[14]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[14]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[14]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[14]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[14]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[14]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[15]
Adding property PAP_IO_LOC, value "J1", to port pad_addr_ch0[15]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[15]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[15]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[15]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[15]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[15]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[1]
Adding property PAP_IO_LOC, value "M3", to port pad_addr_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[2]
Adding property PAP_IO_LOC, value "P2", to port pad_addr_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[2]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[3]
Adding property PAP_IO_LOC, value "P1", to port pad_addr_ch0[3]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[3]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[3]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[3]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[3]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[3]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[4]
Adding property PAP_IO_LOC, value "L5", to port pad_addr_ch0[4]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[4]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[4]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[4]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[4]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[4]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[5]
Adding property PAP_IO_LOC, value "M5", to port pad_addr_ch0[5]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[5]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[5]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[5]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[5]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[5]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[6]
Adding property PAP_IO_LOC, value "N2", to port pad_addr_ch0[6]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[6]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[6]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[6]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[6]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[6]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[7]
Adding property PAP_IO_LOC, value "N1", to port pad_addr_ch0[7]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[7]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[7]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[7]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[7]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[7]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[8]
Adding property PAP_IO_LOC, value "K4", to port pad_addr_ch0[8]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[8]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[8]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[8]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[8]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[8]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[9]
Adding property PAP_IO_LOC, value "M1", to port pad_addr_ch0[9]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[9]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[9]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[9]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[9]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[9]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[0]
Adding property PAP_IO_LOC, value "T8", to port pad_dq_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[0]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[0]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[10]
Adding property PAP_IO_LOC, value "U9", to port pad_dq_ch0[10]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[10]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[10]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[10]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[10]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[10]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[10]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[10]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[10]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[11]
Adding property PAP_IO_LOC, value "V7", to port pad_dq_ch0[11]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[11]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[11]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[11]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[11]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[11]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[11]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[11]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[11]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[12]
Adding property PAP_IO_LOC, value "U7", to port pad_dq_ch0[12]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[12]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[12]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[12]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[12]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[12]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[12]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[12]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[12]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[13]
Adding property PAP_IO_LOC, value "V6", to port pad_dq_ch0[13]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[13]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[13]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[13]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[13]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[13]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[13]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[13]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[13]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[14]
Adding property PAP_IO_LOC, value "U6", to port pad_dq_ch0[14]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[14]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[14]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[14]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[14]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[14]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[14]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[14]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[14]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[15]
Adding property PAP_IO_LOC, value "V5", to port pad_dq_ch0[15]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[15]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[15]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[15]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[15]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[15]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[15]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[15]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[15]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[1]
Adding property PAP_IO_LOC, value "T6", to port pad_dq_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[1]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[1]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[1]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[2]
Adding property PAP_IO_LOC, value "R6", to port pad_dq_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[2]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[2]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[2]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[2]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[3]
Adding property PAP_IO_LOC, value "R9", to port pad_dq_ch0[3]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[3]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[3]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[3]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[3]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[3]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[3]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[3]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[3]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[4]
Adding property PAP_IO_LOC, value "T9", to port pad_dq_ch0[4]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[4]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[4]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[4]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[4]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[4]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[4]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[4]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[4]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[5]
Adding property PAP_IO_LOC, value "N4", to port pad_dq_ch0[5]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[5]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[5]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[5]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[5]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[5]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[5]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[5]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[5]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[6]
Adding property PAP_IO_LOC, value "N5", to port pad_dq_ch0[6]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[6]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[6]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[6]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[6]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[6]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[6]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[6]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[6]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[7]
Adding property PAP_IO_LOC, value "P6", to port pad_dq_ch0[7]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[7]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[7]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[7]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[7]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[7]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[7]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[7]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[7]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[8]
Adding property PAP_IO_LOC, value "T4", to port pad_dq_ch0[8]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[8]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[8]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[8]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[8]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[8]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[8]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[8]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[8]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[9]
Adding property PAP_IO_LOC, value "V9", to port pad_dq_ch0[9]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[9]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[9]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[9]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[9]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[9]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[9]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[9]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[9]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqs_ch0[0]
Adding property PAP_IO_LOC, value "N6", to port pad_dqs_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqs_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqs_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqs_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqs_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqs_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqs_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqs_ch0[1]
Adding property PAP_IO_LOC, value "U8", to port pad_dqs_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqs_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqs_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqs_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqs_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqs_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqs_ch0[1]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqsn_ch0[0]
Adding property PAP_IO_LOC, value "N7", to port pad_dqsn_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqsn_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqsn_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqsn_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqsn_ch0[1]
Adding property PAP_IO_LOC, value "V8", to port pad_dqsn_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqsn_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqsn_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqsn_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_LOC, value "R8", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_LOC, value "U5", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_cke_ch0
Adding property PAP_IO_LOC, value "L4", to port pad_cke_ch0
Adding property PAP_IO_VCCIO, value 1.5, to port pad_cke_ch0
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_cke_ch0
Adding property PAP_IO_SLEW, value "FAST", to port pad_cke_ch0
Adding property PAP_IO_DRIVE, value 7.5, to port pad_cke_ch0
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_cke_ch0
Adding property PAP_IO_DIRECTION, value "Output", to port pad_odt_ch0
Adding property PAP_IO_LOC, value "V2", to port pad_odt_ch0
Adding property PAP_IO_VCCIO, value 1.5, to port pad_odt_ch0
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_odt_ch0
Adding property PAP_IO_SLEW, value "FAST", to port pad_odt_ch0
Adding property PAP_IO_DRIVE, value 7.5, to port pad_odt_ch0
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_odt_ch0
Adding property PAP_IO_DIRECTION, value "Output", to port pad_rasn_ch0
Adding property PAP_IO_LOC, value "R2", to port pad_rasn_ch0
Adding property PAP_IO_VCCIO, value 1.5, to port pad_rasn_ch0
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_rasn_ch0
Adding property PAP_IO_SLEW, value "FAST", to port pad_rasn_ch0
Adding property PAP_IO_DRIVE, value 7.5, to port pad_rasn_ch0
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_rasn_ch0
Adding property PAP_IO_DIRECTION, value "Output", to port pad_casn_ch0
Adding property PAP_IO_LOC, value "T1", to port pad_casn_ch0
Adding property PAP_IO_VCCIO, value 1.5, to port pad_casn_ch0
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_casn_ch0
Adding property PAP_IO_SLEW, value "FAST", to port pad_casn_ch0
Adding property PAP_IO_DRIVE, value 7.5, to port pad_casn_ch0
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_casn_ch0
Adding property PAP_IO_DIRECTION, value "Output", to port pad_wen_ch0
Adding property PAP_IO_LOC, value "V1", to port pad_wen_ch0
Adding property PAP_IO_VCCIO, value 1.5, to port pad_wen_ch0
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_wen_ch0
Adding property PAP_IO_SLEW, value "FAST", to port pad_wen_ch0
Adding property PAP_IO_DRIVE, value 7.5, to port pad_wen_ch0
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_wen_ch0
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[0]
Adding property PAP_IO_LOC, value "U2", to port pad_ba_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[1]
Adding property PAP_IO_LOC, value "U1", to port pad_ba_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[2]
Adding property PAP_IO_LOC, value "T2", to port pad_ba_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[2]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_loop_out
Adding property PAP_IO_LOC, value "P8", to port pad_loop_out
Adding property PAP_IO_VCCIO, value 1.5, to port pad_loop_out
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_loop_out
Adding property PAP_IO_SLEW, value "FAST", to port pad_loop_out
Adding property PAP_IO_DRIVE, value 7.5, to port pad_loop_out
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_loop_out
Adding property PAP_IO_DIRECTION, value "Output", to port pad_loop_out_h
Adding property PAP_IO_LOC, value "U4", to port pad_loop_out_h
Adding property PAP_IO_VCCIO, value 1.5, to port pad_loop_out_h
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_loop_out_h
Adding property PAP_IO_SLEW, value "FAST", to port pad_loop_out_h
Adding property PAP_IO_DRIVE, value 7.5, to port pad_loop_out_h
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_loop_out_h
Adding property PAP_IO_DIRECTION, value "Output", to port err_flag
Adding property PAP_IO_LOC, value "B1", to port err_flag
Adding property PAP_IO_VCCIO, value 3.3, to port err_flag
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port err_flag
Adding property PAP_IO_SLEW, value "FAST", to port err_flag
Adding property PAP_IO_DRIVE, value 4, to port err_flag
Adding property PAP_IO_PULLUP, value "TRUE", to port err_flag
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port err_flag
Adding property PAP_LOC, value "PLL_82_71", to instance u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1

Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 137MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 139MB)

@N: MO111 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":175:41:175:51|Tristate driver DQS_DRIFT_H_1 (in view: work.ipsl_phy_io_Z3(verilog)) on net DQS_DRIFT_H_1 (in view: work.ipsl_phy_io_Z3(verilog)) has its enable tied to GND.
@N: MO111 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":175:41:175:51|Tristate driver DQS_DRIFT_H_2 (in view: work.ipsl_phy_io_Z3(verilog)) on net DQS_DRIFT_H_2 (in view: work.ipsl_phy_io_Z3(verilog)) has its enable tied to GND.
@N: MO111 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":174:41:174:51|Tristate driver DQS_DRIFT_L_1 (in view: work.ipsl_phy_io_Z3(verilog)) on net DQS_DRIFT_L_1 (in view: work.ipsl_phy_io_Z3(verilog)) has its enable tied to GND.
@N: MO111 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":174:41:174:51|Tristate driver DQS_DRIFT_L_2 (in view: work.ipsl_phy_io_Z3(verilog)) on net DQS_DRIFT_L_2 (in view: work.ipsl_phy_io_Z3(verilog)) has its enable tied to GND.
@N: MO111 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":100:41:100:47|Tristate driver PSLVERR (in view: work.ipsl_phy_io_Z3(verilog)) on net PSLVERR (in view: work.ipsl_phy_io_Z3(verilog)) has its enable tied to GND.
@N: BN115 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":284:1:284:6|Removing instance u_prbs (in view: work.test_wr_ctrl_64bit_Z2(verilog)) of type view:work.prbs31_128bit_1_Z1_0(verilog) because it does not drive other instances.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_reset_ctrl.v":141:0:141:5|Removing sequential instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_ddrphy_reset_ctrl.srb_ioclkdiv_rstn because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_ddrphy_reset_ctrl.srb_dqs_rstn. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_reset_ctrl.v":125:0:125:5|Removing sequential instance u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.init_axi_reset2 because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.init_ddrc_rst. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_reset_ctrl.v":125:0:125:5|Removing sequential instance u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.init_axi_reset1 because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.init_ddrc_rst. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_reset_ctrl.v":125:0:125:5|Removing sequential instance u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.init_axi_reset0 because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.init_ddrc_rst. To keep the instance, apply constraint syn_preserve=1 on the instance.
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[0]
Adding property PAP_IO_LOC, value "M4", to port pad_addr_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[10]
Adding property PAP_IO_LOC, value "M6", to port pad_addr_ch0[10]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[10]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[10]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[10]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[10]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[10]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[11]
Adding property PAP_IO_LOC, value "L1", to port pad_addr_ch0[11]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[11]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[11]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[11]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[11]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[11]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[12]
Adding property PAP_IO_LOC, value "K2", to port pad_addr_ch0[12]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[12]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[12]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[12]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[12]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[12]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[13]
Adding property PAP_IO_LOC, value "K1", to port pad_addr_ch0[13]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[13]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[13]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[13]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[13]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[13]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[14]
Adding property PAP_IO_LOC, value "J2", to port pad_addr_ch0[14]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[14]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[14]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[14]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[14]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[14]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[15]
Adding property PAP_IO_LOC, value "J1", to port pad_addr_ch0[15]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[15]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[15]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[15]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[15]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[15]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[1]
Adding property PAP_IO_LOC, value "M3", to port pad_addr_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[2]
Adding property PAP_IO_LOC, value "P2", to port pad_addr_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[2]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[3]
Adding property PAP_IO_LOC, value "P1", to port pad_addr_ch0[3]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[3]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[3]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[3]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[3]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[3]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[4]
Adding property PAP_IO_LOC, value "L5", to port pad_addr_ch0[4]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[4]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[4]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[4]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[4]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[4]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[5]
Adding property PAP_IO_LOC, value "M5", to port pad_addr_ch0[5]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[5]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[5]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[5]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[5]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[5]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[6]
Adding property PAP_IO_LOC, value "N2", to port pad_addr_ch0[6]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[6]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[6]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[6]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[6]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[6]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[7]
Adding property PAP_IO_LOC, value "N1", to port pad_addr_ch0[7]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[7]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[7]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[7]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[7]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[7]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[8]
Adding property PAP_IO_LOC, value "K4", to port pad_addr_ch0[8]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[8]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[8]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[8]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[8]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[8]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[9]
Adding property PAP_IO_LOC, value "M1", to port pad_addr_ch0[9]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[9]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[9]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[9]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[9]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[9]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[0]
Adding property PAP_IO_LOC, value "T8", to port pad_dq_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[0]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[0]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[10]
Adding property PAP_IO_LOC, value "U9", to port pad_dq_ch0[10]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[10]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[10]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[10]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[10]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[10]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[10]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[10]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[10]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[11]
Adding property PAP_IO_LOC, value "V7", to port pad_dq_ch0[11]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[11]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[11]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[11]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[11]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[11]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[11]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[11]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[11]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[12]
Adding property PAP_IO_LOC, value "U7", to port pad_dq_ch0[12]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[12]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[12]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[12]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[12]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[12]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[12]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[12]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[12]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[13]
Adding property PAP_IO_LOC, value "V6", to port pad_dq_ch0[13]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[13]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[13]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[13]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[13]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[13]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[13]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[13]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[13]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[14]
Adding property PAP_IO_LOC, value "U6", to port pad_dq_ch0[14]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[14]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[14]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[14]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[14]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[14]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[14]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[14]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[14]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[15]
Adding property PAP_IO_LOC, value "V5", to port pad_dq_ch0[15]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[15]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[15]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[15]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[15]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[15]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[15]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[15]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[15]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[1]
Adding property PAP_IO_LOC, value "T6", to port pad_dq_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[1]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[1]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[1]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[2]
Adding property PAP_IO_LOC, value "R6", to port pad_dq_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[2]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[2]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[2]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[2]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[3]
Adding property PAP_IO_LOC, value "R9", to port pad_dq_ch0[3]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[3]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[3]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[3]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[3]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[3]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[3]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[3]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[3]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[4]
Adding property PAP_IO_LOC, value "T9", to port pad_dq_ch0[4]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[4]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[4]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[4]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[4]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[4]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[4]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[4]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[4]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[5]
Adding property PAP_IO_LOC, value "N4", to port pad_dq_ch0[5]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[5]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[5]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[5]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[5]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[5]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[5]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[5]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[5]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[6]
Adding property PAP_IO_LOC, value "N5", to port pad_dq_ch0[6]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[6]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[6]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[6]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[6]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[6]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[6]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[6]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[6]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[7]
Adding property PAP_IO_LOC, value "P6", to port pad_dq_ch0[7]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[7]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[7]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[7]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[7]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[7]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[7]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[7]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[7]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[8]
Adding property PAP_IO_LOC, value "T4", to port pad_dq_ch0[8]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[8]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[8]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[8]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[8]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[8]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[8]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[8]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[8]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[9]
Adding property PAP_IO_LOC, value "V9", to port pad_dq_ch0[9]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[9]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[9]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[9]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[9]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[9]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[9]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[9]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[9]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqs_ch0[0]
Adding property PAP_IO_LOC, value "N6", to port pad_dqs_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqs_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqs_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqs_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqs_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqs_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqs_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqs_ch0[1]
Adding property PAP_IO_LOC, value "U8", to port pad_dqs_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqs_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqs_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqs_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqs_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqs_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqs_ch0[1]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqsn_ch0[0]
Adding property PAP_IO_LOC, value "N7", to port pad_dqsn_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqsn_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqsn_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqsn_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqsn_ch0[1]
Adding property PAP_IO_LOC, value "V8", to port pad_dqsn_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqsn_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqsn_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqsn_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_LOC, value "R8", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_LOC, value "U5", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[0]
Adding property PAP_IO_LOC, value "U2", to port pad_ba_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[1]
Adding property PAP_IO_LOC, value "U1", to port pad_ba_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[2]
Adding property PAP_IO_LOC, value "T2", to port pad_ba_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[2]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[0]
Adding property PAP_IO_LOC, value "M4", to port pad_addr_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[10]
Adding property PAP_IO_LOC, value "M6", to port pad_addr_ch0[10]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[10]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[10]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[10]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[10]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[10]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[11]
Adding property PAP_IO_LOC, value "L1", to port pad_addr_ch0[11]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[11]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[11]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[11]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[11]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[11]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[12]
Adding property PAP_IO_LOC, value "K2", to port pad_addr_ch0[12]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[12]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[12]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[12]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[12]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[12]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[13]
Adding property PAP_IO_LOC, value "K1", to port pad_addr_ch0[13]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[13]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[13]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[13]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[13]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[13]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[14]
Adding property PAP_IO_LOC, value "J2", to port pad_addr_ch0[14]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[14]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[14]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[14]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[14]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[14]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[15]
Adding property PAP_IO_LOC, value "J1", to port pad_addr_ch0[15]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[15]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[15]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[15]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[15]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[15]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[1]
Adding property PAP_IO_LOC, value "M3", to port pad_addr_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[2]
Adding property PAP_IO_LOC, value "P2", to port pad_addr_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[2]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[3]
Adding property PAP_IO_LOC, value "P1", to port pad_addr_ch0[3]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[3]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[3]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[3]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[3]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[3]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[4]
Adding property PAP_IO_LOC, value "L5", to port pad_addr_ch0[4]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[4]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[4]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[4]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[4]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[4]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[5]
Adding property PAP_IO_LOC, value "M5", to port pad_addr_ch0[5]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[5]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[5]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[5]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[5]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[5]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[6]
Adding property PAP_IO_LOC, value "N2", to port pad_addr_ch0[6]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[6]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[6]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[6]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[6]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[6]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[7]
Adding property PAP_IO_LOC, value "N1", to port pad_addr_ch0[7]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[7]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[7]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[7]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[7]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[7]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[8]
Adding property PAP_IO_LOC, value "K4", to port pad_addr_ch0[8]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[8]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[8]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[8]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[8]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[8]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[9]
Adding property PAP_IO_LOC, value "M1", to port pad_addr_ch0[9]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[9]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[9]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[9]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[9]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[9]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[0]
Adding property PAP_IO_LOC, value "T8", to port pad_dq_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[0]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[0]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[10]
Adding property PAP_IO_LOC, value "U9", to port pad_dq_ch0[10]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[10]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[10]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[10]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[10]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[10]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[10]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[10]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[10]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[11]
Adding property PAP_IO_LOC, value "V7", to port pad_dq_ch0[11]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[11]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[11]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[11]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[11]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[11]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[11]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[11]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[11]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[12]
Adding property PAP_IO_LOC, value "U7", to port pad_dq_ch0[12]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[12]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[12]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[12]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[12]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[12]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[12]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[12]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[12]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[13]
Adding property PAP_IO_LOC, value "V6", to port pad_dq_ch0[13]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[13]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[13]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[13]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[13]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[13]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[13]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[13]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[13]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[14]
Adding property PAP_IO_LOC, value "U6", to port pad_dq_ch0[14]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[14]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[14]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[14]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[14]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[14]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[14]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[14]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[14]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[15]
Adding property PAP_IO_LOC, value "V5", to port pad_dq_ch0[15]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[15]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[15]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[15]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[15]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[15]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[15]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[15]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[15]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[1]
Adding property PAP_IO_LOC, value "T6", to port pad_dq_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[1]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[1]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[1]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[2]
Adding property PAP_IO_LOC, value "R6", to port pad_dq_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[2]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[2]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[2]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[2]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[3]
Adding property PAP_IO_LOC, value "R9", to port pad_dq_ch0[3]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[3]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[3]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[3]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[3]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[3]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[3]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[3]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[3]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[4]
Adding property PAP_IO_LOC, value "T9", to port pad_dq_ch0[4]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[4]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[4]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[4]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[4]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[4]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[4]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[4]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[4]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[5]
Adding property PAP_IO_LOC, value "N4", to port pad_dq_ch0[5]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[5]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[5]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[5]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[5]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[5]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[5]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[5]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[5]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[6]
Adding property PAP_IO_LOC, value "N5", to port pad_dq_ch0[6]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[6]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[6]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[6]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[6]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[6]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[6]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[6]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[6]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[7]
Adding property PAP_IO_LOC, value "P6", to port pad_dq_ch0[7]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[7]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[7]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[7]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[7]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[7]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[7]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[7]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[7]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[8]
Adding property PAP_IO_LOC, value "T4", to port pad_dq_ch0[8]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[8]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[8]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[8]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[8]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[8]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[8]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[8]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[8]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[9]
Adding property PAP_IO_LOC, value "V9", to port pad_dq_ch0[9]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[9]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[9]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[9]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[9]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[9]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[9]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[9]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[9]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqs_ch0[0]
Adding property PAP_IO_LOC, value "N6", to port pad_dqs_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqs_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqs_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqs_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqs_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqs_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqs_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqs_ch0[1]
Adding property PAP_IO_LOC, value "U8", to port pad_dqs_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqs_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqs_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqs_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqs_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqs_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqs_ch0[1]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqsn_ch0[0]
Adding property PAP_IO_LOC, value "N7", to port pad_dqsn_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqsn_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqsn_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqsn_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqsn_ch0[1]
Adding property PAP_IO_LOC, value "V8", to port pad_dqsn_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqsn_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqsn_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqsn_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_LOC, value "R8", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_LOC, value "U5", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[0]
Adding property PAP_IO_LOC, value "U2", to port pad_ba_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[1]
Adding property PAP_IO_LOC, value "U1", to port pad_ba_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[2]
Adding property PAP_IO_LOC, value "T2", to port pad_ba_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[2]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[0]
Adding property PAP_IO_LOC, value "M4", to port pad_addr_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[10]
Adding property PAP_IO_LOC, value "M6", to port pad_addr_ch0[10]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[10]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[10]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[10]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[10]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[10]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[11]
Adding property PAP_IO_LOC, value "L1", to port pad_addr_ch0[11]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[11]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[11]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[11]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[11]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[11]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[12]
Adding property PAP_IO_LOC, value "K2", to port pad_addr_ch0[12]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[12]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[12]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[12]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[12]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[12]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[13]
Adding property PAP_IO_LOC, value "K1", to port pad_addr_ch0[13]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[13]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[13]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[13]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[13]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[13]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[14]
Adding property PAP_IO_LOC, value "J2", to port pad_addr_ch0[14]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[14]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[14]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[14]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[14]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[14]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[15]
Adding property PAP_IO_LOC, value "J1", to port pad_addr_ch0[15]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[15]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[15]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[15]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[15]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[15]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[1]
Adding property PAP_IO_LOC, value "M3", to port pad_addr_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[2]
Adding property PAP_IO_LOC, value "P2", to port pad_addr_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[2]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[3]
Adding property PAP_IO_LOC, value "P1", to port pad_addr_ch0[3]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[3]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[3]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[3]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[3]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[3]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[4]
Adding property PAP_IO_LOC, value "L5", to port pad_addr_ch0[4]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[4]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[4]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[4]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[4]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[4]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[5]
Adding property PAP_IO_LOC, value "M5", to port pad_addr_ch0[5]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[5]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[5]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[5]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[5]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[5]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[6]
Adding property PAP_IO_LOC, value "N2", to port pad_addr_ch0[6]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[6]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[6]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[6]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[6]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[6]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[7]
Adding property PAP_IO_LOC, value "N1", to port pad_addr_ch0[7]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[7]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[7]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[7]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[7]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[7]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[8]
Adding property PAP_IO_LOC, value "K4", to port pad_addr_ch0[8]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[8]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[8]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[8]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[8]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[8]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[9]
Adding property PAP_IO_LOC, value "M1", to port pad_addr_ch0[9]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[9]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[9]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[9]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[9]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[9]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[0]
Adding property PAP_IO_LOC, value "T8", to port pad_dq_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[0]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[0]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[10]
Adding property PAP_IO_LOC, value "U9", to port pad_dq_ch0[10]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[10]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[10]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[10]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[10]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[10]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[10]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[10]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[10]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[11]
Adding property PAP_IO_LOC, value "V7", to port pad_dq_ch0[11]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[11]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[11]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[11]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[11]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[11]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[11]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[11]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[11]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[12]
Adding property PAP_IO_LOC, value "U7", to port pad_dq_ch0[12]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[12]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[12]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[12]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[12]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[12]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[12]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[12]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[12]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[13]
Adding property PAP_IO_LOC, value "V6", to port pad_dq_ch0[13]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[13]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[13]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[13]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[13]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[13]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[13]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[13]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[13]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[14]
Adding property PAP_IO_LOC, value "U6", to port pad_dq_ch0[14]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[14]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[14]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[14]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[14]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[14]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[14]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[14]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[14]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[15]
Adding property PAP_IO_LOC, value "V5", to port pad_dq_ch0[15]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[15]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[15]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[15]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[15]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[15]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[15]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[15]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[15]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[1]
Adding property PAP_IO_LOC, value "T6", to port pad_dq_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[1]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[1]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[1]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[2]
Adding property PAP_IO_LOC, value "R6", to port pad_dq_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[2]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[2]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[2]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[2]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[3]
Adding property PAP_IO_LOC, value "R9", to port pad_dq_ch0[3]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[3]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[3]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[3]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[3]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[3]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[3]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[3]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[3]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[4]
Adding property PAP_IO_LOC, value "T9", to port pad_dq_ch0[4]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[4]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[4]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[4]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[4]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[4]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[4]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[4]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[4]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[5]
Adding property PAP_IO_LOC, value "N4", to port pad_dq_ch0[5]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[5]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[5]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[5]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[5]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[5]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[5]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[5]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[5]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[6]
Adding property PAP_IO_LOC, value "N5", to port pad_dq_ch0[6]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[6]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[6]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[6]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[6]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[6]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[6]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[6]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[6]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[7]
Adding property PAP_IO_LOC, value "P6", to port pad_dq_ch0[7]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[7]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[7]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[7]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[7]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[7]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[7]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[7]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[7]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[8]
Adding property PAP_IO_LOC, value "T4", to port pad_dq_ch0[8]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[8]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[8]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[8]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[8]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[8]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[8]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[8]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[8]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[9]
Adding property PAP_IO_LOC, value "V9", to port pad_dq_ch0[9]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[9]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[9]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[9]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[9]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[9]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[9]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[9]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[9]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqs_ch0[0]
Adding property PAP_IO_LOC, value "N6", to port pad_dqs_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqs_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqs_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqs_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqs_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqs_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqs_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqs_ch0[1]
Adding property PAP_IO_LOC, value "U8", to port pad_dqs_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqs_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqs_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqs_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqs_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqs_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqs_ch0[1]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqsn_ch0[0]
Adding property PAP_IO_LOC, value "N7", to port pad_dqsn_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqsn_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqsn_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqsn_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqsn_ch0[1]
Adding property PAP_IO_LOC, value "V8", to port pad_dqsn_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqsn_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqsn_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqsn_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_LOC, value "R8", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_LOC, value "U5", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[0]
Adding property PAP_IO_LOC, value "U2", to port pad_ba_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[1]
Adding property PAP_IO_LOC, value "U1", to port pad_ba_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[2]
Adding property PAP_IO_LOC, value "T2", to port pad_ba_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[2]
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":174:0:174:5|Removing sequential instance error (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y_all[128:1] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffpatre(prim) because it does not drive other instances.
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[0]
Adding property PAP_IO_LOC, value "M4", to port pad_addr_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[10]
Adding property PAP_IO_LOC, value "M6", to port pad_addr_ch0[10]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[10]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[10]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[10]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[10]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[10]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[11]
Adding property PAP_IO_LOC, value "L1", to port pad_addr_ch0[11]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[11]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[11]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[11]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[11]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[11]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[12]
Adding property PAP_IO_LOC, value "K2", to port pad_addr_ch0[12]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[12]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[12]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[12]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[12]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[12]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[13]
Adding property PAP_IO_LOC, value "K1", to port pad_addr_ch0[13]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[13]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[13]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[13]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[13]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[13]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[14]
Adding property PAP_IO_LOC, value "J2", to port pad_addr_ch0[14]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[14]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[14]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[14]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[14]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[14]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[15]
Adding property PAP_IO_LOC, value "J1", to port pad_addr_ch0[15]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[15]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[15]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[15]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[15]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[15]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[1]
Adding property PAP_IO_LOC, value "M3", to port pad_addr_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[2]
Adding property PAP_IO_LOC, value "P2", to port pad_addr_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[2]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[3]
Adding property PAP_IO_LOC, value "P1", to port pad_addr_ch0[3]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[3]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[3]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[3]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[3]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[3]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[4]
Adding property PAP_IO_LOC, value "L5", to port pad_addr_ch0[4]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[4]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[4]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[4]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[4]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[4]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[5]
Adding property PAP_IO_LOC, value "M5", to port pad_addr_ch0[5]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[5]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[5]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[5]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[5]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[5]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[6]
Adding property PAP_IO_LOC, value "N2", to port pad_addr_ch0[6]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[6]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[6]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[6]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[6]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[6]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[7]
Adding property PAP_IO_LOC, value "N1", to port pad_addr_ch0[7]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[7]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[7]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[7]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[7]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[7]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[8]
Adding property PAP_IO_LOC, value "K4", to port pad_addr_ch0[8]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[8]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[8]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[8]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[8]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[8]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[9]
Adding property PAP_IO_LOC, value "M1", to port pad_addr_ch0[9]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[9]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[9]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[9]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[9]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[9]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[0]
Adding property PAP_IO_LOC, value "T8", to port pad_dq_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[0]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[0]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[10]
Adding property PAP_IO_LOC, value "U9", to port pad_dq_ch0[10]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[10]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[10]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[10]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[10]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[10]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[10]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[10]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[10]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[11]
Adding property PAP_IO_LOC, value "V7", to port pad_dq_ch0[11]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[11]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[11]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[11]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[11]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[11]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[11]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[11]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[11]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[12]
Adding property PAP_IO_LOC, value "U7", to port pad_dq_ch0[12]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[12]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[12]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[12]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[12]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[12]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[12]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[12]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[12]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[13]
Adding property PAP_IO_LOC, value "V6", to port pad_dq_ch0[13]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[13]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[13]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[13]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[13]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[13]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[13]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[13]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[13]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[14]
Adding property PAP_IO_LOC, value "U6", to port pad_dq_ch0[14]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[14]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[14]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[14]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[14]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[14]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[14]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[14]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[14]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[15]
Adding property PAP_IO_LOC, value "V5", to port pad_dq_ch0[15]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[15]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[15]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[15]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[15]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[15]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[15]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[15]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[15]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[1]
Adding property PAP_IO_LOC, value "T6", to port pad_dq_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[1]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[1]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[1]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[2]
Adding property PAP_IO_LOC, value "R6", to port pad_dq_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[2]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[2]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[2]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[2]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[3]
Adding property PAP_IO_LOC, value "R9", to port pad_dq_ch0[3]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[3]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[3]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[3]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[3]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[3]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[3]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[3]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[3]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[4]
Adding property PAP_IO_LOC, value "T9", to port pad_dq_ch0[4]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[4]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[4]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[4]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[4]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[4]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[4]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[4]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[4]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[5]
Adding property PAP_IO_LOC, value "N4", to port pad_dq_ch0[5]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[5]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[5]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[5]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[5]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[5]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[5]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[5]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[5]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[6]
Adding property PAP_IO_LOC, value "N5", to port pad_dq_ch0[6]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[6]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[6]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[6]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[6]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[6]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[6]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[6]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[6]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[7]
Adding property PAP_IO_LOC, value "P6", to port pad_dq_ch0[7]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[7]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[7]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[7]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[7]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[7]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[7]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[7]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[7]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[8]
Adding property PAP_IO_LOC, value "T4", to port pad_dq_ch0[8]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[8]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[8]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[8]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[8]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[8]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[8]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[8]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[8]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[9]
Adding property PAP_IO_LOC, value "V9", to port pad_dq_ch0[9]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[9]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[9]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[9]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[9]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[9]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[9]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[9]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[9]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqs_ch0[0]
Adding property PAP_IO_LOC, value "N6", to port pad_dqs_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqs_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqs_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqs_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqs_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqs_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqs_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqs_ch0[1]
Adding property PAP_IO_LOC, value "U8", to port pad_dqs_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqs_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqs_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqs_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqs_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqs_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqs_ch0[1]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqsn_ch0[0]
Adding property PAP_IO_LOC, value "N7", to port pad_dqsn_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqsn_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqsn_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqsn_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqsn_ch0[1]
Adding property PAP_IO_LOC, value "V8", to port pad_dqsn_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqsn_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqsn_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqsn_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_LOC, value "R8", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_LOC, value "U5", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[0]
Adding property PAP_IO_LOC, value "U2", to port pad_ba_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[1]
Adding property PAP_IO_LOC, value "U1", to port pad_ba_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[2]
Adding property PAP_IO_LOC, value "T2", to port pad_ba_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[2]

Encoding state machine state[4:0] (in view: work.test_main_ctrl_28s_16s_28s_0s_1s_2s_3s_4s(verilog))
original code -> new code
   0000 -> 00001
   0001 -> 00010
   0010 -> 00100
   0011 -> 01000
   0100 -> 10000
Encoding state machine state[2:0] (in view: work.test_wr_ctrl_64bit_Z2(verilog))
original code -> new code
   0000 -> 00
   0001 -> 01
   0010 -> 10
Encoding state machine state[2:0] (in view: work.test_rd_ctrl_64bit_28s_16s_10s_28s_1s_3s_0s_1s_2s(verilog))
original code -> new code
   000 -> 00
   001 -> 01
   010 -> 10
Encoding state machine state[10:0] (in view: work.ipsl_ddrphy_reset_ctrl(verilog))
original code -> new code
   0000 -> 00000000001
   0001 -> 00000000010
   0010 -> 00000000100
   0011 -> 00000001000
   0100 -> 00000010000
   0101 -> 00000100000
   0110 -> 00001000000
   0111 -> 00010000000
   1000 -> 00100000000
   1001 -> 01000000000
   1010 -> 10000000000
Encoding state machine state[3:0] (in view: work.ipsl_ddrphy_dll_update_ctrl(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N: MO225 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_dll_update_ctrl.v":36:0:36:5|There are no possible illegal states for state machine state[3:0] (in view: work.ipsl_ddrphy_dll_update_ctrl(verilog)); safe FSM implementation is not required.
Encoding state machine state[1:0] (in view: work.ipsl_ddrphy_update_ctrl_16BIT_2s_0s_1s_2s_3s_1(verilog))
original code -> new code
   00 -> 0
   10 -> 1
@N: MO225 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":293:0:293:5|There are no possible illegal states for state machine state[1:0] (in view: work.ipsl_ddrphy_update_ctrl_16BIT_2s_0s_1s_2s_3s_1(verilog)); safe FSM implementation is not required.

Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 223MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 223MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 225MB peak: 225MB)


Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 225MB peak: 225MB)

@N: MT611 :|Automatically generated clock ipsl_ddrphy_dll_update_ctrl|dll_update_n_inferred_clock is not used and is being removed
@W: MT686 :"d:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/ddr_324_left.fdc":6:0:6:0|No path from master pin (-source) to source of clock phy_clk 
@W: MT686 :"d:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/ddr_324_left.fdc":7:0:7:0|No path from master pin (-source) to source of clock pclk 
@W: MT548 :"d:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/ddr_324_left.fdc":8:0:8:0|Source for clock axi_clk0 not found in netlist.
@W: MT686 :"d:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/ddr_324_left.fdc":9:0:9:0|No path from master pin (-source) to source of clock axi_clk1 
@W: MT548 :"d:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/ddr_324_left.fdc":10:0:10:0|Source for clock axi_clk2 not found in netlist.


Clock Summary
******************

          Start                                                        Requested     Requested     Clock                              Clock                    Clock
Level     Clock                                                        Frequency     Period        Type                               Group                    Load 
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
0 -       pll_refclk_in                                                50.0 MHz      20.000        declared                           default_clkgroup         0    
1 .         axi_clk1                                                   100.0 MHz     10.000        generated (from pll_refclk_in)     default_clkgroup         443  
1 .         pclk                                                       50.0 MHz      20.000        generated (from pll_refclk_in)     default_clkgroup         148  
1 .         phy_clk                                                    400.0 MHz     2.500         generated (from pll_refclk_in)     default_clkgroup         21   
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|dqs_ca_clk_r_03_inferred_clock                1.0 MHz       1000.000      inferred                           Inferred_clkgroup_45     12   
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|dqs_clkw_ca_03_inferred_clock                 1.0 MHz       1000.000      inferred                           Inferred_clkgroup_47     12   
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|dqs0_clk_r_inferred_clock                     1.0 MHz       1000.000      inferred                           Inferred_clkgroup_6      10   
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|dqs1_clk_r_inferred_clock                     1.0 MHz       1000.000      inferred                           Inferred_clkgroup_33     10   
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|dqs_ca_clk_r_01_inferred_clock                1.0 MHz       1000.000      inferred                           Inferred_clkgroup_20     9    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|dqs_clkw290_0_inferred_clock                  1.0 MHz       1000.000      inferred                           Inferred_clkgroup_8      9    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|dqs_clkw290_1_inferred_clock                  1.0 MHz       1000.000      inferred                           Inferred_clkgroup_34     9    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|dqs_clkw_ca_01_inferred_clock                 1.0 MHz       1000.000      inferred                           Inferred_clkgroup_22     9    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|dqs_90_0_inferred_clock                       1.0 MHz       1000.000      inferred                           Inferred_clkgroup_10     8    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|dqs_90_1_inferred_clock                       1.0 MHz       1000.000      inferred                           Inferred_clkgroup_32     8    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|dqs_ca_clk_r_04_inferred_clock                1.0 MHz       1000.000      inferred                           Inferred_clkgroup_59     5    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|dqs_clkw_ca_04_inferred_clock                 1.0 MHz       1000.000      inferred                           Inferred_clkgroup_61     5    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|IOCLK_DIV_inferred_clock                      1.0 MHz       1000.000      inferred                           Inferred_clkgroup_0      2    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[3]              1.0 MHz       1000.000      inferred                           Inferred_clkgroup_9      2    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[4]              1.0 MHz       1000.000      inferred                           Inferred_clkgroup_11     2    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[5]              1.0 MHz       1000.000      inferred                           Inferred_clkgroup_12     2    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[6]              1.0 MHz       1000.000      inferred                           Inferred_clkgroup_13     2    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[7]              1.0 MHz       1000.000      inferred                           Inferred_clkgroup_14     2    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[10]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_17     2    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[11]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_18     2    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[12]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_19     2    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[27]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_31     2    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[28]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_35     2    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[29]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_36     2    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[32]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_39     2    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[33]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_40     2    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[34]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_41     2    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[35]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_42     2    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[36]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_43     2    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[2]              1.0 MHz       1000.000      inferred                           Inferred_clkgroup_7      1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[9]              1.0 MHz       1000.000      inferred                           Inferred_clkgroup_15     1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[17]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_21     1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[18]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_23     1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[19]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_24     1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[20]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_25     1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[21]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_26     1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[22]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_27     1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[23]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_28     1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[24]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_29     1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[25]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_30     1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[31]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_37     1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[37]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_44     1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[40]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_46     1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[41]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_48     1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[42]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_49     1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[43]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_50     1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[44]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_51     1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[45]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_52     1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[46]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_53     1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[47]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_54     1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[48]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_55     1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[49]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_56     1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[51]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_57     1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[52]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_58     1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[55]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_60     1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[56]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_62     1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[57]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_63     1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[58]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_64     1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[59]             1.0 MHz       1000.000      inferred                           Inferred_clkgroup_65     1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_dqs_clk_regional_inferred_clock[0]     1.0 MHz       1000.000      inferred                           Inferred_clkgroup_1      1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_dqs_clk_regional_inferred_clock[1]     1.0 MHz       1000.000      inferred                           Inferred_clkgroup_2      1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_dqs_clk_regional_inferred_clock[2]     1.0 MHz       1000.000      inferred                           Inferred_clkgroup_3      1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_dqs_clk_regional_inferred_clock[3]     1.0 MHz       1000.000      inferred                           Inferred_clkgroup_4      1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|buffer_dqs_clk_regional_inferred_clock[4]     1.0 MHz       1000.000      inferred                           Inferred_clkgroup_5      1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|dqs_clkw_0_inferred_clock                     1.0 MHz       1000.000      inferred                           Inferred_clkgroup_16     1    
                                                                                                                                                                    
0 -       ipsl_phy_io_Z3|dqs_clkw_1_inferred_clock                     1.0 MHz       1000.000      inferred                           Inferred_clkgroup_38     1    
====================================================================================================================================================================



Clock Load Summary
***********************

                                                             Clock     Source                                                                                             Clock Pin                                                                     Non-clock Pin     Non-clock Pin                                                                         
Clock                                                        Load      Pin                                                                                                Seq Example                                                                   Seq Example       Comb Example                                                                          
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
pll_refclk_in                                                0         pll_refclk_in(port)                                                                                -                                                                             -                 -                                                                                     
axi_clk1                                                     443       u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1.CLKOUT3(GTP_PLL_E1)                                         clk_led.C                                                                     -                 -                                                                                     
pclk                                                         148       u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1.CLKOUT1(GTP_PLL_E1)                                         u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc.PCLK                            -                 -                                                                                     
phy_clk                                                      21        u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1.CLKOUT0(GTP_PLL_E1)                                         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.CLKA             -                 u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclkbuf01_dut.CLKIN(GTP_IOCLKBUF)
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|dqs_ca_clk_r_03_inferred_clock                12        u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut.RCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr40_dut.SERCLK     -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|dqs_clkw_ca_03_inferred_clock                 12        u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut.WCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr40_dut.OCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|dqs0_clk_r_inferred_clock                     10        u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.RCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr2_dut.SERCLK      -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|dqs1_clk_r_inferred_clock                     10        u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.RCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr27_dut.SERCLK     -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|dqs_ca_clk_r_01_inferred_clock                9         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut.RCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr17_dut.SERCLK     -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|dqs_clkw290_0_inferred_clock                  9         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.WCLK_DELAY(GTP_DDC_E1)                u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr2_dut.OCLK        -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|dqs_clkw290_1_inferred_clock                  9         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.WCLK_DELAY(GTP_DDC_E1)                u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr27_dut.OCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|dqs_clkw_ca_01_inferred_clock                 9         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut.WCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr17_dut.OCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|dqs_90_0_inferred_clock                       8         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.DQSI_DELAY(GTP_DDC_E1)                u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut.ICLK        -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|dqs_90_1_inferred_clock                       8         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.DQSI_DELAY(GTP_DDC_E1)                u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr27_dut.ICLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|dqs_ca_clk_r_04_inferred_clock                5         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut.RCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr55_dut.SERCLK     -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|dqs_clkw_ca_04_inferred_clock                 5         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut.WCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr55_dut.OCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|IOCLK_DIV_inferred_clock                      2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclkdiv_dut.CLKDIVOUT(GTP_IOCLKDIV)           u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc.CORE_DDRC_CORE_CLK              -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[3]              2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[3](GTP_DDRPHY)          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut.RCLK        -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[4]              2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[4](GTP_DDRPHY)          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr4_dut.RCLK        -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[5]              2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[5](GTP_DDRPHY)          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr5_dut.RCLK        -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[6]              2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[6](GTP_DDRPHY)          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr6_dut.RCLK        -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[7]              2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[7](GTP_DDRPHY)          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr7_dut.RCLK        -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[10]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[10](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr10_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[11]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[11](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr11_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[12]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[12](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr12_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[27]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[27](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr27_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[28]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[28](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr28_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[29]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[29](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr29_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[32]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[32](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr32_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[33]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[33](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr33_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[34]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[34](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr34_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[35]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[35](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr35_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[36]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[36](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr36_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[2]              1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[2](GTP_DDRPHY)          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr2_dut.RCLK        -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[9]              1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[9](GTP_DDRPHY)          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr9_dut.RCLK        -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[17]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[17](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr17_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[18]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[18](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr18_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[19]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[19](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr19_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[20]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[20](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr20_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[21]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[21](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr21_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[22]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[22](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr22_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[23]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[23](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr23_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[24]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[24](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr24_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[25]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[25](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[31]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[31](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr31_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[37]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[37](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[40]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[40](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr40_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[41]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[41](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr41_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[42]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[42](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr42_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[43]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[43](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr43_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[44]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[44](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr44_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[45]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[45](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr45_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[46]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[46](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr46_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[47]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[47](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr47_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[48]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[48](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr48_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[49]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[49](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr49_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[51]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[51](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr51_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[52]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[52](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[55]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[55](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr55_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[56]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[56](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr56_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[57]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[57](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr57_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[58]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[58](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr58_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[59]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[59](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut.RCLK       -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_dqs_clk_regional_inferred_clock[0]     1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[0](GTP_DDRPHY)     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.CLKB             -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_dqs_clk_regional_inferred_clock[1]     1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[1](GTP_DDRPHY)     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut.CLKB             -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_dqs_clk_regional_inferred_clock[2]     1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[2](GTP_DDRPHY)     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.CLKB             -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_dqs_clk_regional_inferred_clock[3]     1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[3](GTP_DDRPHY)     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut.CLKB             -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|buffer_dqs_clk_regional_inferred_clock[4]     1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[4](GTP_DDRPHY)     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut.CLKB             -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|dqs_clkw_0_inferred_clock                     1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.WCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr9_dut.OCLK        -                 -                                                                                     
                                                                                                                                                                                                                                                                                                                                                                
ipsl_phy_io_Z3|dqs_clkw_1_inferred_clock                     1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.WCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr31_dut.OCLK       -                 -                                                                                     
================================================================================================================================================================================================================================================================================================================================================================

@W: MT531 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":54:0:54:5|Found signal identified as System clock which controls 10 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.last_dll_step[7:0].  Using this clock, which has no specified timing constraint, can prevent conversion of gated or generated clocks and can adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":960:6:960:15|Found inferred clock ipsl_phy_io_Z3|IOCLK_DIV_inferred_clock which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1134:5:1134:12|Found inferred clock ipsl_phy_io_Z3|buffer_dqs_clk_regional_inferred_clock[0] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1171:13:1171:20|Found inferred clock ipsl_phy_io_Z3|buffer_dqs_clk_regional_inferred_clock[1] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1211:6:1211:13|Found inferred clock ipsl_phy_io_Z3|buffer_dqs_clk_regional_inferred_clock[2] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1248:13:1248:20|Found inferred clock ipsl_phy_io_Z3|buffer_dqs_clk_regional_inferred_clock[3] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1285:13:1285:20|Found inferred clock ipsl_phy_io_Z3|buffer_dqs_clk_regional_inferred_clock[4] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1597:12:1597:25|Found inferred clock ipsl_phy_io_Z3|dqs0_clk_r_inferred_clock which controls 10 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr12_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1332:12:1332:24|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[2] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr2_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1597:12:1597:25|Found inferred clock ipsl_phy_io_Z3|dqs_clkw290_0_inferred_clock which controls 9 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr12_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1363:12:1363:24|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[3] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr3_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1586:12:1586:25|Found inferred clock ipsl_phy_io_Z3|dqs_90_0_inferred_clock which controls 8 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr12_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1395:12:1395:24|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[4] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr4_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1426:12:1426:24|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[5] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr5_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1458:12:1458:24|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[6] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr6_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1489:12:1489:24|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[7] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr7_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1502:12:1502:24|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[9] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr9_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1502:12:1502:24|Found inferred clock ipsl_phy_io_Z3|dqs_clkw_0_inferred_clock which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr9_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1534:12:1534:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[10] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr10_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1565:12:1565:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[11] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr11_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1597:12:1597:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[12] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr12_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1700:12:1700:25|Found inferred clock ipsl_phy_io_Z3|dqs_ca_clk_r_01_inferred_clock which controls 9 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1609:12:1609:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[17] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr17_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1700:12:1700:25|Found inferred clock ipsl_phy_io_Z3|dqs_clkw_ca_01_inferred_clock which controls 9 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1621:12:1621:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[18] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr18_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1632:12:1632:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[19] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr19_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1644:12:1644:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[20] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr20_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1655:12:1655:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[21] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr21_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1666:12:1666:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[22] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr22_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1677:12:1677:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[23] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr23_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1689:12:1689:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[24] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr24_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1700:12:1700:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[25] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1733:12:1733:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[27] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr27_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1956:12:1956:25|Found inferred clock ipsl_phy_io_Z3|dqs_90_1_inferred_clock which controls 8 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr36_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1978:12:1978:25|Found inferred clock ipsl_phy_io_Z3|dqs1_clk_r_inferred_clock which controls 10 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1978:12:1978:25|Found inferred clock ipsl_phy_io_Z3|dqs_clkw290_1_inferred_clock which controls 9 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1765:12:1765:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[28] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr28_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1796:12:1796:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[29] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr29_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1809:12:1809:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[31] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr31_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1809:12:1809:25|Found inferred clock ipsl_phy_io_Z3|dqs_clkw_1_inferred_clock which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr31_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1841:12:1841:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[32] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr32_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1872:12:1872:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[33] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr33_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1904:12:1904:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[34] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr34_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1935:12:1935:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[35] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr35_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1967:12:1967:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[36] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr36_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1978:12:1978:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[37] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2126:12:2126:25|Found inferred clock ipsl_phy_io_Z3|dqs_ca_clk_r_03_inferred_clock which controls 12 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":1993:12:1993:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[40] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr40_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2126:12:2126:25|Found inferred clock ipsl_phy_io_Z3|dqs_clkw_ca_03_inferred_clock which controls 12 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2006:12:2006:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[41] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr41_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2020:12:2020:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[42] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr42_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2031:12:2031:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[43] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr43_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2045:12:2045:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[44] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr44_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2056:12:2056:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[45] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr45_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2068:12:2068:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[46] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr46_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2078:12:2078:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[47] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr47_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2090:12:2090:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[48] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr48_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2101:12:2101:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[49] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr49_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2114:12:2114:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[51] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr51_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2126:12:2126:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[52] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2187:12:2187:25|Found inferred clock ipsl_phy_io_Z3|dqs_ca_clk_r_04_inferred_clock which controls 5 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2140:12:2140:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[55] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr55_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2187:12:2187:25|Found inferred clock ipsl_phy_io_Z3|dqs_clkw_ca_04_inferred_clock which controls 5 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2152:12:2152:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[56] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr56_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2162:12:2162:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[57] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr57_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2174:12:2174:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[58] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr58_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v":2187:12:2187:25|Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[59] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
72 gated/generated clock tree(s) driving 799 clock pin(s) of sequential element(s)
0 instances converted, 799 sequential instances remain driven by gated/generated clocks

================================================================================================================== Gated/Generated Clocks ===================================================================================================================
Clock Tree ID     Driving Element                                                                        Drive Element Type     Unconverted Fanout     Sample Instance                                                        Explanation                    
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
@KP:ckid0_0       u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1.CLKOUT1                                         GTP_PLL_E1             156                    u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                          Black box on clock path        
@KP:ckid0_2       u_ipsl_hmemc_top.aclk_0.O[0]                                                           variable               1                      u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                          Black box on clock path        
@KP:ckid0_3       u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1.CLKOUT3                                         GTP_PLL_E1             443                    u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                          Black box on clock path        
@KP:ckid0_5       u_ipsl_hmemc_top.aclk_2.O[0]                                                           variable               1                      u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                          Black box on clock path        
@KP:ckid0_7       u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclkdiv_dut.CLKDIVOUT             GTP_IOCLKDIV           2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut         Black box on clock path        
@KP:ckid0_8       u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut.WCLK                      GTP_DDC_E1             5                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut     Clock source is invalid for GCC
@KP:ckid0_10      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[59]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut     Clock source is invalid for GCC
@KP:ckid0_12      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut.RCLK                      GTP_DDC_E1             5                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut     Clock source is invalid for GCC
@KP:ckid0_14      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[58]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr58_dut     Clock source is invalid for GCC
@KP:ckid0_16      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[57]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr57_dut     Clock source is invalid for GCC
@KP:ckid0_18      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[56]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr56_dut     Clock source is invalid for GCC
@KP:ckid0_20      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[55]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr55_dut     Clock source is invalid for GCC
@KP:ckid0_22      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut.WCLK                      GTP_DDC_E1             12                     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut     Clock source is invalid for GCC
@KP:ckid0_24      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[52]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut     Clock source is invalid for GCC
@KP:ckid0_26      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut.RCLK                      GTP_DDC_E1             12                     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut     Clock source is invalid for GCC
@KP:ckid0_28      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[51]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr51_dut     Clock source is invalid for GCC
@KP:ckid0_30      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[49]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr49_dut     Clock source is invalid for GCC
@KP:ckid0_32      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[48]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr48_dut     Clock source is invalid for GCC
@KP:ckid0_34      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[47]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr47_dut     Clock source is invalid for GCC
@KP:ckid0_36      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[46]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr46_dut     Clock source is invalid for GCC
@KP:ckid0_38      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[45]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr45_dut     Clock source is invalid for GCC
@KP:ckid0_40      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[44]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr44_dut     Clock source is invalid for GCC
@KP:ckid0_42      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[43]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr43_dut     Clock source is invalid for GCC
@KP:ckid0_44      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[42]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr42_dut     Clock source is invalid for GCC
@KP:ckid0_46      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[41]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr41_dut     Clock source is invalid for GCC
@KP:ckid0_48      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[40]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr40_dut     Clock source is invalid for GCC
@KP:ckid0_50      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.WCLK_DELAY                GTP_DDC_E1             9                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut     Clock source is invalid for GCC
@KP:ckid0_52      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[37]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut     Clock source is invalid for GCC
@KP:ckid0_54      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.RCLK                      GTP_DDC_E1             10                     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut     Clock source is invalid for GCC
@KP:ckid0_56      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[36]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr36_dut     Clock source is invalid for GCC
@KP:ckid0_58      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclkbuf01_dut.CLKOUT              GTP_IOCLKBUF           19                     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr36_dut     Black box on clock path        
@KP:ckid0_59      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.DQSI_DELAY                GTP_DDC_E1             8                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr36_dut     Black box on clock path        
@KP:ckid0_61      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[35]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr35_dut     Clock source is invalid for GCC
@KP:ckid0_63      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[34]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr34_dut     Clock source is invalid for GCC
@KP:ckid0_65      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[33]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr33_dut     Clock source is invalid for GCC
@KP:ckid0_67      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[32]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr32_dut     Clock source is invalid for GCC
@KP:ckid0_69      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.WCLK                      GTP_DDC_E1             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr31_dut     Clock source is invalid for GCC
@KP:ckid0_71      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[31]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr31_dut     Clock source is invalid for GCC
@KP:ckid0_73      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[29]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr29_dut     Clock source is invalid for GCC
@KP:ckid0_75      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[28]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr28_dut     Clock source is invalid for GCC
@KP:ckid0_77      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[27]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr27_dut     Clock source is invalid for GCC
@KP:ckid0_79      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut.WCLK                      GTP_DDC_E1             9                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut     Clock source is invalid for GCC
@KP:ckid0_81      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[25]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut     Clock source is invalid for GCC
@KP:ckid0_83      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut.RCLK                      GTP_DDC_E1             9                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut     Clock source is invalid for GCC
@KP:ckid0_85      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[24]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr24_dut     Clock source is invalid for GCC
@KP:ckid0_87      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[23]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr23_dut     Clock source is invalid for GCC
@KP:ckid0_89      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[22]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr22_dut     Clock source is invalid for GCC
@KP:ckid0_91      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[21]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr21_dut     Clock source is invalid for GCC
@KP:ckid0_93      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[20]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr20_dut     Clock source is invalid for GCC
@KP:ckid0_95      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[19]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr19_dut     Clock source is invalid for GCC
@KP:ckid0_97      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[18]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr18_dut     Clock source is invalid for GCC
@KP:ckid0_99      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[17]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr17_dut     Clock source is invalid for GCC
@KP:ckid0_101     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.WCLK_DELAY                GTP_DDC_E1             9                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr12_dut     Clock source is invalid for GCC
@KP:ckid0_103     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[12]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr12_dut     Clock source is invalid for GCC
@KP:ckid0_105     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.RCLK                      GTP_DDC_E1             10                     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr12_dut     Clock source is invalid for GCC
@KP:ckid0_107     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.DQSI_DELAY                GTP_DDC_E1             8                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr12_dut     Black box on clock path        
@KP:ckid0_109     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[11]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr11_dut     Clock source is invalid for GCC
@KP:ckid0_111     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[10]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr10_dut     Clock source is invalid for GCC
@KP:ckid0_113     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.WCLK                      GTP_DDC_E1             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr9_dut      Clock source is invalid for GCC
@KP:ckid0_115     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[9]          GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr9_dut      Clock source is invalid for GCC
@KP:ckid0_117     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[7]          GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr7_dut      Clock source is invalid for GCC
@KP:ckid0_119     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[6]          GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr6_dut      Clock source is invalid for GCC
@KP:ckid0_121     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[5]          GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr5_dut      Clock source is invalid for GCC
@KP:ckid0_123     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[4]          GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr4_dut      Clock source is invalid for GCC
@KP:ckid0_125     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[3]          GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr3_dut      Clock source is invalid for GCC
@KP:ckid0_127     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[2]          GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr2_dut      Clock source is invalid for GCC
@KP:ckid0_129     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclkbuf02_dut.CLKOUT              GTP_IOCLKBUF           2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut           Black box on clock path        
@KP:ckid0_130     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[4]     GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut           Black box on clock path        
@KP:ckid0_132     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[3]     GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut           Black box on clock path        
@KP:ckid0_134     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[2]     GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut           Black box on clock path        
@KP:ckid0_136     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[1]     GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut           Black box on clock path        
@KP:ckid0_138     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[0]     GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut           Black box on clock path        
=============================================================================================================================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\synthesize\synplify_impl\synplify.sap.

Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 225MB peak: 225MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 225MB peak: 225MB)

@W: MF511 |Found issues with constraints. Please check constraint checker report "D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\synthesize\synplify_impl\synplify_cck.rpt" .

Finished constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 225MB peak: 225MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 145MB peak: 225MB)

Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Tue May  7 10:00:07 2019

###########################################################]
Map & Optimize Report

# Tue May  7 10:00:07 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03P-Beta2
Install: C:\pango\PDS_2019.1-patch2\syn
OS: Windows 6.1

Hostname: ALINX000007-PC

Implementation : synplify_impl
Synopsys Generic Technology Mapper, Version map2019q1p1, Build 1238R, Built Mar 15 2019 09:38:46


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 119MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 119MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 119MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 123MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 209MB peak: 209MB)

@N: MO111 :|Tristate driver dqs_drift_l_t[0] (in view: work.ipsl_hmemc_phy_top_Z4(verilog)) on net dqs_drift_l[0] (in view: work.ipsl_hmemc_phy_top_Z4(verilog)) has its enable tied to GND.
@N: MO111 :|Tristate driver dqs_drift_l_t[1] (in view: work.ipsl_hmemc_phy_top_Z4(verilog)) on net dqs_drift_l[1] (in view: work.ipsl_hmemc_phy_top_Z4(verilog)) has its enable tied to GND.
@N: MO111 :|Tristate driver dqs_drift_h_t[0] (in view: work.ipsl_hmemc_phy_top_Z4(verilog)) on net dqs_drift_h[0] (in view: work.ipsl_hmemc_phy_top_Z4(verilog)) has its enable tied to GND.
@N: MO111 :|Tristate driver dqs_drift_h_t[1] (in view: work.ipsl_hmemc_phy_top_Z4(verilog)) on net dqs_drift_h[1] (in view: work.ipsl_hmemc_phy_top_Z4(verilog)) has its enable tied to GND.

Available hyper_sources - for debug and ip models
	None Found

@N: MT204 |Auto Constrain mode is disabled because clocks are defined in the SDC file

            pll_refclk_in


Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 216MB peak: 216MB)

@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[32] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[41] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[42] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[43] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[44] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[45] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[46] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[47] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[48] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[49] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[50] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[51] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[52] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[53] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[54] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[55] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[56] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[57] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[58] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[59] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[60] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[61] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[62] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[63] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[64] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[65] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[66] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[67] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[68] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[69] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[70] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[71] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[72] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[73] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[74] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[75] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[76] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[77] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[78] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[79] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[80] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[81] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[82] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[83] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[84] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[85] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[86] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[87] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[88] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[89] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[90] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[91] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[92] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[93] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[94] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[95] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[96] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[118] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[119] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[120] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[121] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[122] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[123] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[124] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[125] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[126] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[127] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":164:0:164:5|Removing sequential instance latch_y[128] (in view: work.prbs31_128bit_1_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":174:0:174:5|Removing sequential instance insert_er_d[0] (in view: work.prbs31_128bit_1_Z1(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":174:0:174:5|Removing sequential instance insert_er_d[1] (in view: work.prbs31_128bit_1_Z1(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\prbs31_128bit.v":174:0:174:5|Removing sequential instance insert_er_d[2] (in view: work.prbs31_128bit_1_Z1(verilog)) because it does not drive other instances.
@N: MO231 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":164:0:164:5|Found counter in view:work.test_wr_ctrl_64bit_Z2(verilog) instance init_addr[29:2] 
@N: MO231 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Found counter in view:work.test_wr_ctrl_64bit_Z2(verilog) instance axi_awid[7:0] 
@N: MO231 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":164:0:164:5|Found counter in view:work.test_wr_ctrl_64bit_Z2(verilog) instance cnt_len[4:0] 
@N: MO231 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":232:0:232:5|Found counter in view:work.test_wr_ctrl_64bit_Z2(verilog) instance execute_wr_cnt[15:0] 
@N: MF179 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":251:25:251:53|Found 16 by 16 bit equality operator ('==') write_finished (in view: work.test_wr_ctrl_64bit_Z2(verilog))
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":94:0:94:5|Removing instance u_test_rd_ctrl.axi_araddr_1[7] because it is equivalent to instance u_test_rd_ctrl.axi_araddr_1[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":94:0:94:5|Removing instance u_test_rd_ctrl.axi_araddr_1[6] because it is equivalent to instance u_test_rd_ctrl.axi_araddr_1[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":94:0:94:5|Removing instance u_test_rd_ctrl.axi_araddr_1[5] because it is equivalent to instance u_test_rd_ctrl.axi_araddr_1[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":94:0:94:5|Removing instance u_test_rd_ctrl.axi_araddr_1[4] because it is equivalent to instance u_test_rd_ctrl.axi_araddr_1[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":94:0:94:5|Removing instance u_test_rd_ctrl.axi_araddr_1[3] because it is equivalent to instance u_test_rd_ctrl.axi_araddr_1[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":94:0:94:5|Removing instance u_test_rd_ctrl.axi_araddr_1[2] because it is equivalent to instance u_test_rd_ctrl.axi_araddr_1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N: MO231 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":147:0:147:5|Found counter in view:work.test_rd_ctrl_64bit_28s_16s_10s_28s_1s_3s_0s_1s_2s(verilog) instance cnt_len[4:0] 
@N: MO231 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":171:0:171:5|Found counter in view:work.test_rd_ctrl_64bit_28s_16s_10s_28s_1s_3s_0s_1s_2s(verilog) instance execute_rd_cnt[15:0] 
@N: MF179 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":185:25:185:53|Found 16 by 16 bit equality operator ('==') read_finished (in view: work.test_rd_ctrl_64bit_28s_16s_10s_28s_1s_3s_0s_1s_2s(verilog))
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":94:0:94:5|Removing sequential instance axi_araddr_1[1] (in view: work.test_rd_ctrl_64bit_28s_16s_10s_28s_1s_3s_0s_1s_2s(verilog)) because it does not drive other instances.
@N: MO231 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_reset_ctrl.v":52:0:52:5|Found counter in view:work.ipsl_ddrphy_reset_ctrl(verilog) instance cnt[7:0] 
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":293:0:293:5|Removing instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.ddrphy_update_comp_val_l[1] because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.ddrphy_update_comp_val_h[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N: MO231 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":121:0:121:5|Found counter in view:work.ipsl_ddrphy_update_ctrl_16BIT_2s_0s_1s_2s_3s_1(verilog) instance dqs_drift_h_cnt[7:0] 
@N: MO231 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":102:0:102:5|Found counter in view:work.ipsl_ddrphy_update_ctrl_16BIT_2s_0s_1s_2s_3s_1(verilog) instance dqs_drift_l_cnt[7:0] 
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":293:0:293:5|Removing sequential instance ddrphy_update_comp_val_h[1] (in view: work.ipsl_ddrphy_update_ctrl_16BIT_2s_0s_1s_2s_3s_1(verilog)) because it does not drive other instances.
@N: MO231 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_reset_ctrl.v":113:0:113:5|Found counter in view:work.ipsl_hmemc_ddrc_top_Z7(verilog) instance u_ipsl_ddrc_reset_ctrl.ddrc_rst_cnt[4:0] 
@N: MO231 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_reset_ctrl.v":86:0:86:5|Found counter in view:work.ipsl_hmemc_ddrc_top_Z7(verilog) instance u_ipsl_ddrc_reset_ctrl.rst_cnt[4:0] 
@N: MO231 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_apb_reset.v":387:0:387:5|Found counter in view:work.ipsl_ddrc_apb_reset_Z5(verilog) instance cnt[6:0] 

Starting factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 218MB peak: 218MB)

@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":121:0:121:5|Removing instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_h_d1[1] because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_h_d1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":102:0:102:5|Removing instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_l_d1[1] because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_h_d1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":102:0:102:5|Removing instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_l_d1[0] because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_h_d1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":121:0:121:5|Removing instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_h_now[1] because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_h_now[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":102:0:102:5|Removing instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_l_now[1] because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_l_now[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":293:0:293:5|Removing instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_h_last[1] because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_h_last[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":293:0:293:5|Removing instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_l_last[1] because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_l_last[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":293:0:293:5|Removing instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.ddrphy_update_comp_dir_l because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.ddrphy_update_comp_dir_h. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":121:0:121:5|Removing sequential instance u_ddrphy_update_ctrl.dqs_drift_h_d1[0] (in view: work.ipsl_hmemc_phy_top_Z4(verilog)) because it does not drive other instances.
Auto Dissolve of u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top (inst of view:work.ipsl_hmemc_phy_top_Z4(verilog))

Finished factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 223MB peak: 223MB)

@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":54:0:54:5|Removing sequential instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.last_dll_step_1[1] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":54:0:54:5|Removing sequential instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.last_dll_step_1[2] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":54:0:54:5|Removing sequential instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.last_dll_step_1[3] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":54:0:54:5|Removing sequential instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.last_dll_step_1[4] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":54:0:54:5|Removing sequential instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.last_dll_step_1[5] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":54:0:54:5|Removing sequential instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.last_dll_step_1[6] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":164:0:164:5|Removing sequential instance u_test_wr_ctrl.normal_wr_addr_0_0[2] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":164:0:164:5|Removing sequential instance u_test_wr_ctrl.normal_wr_addr_0_0[3] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":164:0:164:5|Removing sequential instance u_test_wr_ctrl.normal_wr_addr_0_0[4] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":164:0:164:5|Removing sequential instance u_test_wr_ctrl.normal_wr_addr_0_0[5] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":164:0:164:5|Removing sequential instance u_test_wr_ctrl.normal_wr_addr_0_0[6] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":164:0:164:5|Removing sequential instance u_test_wr_ctrl.normal_wr_addr_0_0[7] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":164:0:164:5|Removing sequential instance u_test_wr_ctrl.normal_wr_addr_0[2] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":164:0:164:5|Removing sequential instance u_test_wr_ctrl.normal_wr_addr_0[3] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":164:0:164:5|Removing sequential instance u_test_wr_ctrl.normal_wr_addr_0[4] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":164:0:164:5|Removing sequential instance u_test_wr_ctrl.normal_wr_addr_0[5] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":164:0:164:5|Removing sequential instance u_test_wr_ctrl.normal_wr_addr_0[6] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":164:0:164:5|Removing sequential instance u_test_wr_ctrl.normal_wr_addr_0[7] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing sequential instance u_test_wr_ctrl.axi_awaddr_1_0[8] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing sequential instance u_test_wr_ctrl.axi_awaddr_1_0[9] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing sequential instance u_test_wr_ctrl.axi_awaddr_1_0[10] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing sequential instance u_test_wr_ctrl.axi_awaddr_1_0[11] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing sequential instance u_test_wr_ctrl.axi_awaddr_1_0[12] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing sequential instance u_test_wr_ctrl.axi_awaddr_1_0[13] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing sequential instance u_test_wr_ctrl.axi_awaddr_1_0[14] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N: BN362 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing sequential instance u_test_wr_ctrl.axi_awaddr_1_0[15] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.

Only the first 100 messages of id 'BN362' are reported. To see all messages use 'report_messages -log D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\synthesize\synplify_impl\synlog\synplify_fpga_mapper.srr -id BN362' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {BN362} -count unlimited' in the Tcl shell.

Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 358MB peak: 358MB)

@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":164:0:164:5|Removing instance u_test_wr_ctrl.normal_wr_addr_0_0[0] because it is equivalent to instance u_test_wr_ctrl.normal_wr_addr_0[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":164:0:164:5|Removing instance u_test_wr_ctrl.normal_wr_addr_0_0[1] because it is equivalent to instance u_test_wr_ctrl.normal_wr_addr_0[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":164:0:164:5|Removing instance u_test_wr_ctrl.normal_wr_addr_0_1[0] because it is equivalent to instance u_test_wr_ctrl.normal_wr_addr[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":164:0:164:5|Removing instance u_test_wr_ctrl.normal_wr_addr_0_1[1] because it is equivalent to instance u_test_wr_ctrl.normal_wr_addr[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":164:0:164:5|Removing instance u_test_wr_ctrl.normal_wr_addr_0_1[2] because it is equivalent to instance u_test_wr_ctrl.normal_wr_addr[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":164:0:164:5|Removing instance u_test_wr_ctrl.normal_wr_addr_0_1[3] because it is equivalent to instance u_test_wr_ctrl.normal_wr_addr[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":164:0:164:5|Removing instance u_test_wr_ctrl.normal_wr_addr_0_1[4] because it is equivalent to instance u_test_wr_ctrl.normal_wr_addr[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":164:0:164:5|Removing instance u_test_wr_ctrl.normal_wr_addr_0_1[5] because it is equivalent to instance u_test_wr_ctrl.normal_wr_addr[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":147:0:147:5|Removing instance u_test_rd_ctrl.normal_rd_addr_1[6] because it is equivalent to instance u_test_rd_ctrl.normal_rd_addr[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":147:0:147:5|Removing instance u_test_rd_ctrl.normal_rd_addr_0[6] because it is equivalent to instance u_test_rd_ctrl.normal_rd_addr[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":147:0:147:5|Removing instance u_test_rd_ctrl.normal_rd_addr_3[6] because it is equivalent to instance u_test_rd_ctrl.normal_rd_addr[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":147:0:147:5|Removing instance u_test_rd_ctrl.normal_rd_addr_2[6] because it is equivalent to instance u_test_rd_ctrl.normal_rd_addr[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_0[0] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_1[0] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_0[1] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_1[1] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_0[2] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_1[2] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_0[3] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_1[3] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_0[4] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_1[4] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_0[5] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_1[5] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_0[6] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_1[6] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_0[7] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_1[7] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_1[8] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_1[9] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[9]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_1[10] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_1[11] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_1[12] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_1[13] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_1[14] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_1[15] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_1[16] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[16]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_1[17] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[17]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_1[18] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[18]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_1[19] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[19]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_1[20] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[20]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_1[21] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[21]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_1[22] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[22]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_1[23] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[23]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_1[24] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[24]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_1[25] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[25]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_1[26] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[26]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_1[27] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[27]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awaddr_1_1[28] because it is equivalent to instance u_test_wr_ctrl.axi_awaddr_1[28]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\ipsl_hmemc_top_test.v":116:0:116:5|Removing instance u_test_wr_ctrl.cnt_1[7] because it is equivalent to instance u_test_wr_ctrl.cnt[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\ipsl_hmemc_top_test.v":116:0:116:5|Removing instance u_test_wr_ctrl.cnt_1[8] because it is equivalent to instance u_test_wr_ctrl.cnt[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\ipsl_hmemc_top_test.v":116:0:116:5|Removing instance u_test_wr_ctrl.cnt_1[10] because it is equivalent to instance u_test_wr_ctrl.cnt[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\ipsl_hmemc_top_test.v":116:0:116:5|Removing instance u_test_wr_ctrl.cnt_1[12] because it is equivalent to instance u_test_wr_ctrl.cnt[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\ipsl_hmemc_top_test.v":116:0:116:5|Removing instance u_test_wr_ctrl.cnt_1[13] because it is equivalent to instance u_test_wr_ctrl.cnt[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\ipsl_hmemc_top_test.v":116:0:116:5|Removing instance u_test_wr_ctrl.cnt_1[14] because it is equivalent to instance u_test_wr_ctrl.cnt[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\ipsl_hmemc_top_test.v":116:0:116:5|Removing instance u_test_wr_ctrl.cnt_1[19] because it is equivalent to instance u_test_wr_ctrl.cnt[19]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awlen_1_0[0] because it is equivalent to instance u_test_wr_ctrl.axi_awlen_1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awlen_1_1[0] because it is equivalent to instance u_test_wr_ctrl.axi_awlen_1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awlen_1_0[1] because it is equivalent to instance u_test_wr_ctrl.axi_awlen_1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awlen_1_1[1] because it is equivalent to instance u_test_wr_ctrl.axi_awlen_1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awlen_1_0[2] because it is equivalent to instance u_test_wr_ctrl.axi_awlen_1[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awlen_1_1[2] because it is equivalent to instance u_test_wr_ctrl.axi_awlen_1[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awlen_1_0[3] because it is equivalent to instance u_test_wr_ctrl.axi_awlen_1[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_wr_ctrl_64bit.v":104:0:104:5|Removing instance u_test_wr_ctrl.axi_awlen_1_1[3] because it is equivalent to instance u_test_wr_ctrl.axi_awlen_1[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":171:0:171:5|Removing instance u_test_rd_ctrl.req_rd_cnt_0[0] because it is equivalent to instance u_test_rd_ctrl.req_rd_cnt[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":171:0:171:5|Removing instance u_test_rd_ctrl.req_rd_cnt_0[1] because it is equivalent to instance u_test_rd_ctrl.req_rd_cnt[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":171:0:171:5|Removing instance u_test_rd_ctrl.req_rd_cnt_0[2] because it is equivalent to instance u_test_rd_ctrl.req_rd_cnt[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":171:0:171:5|Removing instance u_test_rd_ctrl.req_rd_cnt_0[3] because it is equivalent to instance u_test_rd_ctrl.req_rd_cnt[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":171:0:171:5|Removing instance u_test_rd_ctrl.req_rd_cnt_0[4] because it is equivalent to instance u_test_rd_ctrl.req_rd_cnt[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":171:0:171:5|Removing instance u_test_rd_ctrl.req_rd_cnt_0[5] because it is equivalent to instance u_test_rd_ctrl.req_rd_cnt[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":171:0:171:5|Removing instance u_test_rd_ctrl.req_rd_cnt_0[6] because it is equivalent to instance u_test_rd_ctrl.req_rd_cnt[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":171:0:171:5|Removing instance u_test_rd_ctrl.req_rd_cnt_0[7] because it is equivalent to instance u_test_rd_ctrl.req_rd_cnt[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":171:0:171:5|Removing instance u_test_rd_ctrl.req_rd_cnt_0[8] because it is equivalent to instance u_test_rd_ctrl.req_rd_cnt[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":171:0:171:5|Removing instance u_test_rd_ctrl.req_rd_cnt_0[9] because it is equivalent to instance u_test_rd_ctrl.req_rd_cnt[9]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":171:0:171:5|Removing instance u_test_rd_ctrl.req_rd_cnt_0[10] because it is equivalent to instance u_test_rd_ctrl.req_rd_cnt[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":171:0:171:5|Removing instance u_test_rd_ctrl.req_rd_cnt_0[11] because it is equivalent to instance u_test_rd_ctrl.req_rd_cnt[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":171:0:171:5|Removing instance u_test_rd_ctrl.req_rd_cnt_0[12] because it is equivalent to instance u_test_rd_ctrl.req_rd_cnt[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":171:0:171:5|Removing instance u_test_rd_ctrl.req_rd_cnt_0[13] because it is equivalent to instance u_test_rd_ctrl.req_rd_cnt[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":171:0:171:5|Removing instance u_test_rd_ctrl.req_rd_cnt_0[14] because it is equivalent to instance u_test_rd_ctrl.req_rd_cnt[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\test_rd_ctrl_64bit.v":171:0:171:5|Removing instance u_test_rd_ctrl.req_rd_cnt_0[15] because it is equivalent to instance u_test_rd_ctrl.req_rd_cnt[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":54:0:54:5|Removing instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.last_dll_step_2[0] because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.last_dll_step_0[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":54:0:54:5|Removing instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.last_dll_step_1[0] because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.last_dll_step_0[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":54:0:54:5|Removing instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.last_dll_step_0[1] because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.last_dll_step[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":54:0:54:5|Removing instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.last_dll_step_0[2] because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.last_dll_step[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v":54:0:54:5|Removing instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.last_dll_step_0[3] because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.last_dll_step[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.

Only the first 100 messages of id 'BN132' are reported. To see all messages use 'report_messages -log D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\synthesize\synplify_impl\synlog\synplify_fpga_mapper.srr -id BN132' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {BN132} -count unlimited' in the Tcl shell.

Starting Early Timing Optimization (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 359MB peak: 359MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 359MB peak: 359MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 359MB peak: 359MB)

@W: FX553 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_apb_reset.v":115:15:115:18|Could not implement Block ROM for u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.data_2[43:3].
@N: FX214 :"d:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_apb_reset.v":115:15:115:18|Generating ROM u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.data_2[43:3] (in view: work.ipsl_hmemc_ddrc_top_Z7(verilog)).

Finished preparing to map (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 361MB peak: 361MB)


Finished technology mapping (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 363MB peak: 363MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:09s		     1.51ns		 783 /       436

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 364MB peak: 364MB)

@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  

Finished restoring hierarchy (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:13s; Memory used current: 364MB peak: 364MB)


Start Writing Netlists (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:13s; Memory used current: 299MB peak: 365MB)

Writing Analyst data base D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\synthesize\synplify_impl\synwork\synplify_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:20s; CPU Time elapsed 0h:00m:17s; Memory used current: 371MB peak: 371MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:22s; CPU Time elapsed 0h:00m:19s; Memory used current: 402MB peak: 402MB)

@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: BW278 :"d:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/ddr_324_left.fdc":7:0:7:0|Clock pclk source pin u_ipsl_hmemc_top.u_pll_50_400.clkout1_keep.OUT[0]
@N: BW279 :"d:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/ddr_324_left.fdc":7:0:7:0|Clock pclk drive pin u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1.CLKOUT1
@N: BW280 :"d:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/ddr_324_left.fdc":7:0:7:0|Forward annotating clock pclk on drive pins would add that clock to 8 clock pins including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.last_dll_step[0].CLK
@N: BW283 :"d:/example_ziguang/sd_picture_hdmi _ddrtest/ipcore/ddr3/pnr/ctrl_phy_22/ddr_324_left.fdc":7:0:7:0|Forward annotating clock pclk on input pins
@W: BW150 :|Clock ipsl_ddrphy_dll_update_ctrl|dll_update_n_inferred_clock in set_clock_groups command cannot be found and will not be forward annotated

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:22s; CPU Time elapsed 0h:00m:19s; Memory used current: 402MB peak: 402MB)


Start final timing analysis (Real Time elapsed 0h:00m:23s; CPU Time elapsed 0h:00m:20s; Memory used current: 364MB peak: 403MB)

@N: MT615 |Found clock pll_refclk_in with period 20.00ns 
@N: MT615 |Found clock phy_clk with period 2.50ns 
@N: MT615 |Found clock pclk with period 20.00ns 
@N: MT615 |Found clock axi_clk1 with period 10.00ns 
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|IOCLK_DIV_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrc_core_clk.
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_dqs_clk_regional_inferred_clock[0] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_dqs_clk_regional[0].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_dqs_clk_regional_inferred_clock[1] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_dqs_clk_regional[1].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_dqs_clk_regional_inferred_clock[2] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_dqs_clk_regional[2].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_dqs_clk_regional_inferred_clock[3] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_dqs_clk_regional[3].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_dqs_clk_regional_inferred_clock[4] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_dqs_clk_regional[4].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|dqs0_clk_r_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_clk_r.
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[2] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[2].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|dqs_clkw290_0_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw290_0.
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[3] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[3].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|dqs_90_0_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_90_0.
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[4] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[4].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[5] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[5].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[6] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[6].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[7] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[7].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[9] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[9].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|dqs_clkw_0_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw_0.
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[10] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[10].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[11] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[11].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[12] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[12].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|dqs_ca_clk_r_01_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_ca_clk_r_01.
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[17] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[17].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|dqs_clkw_ca_01_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw_ca_01.
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[18] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[18].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[19] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[19].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[20] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[20].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[21] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[21].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[22] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[22].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[23] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[23].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[24] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[24].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[25] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[25].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[27] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[27].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|dqs_90_1_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_90_1.
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|dqs1_clk_r_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_clk_r.
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|dqs_clkw290_1_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw290_1.
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[28] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[28].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[29] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[29].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[31] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[31].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|dqs_clkw_1_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw_1.
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[32] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[32].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[33] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[33].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[34] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[34].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[35] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[35].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[36] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[36].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[37] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[37].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|dqs_ca_clk_r_03_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_ca_clk_r_03.
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[40] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[40].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|dqs_clkw_ca_03_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw_ca_03.
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[41] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[41].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[42] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[42].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[43] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[43].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[44] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[44].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[45] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[45].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[46] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[46].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[47] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[47].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[48] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[48].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[49] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[49].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[51] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[51].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[52] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[52].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|dqs_ca_clk_r_04_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_ca_clk_r_04.
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[55] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[55].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|dqs_clkw_ca_04_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw_ca_04.
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[56] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[56].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[57] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[57].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[58] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[58].
@W: MT420 |Found inferred clock ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[59] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[59].
@W: MT420 |Found inferred clock pll_50_400|clkout1_0_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_pll_50_400.clkout1_0[0].


##### START OF TIMING REPORT #####[
# Timing report written on Tue May  7 10:00:31 2019
#


Top view:               ipsl_hmemc_top_test
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        3
Constraint File(s):    D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\ddr_324_left.fdc
                       
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.



Performance Summary
*******************


Worst slack in design: 1.508

                                                             Requested     Estimated      Requested     Estimated                Clock                              Clock               
Starting Clock                                               Frequency     Frequency      Period        Period        Slack      Type                               Group               
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
axi_clk1                                                     100.0 MHz     192.8 MHz      10.000        5.186         4.814      generated (from pll_refclk_in)     default_clkgroup    
ipsl_phy_io_Z3|IOCLK_DIV_inferred_clock                      1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_0 
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[2]              1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_7 
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[3]              1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_9 
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[4]              1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_11
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[5]              1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_12
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[6]              1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_13
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[7]              1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_14
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[9]              1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_15
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[10]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_17
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[11]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_18
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[12]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_19
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[17]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_21
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[18]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_23
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[19]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_24
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[20]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_25
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[21]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_26
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[22]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_27
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[23]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_28
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[24]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_29
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[25]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_30
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[27]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_31
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[28]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_35
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[29]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_36
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[31]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_37
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[32]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_39
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[33]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_40
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[34]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_41
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[35]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_42
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[36]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_43
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[37]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_44
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[40]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_46
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[41]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_48
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[42]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_49
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[43]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_50
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[44]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_51
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[45]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_52
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[46]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_53
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[47]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_54
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[48]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_55
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[49]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_56
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[51]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_57
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[52]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_58
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[55]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_60
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[56]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_62
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[57]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_63
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[58]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_64
ipsl_phy_io_Z3|buffer_clk_sys_inferred_clock[59]             1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_65
ipsl_phy_io_Z3|buffer_dqs_clk_regional_inferred_clock[0]     1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_1 
ipsl_phy_io_Z3|buffer_dqs_clk_regional_inferred_clock[1]     1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_2 
ipsl_phy_io_Z3|buffer_dqs_clk_regional_inferred_clock[2]     1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_3 
ipsl_phy_io_Z3|buffer_dqs_clk_regional_inferred_clock[3]     1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_4 
ipsl_phy_io_Z3|buffer_dqs_clk_regional_inferred_clock[4]     1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_5 
ipsl_phy_io_Z3|dqs0_clk_r_inferred_clock                     1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_6 
ipsl_phy_io_Z3|dqs1_clk_r_inferred_clock                     1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_33
ipsl_phy_io_Z3|dqs_90_0_inferred_clock                       1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_10
ipsl_phy_io_Z3|dqs_90_1_inferred_clock                       1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_32
ipsl_phy_io_Z3|dqs_ca_clk_r_01_inferred_clock                1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_20
ipsl_phy_io_Z3|dqs_ca_clk_r_03_inferred_clock                1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_45
ipsl_phy_io_Z3|dqs_ca_clk_r_04_inferred_clock                1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_59
ipsl_phy_io_Z3|dqs_clkw290_0_inferred_clock                  1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_8 
ipsl_phy_io_Z3|dqs_clkw290_1_inferred_clock                  1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_34
ipsl_phy_io_Z3|dqs_clkw_0_inferred_clock                     1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_16
ipsl_phy_io_Z3|dqs_clkw_1_inferred_clock                     1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_38
ipsl_phy_io_Z3|dqs_clkw_ca_01_inferred_clock                 1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_22
ipsl_phy_io_Z3|dqs_clkw_ca_03_inferred_clock                 1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_47
ipsl_phy_io_Z3|dqs_clkw_ca_04_inferred_clock                 1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_61
pclk                                                         50.0 MHz      120.6 MHz      20.000        8.294         9.134      generated (from pll_refclk_in)     default_clkgroup    
phy_clk                                                      400.0 MHz     1008.1 MHz     2.500         0.992         1.508      generated (from pll_refclk_in)     default_clkgroup    
pll_50_400|clkout1_0_inferred_clock                          1.0 MHz       NA             1000.000      NA            NA         inferred                           Inferred_clkgroup_67
pll_refclk_in                                                50.0 MHz      NA             20.000        NA            NA         declared                           default_clkgroup    
System                                                       1.0 MHz       1.0 MHz        1000.000      980.269       19.731     system                             system_clkgroup     
========================================================================================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform





Clock Relationships
*******************

Clocks                                                                            |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                 Ending                                   |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                   pclk                                     |  20.000      19.731   |  No paths    -      |  No paths    -      |  No paths    -    
System                                   pll_50_400|clkout1_0_inferred_clock      |  1000.000    999.731  |  No paths    -      |  No paths    -      |  No paths    -    
phy_clk                                  phy_clk                                  |  2.500       1.508    |  No paths    -      |  No paths    -      |  No paths    -    
pclk                                     System                                   |  20.000      19.133   |  No paths    -      |  No paths    -      |  No paths    -    
pclk                                     pclk                                     |  20.000      11.706   |  No paths    -      |  No paths    -      |  No paths    -    
pclk                                     axi_clk1                                 |  10.000      9.134    |  No paths    -      |  No paths    -      |  No paths    -    
pclk                                     ipsl_phy_io_Z3|IOCLK_DIV_inferred_clock  |  Diff grp    -        |  No paths    -      |  No paths    -      |  No paths    -    
pclk                                     pll_50_400|clkout1_0_inferred_clock      |  Diff grp    -        |  No paths    -      |  No paths    -      |  No paths    -    
axi_clk1                                 axi_clk1                                 |  10.000      4.814    |  No paths    -      |  No paths    -      |  No paths    -    
ipsl_phy_io_Z3|IOCLK_DIV_inferred_clock  pclk                                     |  Diff grp    -        |  No paths    -      |  No paths    -      |  No paths    -    
pll_50_400|clkout1_0_inferred_clock      pclk                                     |  Diff grp    -        |  No paths    -      |  No paths    -      |  No paths    -    
==========================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: axi_clk1
====================================



Starting Points with Worst Slack
********************************

                                                  Starting                                                     Arrival          
Instance                                          Reference     Type          Pin           Net                Time        Slack
                                                  Clock                                                                         
--------------------------------------------------------------------------------------------------------------------------------
u_test_rd_ctrl.axi_arvalid                        axi_clk1      GTP_DFF_C     Q             axi_arvalid        0.290       4.814
u_test_wr_ctrl.axi_awvalid                        axi_clk1      GTP_DFF_C     Q             axi_awvalid        0.290       4.845
u_test_wr_ctrl.axi_awaddr_1[27]                   axi_clk1      GTP_DFF_C     Q             axi_awaddr[27]     0.290       5.508
u_test_wr_ctrl.axi_awaddr_1[26]                   axi_clk1      GTP_DFF_C     Q             axi_awaddr[26]     0.290       5.618
u_test_wr_ctrl.axi_awaddr_1[25]                   axi_clk1      GTP_DFF_C     Q             axi_awaddr[25]     0.290       5.673
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc     axi_clk1      GTP_DDRC      AWREADY_1     awready_1          0.988       5.695
u_test_wr_ctrl.axi_awaddr_1[10]                   axi_clk1      GTP_DFF_C     Q             axi_awaddr[10]     0.290       5.705
u_test_wr_ctrl.axi_awaddr_1[9]                    axi_clk1      GTP_DFF_C     Q             axi_awaddr[9]      0.290       5.709
u_test_wr_ctrl.axi_awaddr_1[15]                   axi_clk1      GTP_DFF_C     Q             axi_awaddr[15]     0.290       5.709
u_test_wr_ctrl.axi_awaddr_1[14]                   axi_clk1      GTP_DFF_C     Q             axi_awaddr[14]     0.290       5.713
================================================================================================================================


Ending Points with Worst Slack
******************************

                                                  Starting                                                       Required          
Instance                                          Reference     Type          Pin           Net                  Time         Slack
                                                  Clock                                                                            
-----------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc     axi_clk1      GTP_DDRC      ARVALID_1     arvalid_1            5.432        4.814
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc     axi_clk1      GTP_DDRC      AWVALID_1     awvalid_1            5.443        4.845
u_test_wr_ctrl.axi_awaddr_1[27]                   axi_clk1      GTP_DFF_C     D             axi_awaddr_7[27]     10.020       5.508
u_test_wr_ctrl.axi_awaddr_1[28]                   axi_clk1      GTP_DFF_C     D             axi_awaddr_7[28]     10.023       5.532
u_test_wr_ctrl.axi_awaddr_1[26]                   axi_clk1      GTP_DFF_C     D             axi_awaddr_7[26]     10.020       5.542
u_test_wr_ctrl.axi_awaddr_1[25]                   axi_clk1      GTP_DFF_C     D             axi_awaddr_7[25]     10.020       5.576
u_test_wr_ctrl.axi_awaddr_1[24]                   axi_clk1      GTP_DFF_C     D             axi_awaddr_7[24]     10.020       5.610
u_test_wr_ctrl.axi_awaddr_1[23]                   axi_clk1      GTP_DFF_C     D             axi_awaddr_7[23]     10.020       5.644
u_test_wr_ctrl.axi_awaddr_1[22]                   axi_clk1      GTP_DFF_C     D             axi_awaddr_7[22]     10.020       5.678
u_test_wr_ctrl.axi_awaddr_1[21]                   axi_clk1      GTP_DFF_C     D             axi_awaddr_7[21]     10.020       5.712
===================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            4.568
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.432

    - Propagation time:                      0.618
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 4.814

    Number of logic level(s):                0
    Starting point:                          u_test_rd_ctrl.axi_arvalid / Q
    Ending point:                            u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc / ARVALID_1
    The start point is clocked by            axi_clk1 [rising] on pin CLK
    The end   point is clocked by            axi_clk1 [rising] on pin ACLK_1

Instance / Net                                                  Pin           Pin               Arrival     No. of    
Name                                              Type          Name          Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------
u_test_rd_ctrl.axi_arvalid                        GTP_DFF_C     Q             Out     0.290     0.290       -         
axi_arvalid                                       Net           -             -       0.328     -           4         
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc     GTP_DDRC      ARVALID_1     In      -         0.618       -         
======================================================================================================================
Total path delay (propagation time + setup) of 5.186 is 4.858(93.7%) logic and 0.328(6.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      10.000
    - Setup time:                            4.557
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.443

    - Propagation time:                      0.599
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 4.845

    Number of logic level(s):                0
    Starting point:                          u_test_wr_ctrl.axi_awvalid / Q
    Ending point:                            u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc / AWVALID_1
    The start point is clocked by            axi_clk1 [rising] on pin CLK
    The end   point is clocked by            axi_clk1 [rising] on pin ACLK_1

Instance / Net                                                  Pin           Pin               Arrival     No. of    
Name                                              Type          Name          Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------
u_test_wr_ctrl.axi_awvalid                        GTP_DFF_C     Q             Out     0.290     0.290       -         
axi_awvalid                                       Net           -             -       0.308     -           3         
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc     GTP_DDRC      AWVALID_1     In      -         0.599       -         
======================================================================================================================
Total path delay (propagation time + setup) of 5.155 is 4.847(94.0%) logic and 0.308(6.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      10.000
    - Setup time:                            -0.020
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         10.020

    - Propagation time:                      4.512
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 5.508

    Number of logic level(s):                27
    Starting point:                          u_test_wr_ctrl.axi_awaddr_1[27] / Q
    Ending point:                            u_test_wr_ctrl.axi_awaddr_1[27] / D
    The start point is clocked by            axi_clk1 [rising] on pin CLK
    The end   point is clocked by            axi_clk1 [rising] on pin CLK

Instance / Net                                                   Pin      Pin               Arrival     No. of    
Name                                           Type              Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------
u_test_wr_ctrl.axi_awaddr_1[27]                GTP_DFF_C         Q        Out     0.290     0.290       -         
axi_awaddr[27]                                 Net               -        -       0.308     -           3         
u_test_wr_ctrl.axi_awvalid_1_sqmuxa_1_25_0     GTP_LUT4          I2       In      -         0.599       -         
u_test_wr_ctrl.axi_awvalid_1_sqmuxa_1_25_0     GTP_LUT4          Z        Out     0.416     1.014       -         
axi_awvalid_1_sqmuxa_1_25_0                    Net               -        -       0.269     -           1         
u_test_wr_ctrl.axi_awvalid_1_sqmuxa_1_25       GTP_LUT5          I4       In      -         1.283       -         
u_test_wr_ctrl.axi_awvalid_1_sqmuxa_1_25       GTP_LUT5          Z        Out     0.176     1.459       -         
axi_awvalid_1_sqmuxa_1_25                      Net               -        -       0.289     -           2         
u_test_wr_ctrl.axi_awvalid10lto29              GTP_LUT5          I4       In      -         1.748       -         
u_test_wr_ctrl.axi_awvalid10lto29              GTP_LUT5          Z        Out     0.176     1.924       -         
axi_awvalid10                                  Net               -        -       0.308     -           3         
u_test_wr_ctrl.axi_awaddr_7_0_cry_6_cco        GTP_LUT3          I2       In      -         2.232       -         
u_test_wr_ctrl.axi_awaddr_7_0_cry_6_cco        GTP_LUT3          Z        Out     0.176     2.408       -         
axi_awaddr_7_0_cry_6_cco                       Net               -        -       0.269     -           1         
u_test_wr_ctrl.axi_awaddr_7_0_cry_6            GTP_LUT5CARRY     I2       In      -         2.677       -         
u_test_wr_ctrl.axi_awaddr_7_0_cry_6            GTP_LUT5CARRY     COUT     Out     0.348     3.025       -         
axi_awaddr_7_0_cry_6                           Net               -        -       0.000     -           1         
u_test_wr_ctrl.axi_awaddr_7_0_cry_7            GTP_LUT5CARRY     CIN      In      -         3.025       -         
u_test_wr_ctrl.axi_awaddr_7_0_cry_7            GTP_LUT5CARRY     COUT     Out     0.034     3.059       -         
axi_awaddr_7_0_cry_7                           Net               -        -       0.000     -           1         
u_test_wr_ctrl.axi_awaddr_7_0_cry_8            GTP_LUT5CARRY     CIN      In      -         3.059       -         
u_test_wr_ctrl.axi_awaddr_7_0_cry_8            GTP_LUT5CARRY     COUT     Out     0.034     3.093       -         
axi_awaddr_7_0_cry_8                           Net               -        -       0.000     -           1         
u_test_wr_ctrl.axi_awaddr_7_0_cry_9            GTP_LUT5CARRY     CIN      In      -         3.093       -         
u_test_wr_ctrl.axi_awaddr_7_0_cry_9            GTP_LUT5CARRY     COUT     Out     0.034     3.127       -         
axi_awaddr_7_0_cry_9                           Net               -        -       0.000     -           1         
u_test_wr_ctrl.axi_awaddr_7_0_cry_10           GTP_LUT5CARRY     CIN      In      -         3.127       -         
u_test_wr_ctrl.axi_awaddr_7_0_cry_10           GTP_LUT5CARRY     COUT     Out     0.034     3.161       -         
axi_awaddr_7_0_cry_10                          Net               -        -       0.000     -           1         
u_test_wr_ctrl.axi_awaddr_7_0_cry_11           GTP_LUT5CARRY     CIN      In      -         3.161       -         
u_test_wr_ctrl.axi_awaddr_7_0_cry_11           GTP_LUT5CARRY     COUT     Out     0.034     3.195       -         
axi_awaddr_7_0_cry_11                          Net               -        -       0.000     -           1         
u_test_wr_ctrl.axi_awaddr_7_0_cry_12           GTP_LUT5CARRY     CIN      In      -         3.195       -         
u_test_wr_ctrl.axi_awaddr_7_0_cry_12           GTP_LUT5CARRY     COUT     Out     0.034     3.229       -         
axi_awaddr_7_0_cry_12                          Net               -        -       0.000     -           1         
u_test_wr_ctrl.axi_awaddr_7_0_cry_13           GTP_LUT5CARRY     CIN      In      -         3.229       -         
u_test_wr_ctrl.axi_awaddr_7_0_cry_13           GTP_LUT5CARRY     COUT     Out     0.034     3.263       -         
axi_awaddr_7_0_cry_13                          Net               -        -       0.000     -           1         
u_test_wr_ctrl.axi_awaddr_7_0_cry_14           GTP_LUT5CARRY     CIN      In      -         3.263       -         
u_test_wr_ctrl.axi_awaddr_7_0_cry_14           GTP_LUT5CARRY     COUT     Out     0.034     3.297       -         
axi_awaddr_7_0_cry_14                          Net               -        -       0.000     -           1         
u_test_wr_ctrl.axi_awaddr_7_0_cry_15           GTP_LUT5CARRY     CIN      In      -         3.297       -         
u_test_wr_ctrl.axi_awaddr_7_0_cry_15           GTP_LUT5CARRY     COUT     Out     0.034     3.331       -         
axi_awaddr_7_0_cry_15                          Net               -        -       0.000     -           1         
u_test_wr_ctrl.axi_awaddr_7_0_cry_16           GTP_LUT5CARRY     CIN      In      -         3.331       -         
u_test_wr_ctrl.axi_awaddr_7_0_cry_16           GTP_LUT5CARRY     COUT     Out     0.034     3.365       -         
axi_awaddr_7_0_cry_16                          Net               -        -       0.000     -           1         
u_test_wr_ctrl.axi_awaddr_7_0_cry_17           GTP_LUT5CARRY     CIN      In      -         3.365       -         
u_test_wr_ctrl.axi_awaddr_7_0_cry_17           GTP_LUT5CARRY     COUT     Out     0.034     3.399       -         
axi_awaddr_7_0_cry_17                          Net               -        -       0.000     -           1         
u_test_wr_ctrl.axi_awaddr_7_0_cry_18           GTP_LUT5CARRY     CIN      In      -         3.399       -         
u_test_wr_ctrl.axi_awaddr_7_0_cry_18           GTP_LUT5CARRY     COUT     Out     0.034     3.433       -         
axi_awaddr_7_0_cry_18                          Net               -        -       0.000     -           1         
u_test_wr_ctrl.axi_awaddr_7_0_cry_19           GTP_LUT5CARRY     CIN      In      -         3.433       -         
u_test_wr_ctrl.axi_awaddr_7_0_cry_19           GTP_LUT5CARRY     COUT     Out     0.034     3.467       -         
axi_awaddr_7_0_cry_19                          Net               -        -       0.000     -           1         
u_test_wr_ctrl.axi_awaddr_7_0_cry_20           GTP_LUT5CARRY     CIN      In      -         3.467       -         
u_test_wr_ctrl.axi_awaddr_7_0_cry_20           GTP_LUT5CARRY     COUT     Out     0.034     3.501       -         
axi_awaddr_7_0_cry_20                          Net               -        -       0.000     -           1         
u_test_wr_ctrl.axi_awaddr_7_0_cry_21           GTP_LUT5CARRY     CIN      In      -         3.501       -         
u_test_wr_ctrl.axi_awaddr_7_0_cry_21           GTP_LUT5CARRY     COUT     Out     0.034     3.535       -         
axi_awaddr_7_0_cry_21                          Net               -        -       0.000     -           1         
u_test_wr_ctrl.axi_awaddr_7_0_cry_22           GTP_LUT5CARRY     CIN      In      -         3.535       -         
u_test_wr_ctrl.axi_awaddr_7_0_cry_22           GTP_LUT5CARRY     COUT     Out     0.034     3.569       -         
axi_awaddr_7_0_cry_22                          Net               -        -       0.000     -           1         
u_test_wr_ctrl.axi_awaddr_7_0_cry_23           GTP_LUT5CARRY     CIN      In      -         3.569       -         
u_test_wr_ctrl.axi_awaddr_7_0_cry_23           GTP_LUT5CARRY     COUT     Out     0.034     3.603       -         
axi_awaddr_7_0_cry_23                          Net               -        -       0.000     -           1         
u_test_wr_ctrl.axi_awaddr_7_0_cry_24           GTP_LUT5CARRY     CIN      In      -         3.603       -         
u_test_wr_ctrl.axi_awaddr_7_0_cry_24           GTP_LUT5CARRY     COUT     Out     0.034     3.637       -         
axi_awaddr_7_0_cry_24                          Net               -        -       0.000     -           1         
u_test_wr_ctrl.axi_awaddr_7_0_cry_25           GTP_LUT5CARRY     CIN      In      -         3.637       -         
u_test_wr_ctrl.axi_awaddr_7_0_cry_25           GTP_LUT5CARRY     COUT     Out     0.034     3.671       -         
axi_awaddr_7_0_cry_25                          Net               -        -       0.000     -           1         
u_test_wr_ctrl.axi_awaddr_7_0_cry_26           GTP_LUT5CARRY     CIN      In      -         3.671       -         
u_test_wr_ctrl.axi_awaddr_7_0_cry_26           GTP_LUT5CARRY     COUT     Out     0.034     3.705       -         
axi_awaddr_7_0_cry_26                          Net               -        -       0.000     -           1         
u_test_wr_ctrl.axi_awaddr_7_0_cry_27           GTP_LUT5CARRY     CIN      In      -         3.705       -         
u_test_wr_ctrl.axi_awaddr_7_0_cry_27           GTP_LUT5CARRY     Z        Out     0.232     3.937       -         
axi_awaddr_7_0[27]                             Net               -        -       0.269     -           1         
u_test_wr_ctrl.axi_awaddr_7[27]                GTP_LUT3          I1       In      -         4.206       -         
u_test_wr_ctrl.axi_awaddr_7[27]                GTP_LUT3          Z        Out     0.306     4.512       -         
axi_awaddr_7[27]                               Net               -        -       0.000     -           1         
u_test_wr_ctrl.axi_awaddr_1[27]                GTP_DFF_C         D        In      -         4.512       -         
==================================================================================================================
Total path delay (propagation time + setup) of 4.492 is 2.780(61.9%) logic and 1.712(38.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: pclk
====================================



Starting Points with Worst Slack
********************************

                                                                                               Starting                                                 Arrival           
Instance                                                                                       Reference     Type           Pin     Net                 Time        Slack 
                                                                                               Clock                                                                      
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.ddr_init_done                    pclk          GTP_DFF_CE     Q       ddrc_init_done      0.290       9.134 
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[1]     pclk          GTP_DFF_CE     Q       cnt[1]              0.290       11.706
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[0]     pclk          GTP_DFF_CE     Q       cnt[0]              0.290       11.754
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[4]     pclk          GTP_DFF_CE     Q       cnt[4]              0.290       12.061
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[5]     pclk          GTP_DFF_CE     Q       cnt[5]              0.290       12.084
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[3]     pclk          GTP_DFF_CE     Q       cnt[3]              0.290       12.191
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[2]     pclk          GTP_DFF_CE     Q       cnt[2]              0.290       12.239
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[6]     pclk          GTP_DFF_CE     Q       cnt[6]              0.290       13.840
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.ddrc_init_start                  pclk          GTP_DFF_PE     Q       ddrc_init_start     0.290       15.070
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.psel       pclk          GTP_DFF_C      Q       init_psel           0.290       15.277
==========================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                   Starting                                                    Required           
Instance                                                           Reference     Type           Pin          Net               Time         Slack 
                                                                   Clock                                                                          
--------------------------------------------------------------------------------------------------------------------------------------------------
u_test_main_ctrl.state[0]                                          pclk          GTP_DFF_P      D            state             10.023       9.134 
u_test_main_ctrl.state[1]                                          pclk          GTP_DFF_C      D            state_ns[1]       10.023       9.134 
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut     pclk          GTP_DDRPHY     PWRITE       ddrc_pwrite       16.782       11.706
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                      pclk          GTP_DDRC       PWRITE       ddrc_pwrite       16.782       11.706
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut     pclk          GTP_DDRPHY     PADDR[2]     ddrc_paddr[2]     18.089       12.784
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                      pclk          GTP_DDRC       PADDR[2]     ddrc_paddr[2]     18.089       12.784
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut     pclk          GTP_DDRPHY     PADDR[7]     ddrc_paddr[7]     17.967       12.835
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                      pclk          GTP_DDRC       PADDR[7]     ddrc_paddr[7]     17.967       12.835
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut     pclk          GTP_DDRPHY     PADDR[9]     ddrc_paddr[9]     18.195       12.889
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                      pclk          GTP_DDRC       PADDR[9]     ddrc_paddr[9]     18.195       12.889
==================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            -0.023
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         10.023

    - Propagation time:                      0.889
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 9.134

    Number of logic level(s):                1
    Starting point:                          u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.ddr_init_done / Q
    Ending point:                            u_test_main_ctrl.state[0] / D
    The start point is clocked by            pclk [rising] on pin CLK
    The end   point is clocked by            axi_clk1 [rising] on pin CLK

Instance / Net                                                                                 Pin      Pin               Arrival     No. of    
Name                                                                            Type           Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.ddr_init_done     GTP_DFF_CE     Q        Out     0.290     0.290       -         
ddrc_init_done                                                                  Net            -        -       0.348     -           5         
u_test_main_ctrl.state_e[0]                                                     GTP_LUT2       I0       In      -         0.638       -         
u_test_main_ctrl.state_e[0]                                                     GTP_LUT2       Z        Out     0.251     0.889       -         
state                                                                           Net            -        -       0.000     -           1         
u_test_main_ctrl.state[0]                                                       GTP_DFF_P      D        In      -         0.889       -         
================================================================================================================================================
Total path delay (propagation time + setup) of 0.866 is 0.518(59.8%) logic and 0.348(40.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      10.000
    - Setup time:                            -0.023
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         10.023

    - Propagation time:                      0.889
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 9.134

    Number of logic level(s):                1
    Starting point:                          u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.ddr_init_done / Q
    Ending point:                            u_test_main_ctrl.state[1] / D
    The start point is clocked by            pclk [rising] on pin CLK
    The end   point is clocked by            axi_clk1 [rising] on pin CLK

Instance / Net                                                                                 Pin      Pin               Arrival     No. of    
Name                                                                            Type           Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.ddr_init_done     GTP_DFF_CE     Q        Out     0.290     0.290       -         
ddrc_init_done                                                                  Net            -        -       0.348     -           5         
u_test_main_ctrl.state_ns[1]                                                    GTP_LUT4       I0       In      -         0.638       -         
u_test_main_ctrl.state_ns[1]                                                    GTP_LUT4       Z        Out     0.251     0.889       -         
state_ns[1]                                                                     Net            -        -       0.000     -           1         
u_test_main_ctrl.state[1]                                                       GTP_DFF_C      D        In      -         0.889       -         
================================================================================================================================================
Total path delay (propagation time + setup) of 0.866 is 0.518(59.8%) logic and 0.348(40.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      20.000
    - Setup time:                            3.218
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         16.782

    - Propagation time:                      5.077
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 11.706

    Number of logic level(s):                3
    Starting point:                          u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[1] / Q
    Ending point:                            u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut / PWRITE
    The start point is clocked by            pclk [rising] on pin CLK
    The end   point is clocked by            pclk [rising] on pin PCLK

Instance / Net                                                                                                        Pin        Pin               Arrival     No. of    
Name                                                                                                   Type           Name       Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[1]             GTP_DFF_CE     Q          Out     0.290     0.290       -         
cnt[1]                                                                                                 Net            -          -       2.773     -           81        
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.un2_pwrite_0_0     GTP_LUT3       I1         In      -         3.063       -         
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.un2_pwrite_0_0     GTP_LUT3       Z          Out     0.306     3.369       -         
un2_pwrite_0_0                                                                                         Net            -          -       0.269     -           1         
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.un2_pwrite         GTP_LUT5       I4         In      -         3.638       -         
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.un2_pwrite         GTP_LUT5       Z          Out     0.176     3.813       -         
un2_pwrite                                                                                             Net            -          -       0.798     -           48        
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.ddrc_pwrite                              GTP_LUT2       I1         In      -         4.612       -         
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.ddrc_pwrite                              GTP_LUT2       Z          Out     0.176     4.788       -         
ddrc_pwrite                                                                                            Net            -          -       0.289     -           2         
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut                                         GTP_DDRPHY     PWRITE     In      -         5.077       -         
=========================================================================================================================================================================
Total path delay (propagation time + setup) of 8.294 is 4.166(50.2%) logic and 4.128(49.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: phy_clk
====================================



Starting Points with Worst Slack
********************************

                                                                 Starting                                                                  Arrival          
Instance                                                         Reference     Type           Pin                Net                       Time        Slack
                                                                 Clock                                                                                      
------------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut     phy_clk       GTP_DDC_E1     IFIFO_RADDR[0]     dqs_ififo_rpoint_0[0]     0.464       1.508
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut     phy_clk       GTP_DDC_E1     IFIFO_RADDR[1]     dqs_ififo_rpoint_0[1]     0.464       1.508
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut     phy_clk       GTP_DDC_E1     IFIFO_RADDR[2]     dqs_ififo_rpoint_0[2]     0.464       1.508
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut     phy_clk       GTP_DDC_E1     IFIFO_RADDR[0]     dqs_ififo_rpoint_1[0]     0.464       1.508
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut     phy_clk       GTP_DDC_E1     IFIFO_RADDR[1]     dqs_ififo_rpoint_1[1]     0.464       1.508
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut     phy_clk       GTP_DDC_E1     IFIFO_RADDR[2]     dqs_ififo_rpoint_1[2]     0.464       1.508
============================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                      Starting                                                             Required          
Instance                                                              Reference     Type            Pin          Net                       Time         Slack
                                                                      Clock                                                                                  
-------------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut     phy_clk       GTP_ISERDES     RADDR[0]     dqs_ififo_rpoint_0[0]     2.380        1.508
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut     phy_clk       GTP_ISERDES     RADDR[1]     dqs_ififo_rpoint_0[1]     2.380        1.508
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut     phy_clk       GTP_ISERDES     RADDR[2]     dqs_ififo_rpoint_0[2]     2.380        1.508
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr4_dut     phy_clk       GTP_ISERDES     RADDR[0]     dqs_ififo_rpoint_0[0]     2.380        1.508
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr4_dut     phy_clk       GTP_ISERDES     RADDR[1]     dqs_ififo_rpoint_0[1]     2.380        1.508
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr4_dut     phy_clk       GTP_ISERDES     RADDR[2]     dqs_ififo_rpoint_0[2]     2.380        1.508
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr5_dut     phy_clk       GTP_ISERDES     RADDR[0]     dqs_ififo_rpoint_0[0]     2.380        1.508
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr5_dut     phy_clk       GTP_ISERDES     RADDR[1]     dqs_ififo_rpoint_0[1]     2.380        1.508
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr5_dut     phy_clk       GTP_ISERDES     RADDR[2]     dqs_ififo_rpoint_0[2]     2.380        1.508
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr6_dut     phy_clk       GTP_ISERDES     RADDR[0]     dqs_ififo_rpoint_0[0]     2.380        1.508
=============================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      2.500
    - Setup time:                            0.120
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.380

    - Propagation time:                      0.872
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     1.508

    Number of logic level(s):                0
    Starting point:                          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut / IFIFO_RADDR[0]
    Ending point:                            u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut / RADDR[0]
    The start point is clocked by            phy_clk [rising] on pin CLKA
    The end   point is clocked by            phy_clk [rising] on pin DESCLK

Instance / Net                                                                        Pin                Pin               Arrival     No. of    
Name                                                                  Type            Name               Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut          GTP_DDC_E1      IFIFO_RADDR[0]     Out     0.464     0.464       -         
dqs_ififo_rpoint_0[0]                                                 Net             -                  -       0.408     -           8         
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut     GTP_ISERDES     RADDR[0]           In      -         0.872       -         
=================================================================================================================================================
Total path delay (propagation time + setup) of 0.992 is 0.584(58.9%) logic and 0.408(41.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      2.500
    - Setup time:                            0.120
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.380

    - Propagation time:                      0.872
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     1.508

    Number of logic level(s):                0
    Starting point:                          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut / IFIFO_RADDR[1]
    Ending point:                            u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut / RADDR[1]
    The start point is clocked by            phy_clk [rising] on pin CLKA
    The end   point is clocked by            phy_clk [rising] on pin DESCLK

Instance / Net                                                                        Pin                Pin               Arrival     No. of    
Name                                                                  Type            Name               Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut          GTP_DDC_E1      IFIFO_RADDR[1]     Out     0.464     0.464       -         
dqs_ififo_rpoint_0[1]                                                 Net             -                  -       0.408     -           8         
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut     GTP_ISERDES     RADDR[1]           In      -         0.872       -         
=================================================================================================================================================
Total path delay (propagation time + setup) of 0.992 is 0.584(58.9%) logic and 0.408(41.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      2.500
    - Setup time:                            0.120
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.380

    - Propagation time:                      0.872
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     1.508

    Number of logic level(s):                0
    Starting point:                          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut / IFIFO_RADDR[2]
    Ending point:                            u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut / RADDR[2]
    The start point is clocked by            phy_clk [rising] on pin CLKA
    The end   point is clocked by            phy_clk [rising] on pin DESCLK

Instance / Net                                                                        Pin                Pin               Arrival     No. of    
Name                                                                  Type            Name               Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut          GTP_DDC_E1      IFIFO_RADDR[2]     Out     0.464     0.464       -         
dqs_ififo_rpoint_0[2]                                                 Net             -                  -       0.408     -           8         
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut     GTP_ISERDES     RADDR[2]           In      -         0.872       -         
=================================================================================================================================================
Total path delay (propagation time + setup) of 0.992 is 0.584(58.9%) logic and 0.408(41.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                                                      Starting                                                            Arrival           
Instance                                                              Reference     Type           Pin               Net                  Time        Slack 
                                                                      Clock                                                                                 
------------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy                  System        GTP_DLL        DELAY_STEP[0]     dll_step_copy[0]     0.000       19.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy                  System        GTP_DLL        DELAY_STEP[1]     dll_step_copy[1]     0.000       19.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy                  System        GTP_DLL        DELAY_STEP[2]     dll_step_copy[2]     0.000       19.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy                  System        GTP_DLL        DELAY_STEP[3]     dll_step_copy[3]     0.000       19.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy                  System        GTP_DLL        DELAY_STEP[4]     dll_step_copy[4]     0.000       19.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy                  System        GTP_DLL        DELAY_STEP[5]     dll_step_copy[5]     0.000       19.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy                  System        GTP_DLL        DELAY_STEP[6]     dll_step_copy[6]     0.000       19.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy                  System        GTP_DLL        DELAY_STEP[7]     dll_step_copy[7]     0.000       19.731
u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1                                System        GTP_PLL_E1     LOCK              pll_lock_c           0.000       19.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dll_hmemc_dut     System        GTP_DLL        LOCK              dll_lock             0.000       19.751
============================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                   Starting                                                 Required           
Instance                                                                           Reference     Type          Pin     Net                  Time         Slack 
                                                                                   Clock                                                                       
---------------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[0]     System        GTP_DFF_C     D       dll_step_copy[0]     20.020       19.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[1]     System        GTP_DFF_C     D       dll_step_copy[1]     20.020       19.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[2]     System        GTP_DFF_C     D       dll_step_copy[2]     20.020       19.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[3]     System        GTP_DFF_C     D       dll_step_copy[3]     20.020       19.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[4]     System        GTP_DFF_C     D       dll_step_copy[4]     20.020       19.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[5]     System        GTP_DFF_C     D       dll_step_copy[5]     20.020       19.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[6]     System        GTP_DFF_C     D       dll_step_copy[6]     20.020       19.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[7]     System        GTP_DFF_C     D       dll_step_copy[7]     20.020       19.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_ddrphy_reset_ctrl.pll_lock_d[0]       System        GTP_DFF_C     D       pll_lock_c           20.020       19.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_ddrphy_reset_ctrl.dll_lock_d[0]       System        GTP_DFF_C     D       dll_lock             20.020       19.751
===============================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      20.000
    - Setup time:                            -0.020
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         20.020

    - Propagation time:                      0.289
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 19.731

    Number of logic level(s):                0
    Starting point:                          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy / DELAY_STEP[0]
    Ending point:                            u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[0] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            pclk [rising] on pin CLK

Instance / Net                                                                                   Pin               Pin               Arrival     No. of    
Name                                                                               Type          Name              Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy                               GTP_DLL       DELAY_STEP[0]     Out     0.000     0.000       -         
dll_step_copy[0]                                                                   Net           -                 -       0.289     -           2         
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[0]     GTP_DFF_C     D                 In      -         0.289       -         
===========================================================================================================================================================
Total path delay (propagation time + setup) of 0.269 is -0.020(-7.4%) logic and 0.289(107.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      20.000
    - Setup time:                            -0.020
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         20.020

    - Propagation time:                      0.289
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 19.731

    Number of logic level(s):                0
    Starting point:                          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy / DELAY_STEP[1]
    Ending point:                            u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[1] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            pclk [rising] on pin CLK

Instance / Net                                                                                   Pin               Pin               Arrival     No. of    
Name                                                                               Type          Name              Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy                               GTP_DLL       DELAY_STEP[1]     Out     0.000     0.000       -         
dll_step_copy[1]                                                                   Net           -                 -       0.289     -           2         
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[1]     GTP_DFF_C     D                 In      -         0.289       -         
===========================================================================================================================================================
Total path delay (propagation time + setup) of 0.269 is -0.020(-7.4%) logic and 0.289(107.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      20.000
    - Setup time:                            -0.020
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         20.020

    - Propagation time:                      0.289
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 19.731

    Number of logic level(s):                0
    Starting point:                          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy / DELAY_STEP[2]
    Ending point:                            u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[2] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            pclk [rising] on pin CLK

Instance / Net                                                                                   Pin               Pin               Arrival     No. of    
Name                                                                               Type          Name              Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy                               GTP_DLL       DELAY_STEP[2]     Out     0.000     0.000       -         
dll_step_copy[2]                                                                   Net           -                 -       0.289     -           2         
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[2]     GTP_DFF_C     D                 In      -         0.289       -         
===========================================================================================================================================================
Total path delay (propagation time + setup) of 0.269 is -0.020(-7.4%) logic and 0.289(107.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied

Finished final timing analysis (Real Time elapsed 0h:00m:23s; CPU Time elapsed 0h:00m:20s; Memory used current: 365MB peak: 403MB)


Finished timing report (Real Time elapsed 0h:00m:23s; CPU Time elapsed 0h:00m:20s; Memory used current: 365MB peak: 403MB)

---------------------------------------
Resource Usage Report for ipsl_hmemc_top_test 

Mapping to part: pgl22gbg324-7
Cell usage:
GTP_DDC_E1      5 uses
GTP_DDRC        1 use
GTP_DDRPHY      1 use
GTP_DFF         3 uses
GTP_DFF_C       187 uses
GTP_DFF_CE      207 uses
GTP_DFF_P       9 uses
GTP_DFF_PE      30 uses
GTP_DLL         2 uses
GTP_GRS         1 use
GTP_INV         54 uses
GTP_IOCLKBUF    2 uses
GTP_IOCLKDIV    1 use
GTP_IODELAY     16 uses
GTP_ISERDES     16 uses
GTP_LUT2        170 uses
GTP_LUT3        104 uses
GTP_LUT4        130 uses
GTP_LUT5        125 uses
GTP_LUT5CARRY   318 uses
GTP_OSERDES     46 uses
GTP_PLL_E1      1 use
GTP_ROM64X1     30 uses

I/O ports: 61
GTP_INBUF      2 uses
GTP_INBUFG     2 uses
GTP_IOBUF      16 uses
GTP_IOBUFCO    2 uses
GTP_OUTBUF     7 uses
GTP_OUTBUFT    28 uses
GTP_OUTBUFTCO  1 use


RAM/ROM usage summary
Distributed Rams : 30.00 of 1110 (2.70%)


Mapping Summary:
Total LUTs: 907 of 17536 (5.17%)
	LUTs as dram: 0 of 4440 (0.00%)
	LUTs as logic: 907 
Total Registers: 436 of 26304 (1.66%)

DRM18K:
Total DRM18K =  0 of 48 (0.00%)

APMs:
Total APMs =  0.00 of 30 (0.00%)

Total I/O primitives =  58 of 240 (24.17%)


 Number of unique control sets:              32
 CLK(clkout1_0_i), C(global_reset_i_0), P(GND), CE(dll_step_copy_synced4_NE_i_0)		: 8
 CLK(clkout1_0_i), C(GND), P(global_reset_i_0), CE(VCC)		: 5
 CLK(clkout1_0_i), C(global_reset_i_0), P(GND), CE(VCC)		: 41
 CLK(clkout1_0_i), C(global_reset_i_0), P(GND), CE(dll_update_n_i_i_0)		: 8
 CLK(clkout1_0_i), C(GND), P(GND), CE(VCC)		: 3
 CLK(clkout1_0_i), C(GND), P(global_reset_i_0), CE(N_82_i_0)		: 1
 CLK(clkout1_0_i), C(global_reset_i_0), P(GND), CE(N_82_i_0)		: 1
 CLK(clkout1_0_i), C(resetn_c_i_0), P(GND), CE(VCC)		: 17
 CLK(clkout1_0_i), C(GND), P(resetn_c_i_0), CE(VCC)		: 1
 CLK(clkout1_0_i), C(resetn_c_i_0), P(GND), CE(N_6_i_0)		: 8
 CLK(clkout1_0_i), C(presetn_i_0), P(GND), CE(VCC)		: 3
 CLK(clkout1_0_i), C(presetn_i_0), P(GND), CE(cnte)		: 7
 CLK(clkout1_0_i), C(resetn_i_0), P(GND), CE(un1_init_preset8_g)		: 1
 CLK(clkout1_0_i), C(GND), P(resetn_i_0), CE(un1_init_preset8_g)		: 1
 CLK(clkout1_0_i), C(GND), P(resetn_i_0), CE(VCC)		: 1
 CLK(clkout1_0_i), C(GND), P(resetn_i_0), CE(ddrc_init_done)		: 1
 CLK(clkout1_0_i), C(resetn_i_0), P(GND), CE(ddrc_init_done)		: 1
 CLK(clkout1_0_i), C(resetn_i_0), P(GND), CE(ddrc_rst_cnte)		: 5
 CLK(clkout1_0_i), C(resetn_i_0), P(GND), CE(rst_cnt7)		: 5
 CLK(clkout3), C(resetn_c_i_0), P(GND), CE(state_0_sqmuxa)		: 29
 CLK(clkout3), C(resetn_c_i_0), P(GND), CE(VCC)		: 126
 CLK(clkout3), C(resetn_c_i_0), P(GND), CE(N_27_i_0)		: 5
 CLK(clkout3), C(resetn_c_i_0), P(GND), CE(rvalid_1)		: 16
 CLK(clkout3), C(resetn_c_i_0), P(GND), CE(N_936_0)		: 8
 CLK(clkout3), C(resetn_c_i_0), P(GND), CE(un1_axi_awlen_1_sqmuxa_g)		: 4
 CLK(clkout3), C(resetn_c_i_0), P(GND), CE(N_54_i_0)		: 16
 CLK(clkout3), C(resetn_c_i_0), P(GND), CE(init_addr7)		: 28
 CLK(clkout3), C(resetn_c_i_0), P(GND), CE(axi_awide)		: 8
 CLK(clkout3), C(resetn_c_i_0), P(GND), CE(execute_wr_cnte)		: 16
 CLK(clkout3), C(resetn_c_i_0), P(GND), CE(N_36_i_0)		: 33
 CLK(clkout3), C(GND), P(resetn_c_i_0), CE(N_36_i_0)		: 27
 CLK(clkout3), C(GND), P(resetn_c_i_0), CE(VCC)		: 2

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:23s; CPU Time elapsed 0h:00m:20s; Memory used current: 226MB peak: 403MB)

Process took 0h:00m:23s realtime, 0h:00m:20s cputime
# Tue May  7 10:00:31 2019

###########################################################]
