// Created by IP Generator (Version 2020.3 build 62942)
// Instantiation Template
//
// Insert the following codes into your Verilog file.
//   * Change the_instance_name to your own instance name.
//   * Change the signal names in the port associations


ila1 the_instance_name (
  .hub_tdi(hub_tdi),      // input
  .hub_tdo(hub_tdo),      // output
  .id_i(id_i),            // input [4:0]
  .capt_i(capt_i),        // input
  .shift_i(shift_i),      // input
  .conf_sel(conf_sel),    // input
  .drck_in(drck_in),      // input
  .clk(clk),              // input
  .resetn_i(resetn_i),    // input
  .trig0_i(trig0_i),      // input [7:0]
  .trig1_i(trig1_i),      // input [8:0]
  .trig2_i(trig2_i),      // input [7:0]
  .trig3_i(trig3_i),      // input
  .trig4_i(trig4_i),      // input [23:0]
  .trig5_i(trig5_i)       // input [2:0]
);
