
#Begin clock constraint
define_clock -name {pll_50_400|clkout3_inferred_clock} {n:pll_50_400|clkout3_inferred_clock} -period 4.542 -clockgroup Autoconstr_clkgroup_0 -rise 0.000 -fall 2.271 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {pll_50_400|clkout1_inferred_clock} {n:pll_50_400|clkout1_inferred_clock} -period 4.420 -clockgroup Autoconstr_clkgroup_1 -rise 0.000 -fall 2.210 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|IOCLK_DIV_inferred_clock} {n:ipsl_phy_io_Z8|IOCLK_DIV_inferred_clock} -period 10000000.000 -clockgroup Autoconstr_clkgroup_2 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[0]} {n:ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[0]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_3 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|ioclk_01_inferred_clock} {n:ipsl_phy_io_Z8|ioclk_01_inferred_clock} -period 0.843 -clockgroup Autoconstr_clkgroup_4 -rise 0.000 -fall 0.422 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[1]} {n:ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[1]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_5 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[2]} {n:ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[2]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_6 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[3]} {n:ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[3]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_7 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|ioclk_02_inferred_clock} {n:ipsl_phy_io_Z8|ioclk_02_inferred_clock} -period 10000000.000 -clockgroup Autoconstr_clkgroup_8 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[4]} {n:ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[4]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_9 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|dqs0_clk_r_inferred_clock} {n:ipsl_phy_io_Z8|dqs0_clk_r_inferred_clock} -period 10000000.000 -clockgroup Autoconstr_clkgroup_10 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[2]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[2]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_11 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|dqs_clkw290_0_inferred_clock} {n:ipsl_phy_io_Z8|dqs_clkw290_0_inferred_clock} -period 10000000.000 -clockgroup Autoconstr_clkgroup_12 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[3]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[3]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_13 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|dqs_90_0_inferred_clock} {n:ipsl_phy_io_Z8|dqs_90_0_inferred_clock} -period 10000000.000 -clockgroup Autoconstr_clkgroup_14 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[4]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[4]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_15 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[5]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[5]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_16 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[6]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[6]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_17 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[7]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[7]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_18 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[9]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[9]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_19 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|dqs_clkw_0_inferred_clock} {n:ipsl_phy_io_Z8|dqs_clkw_0_inferred_clock} -period 10000000.000 -clockgroup Autoconstr_clkgroup_20 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[10]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[10]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_21 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[11]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[11]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_22 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[12]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[12]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_23 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|dqs_ca_clk_r_01_inferred_clock} {n:ipsl_phy_io_Z8|dqs_ca_clk_r_01_inferred_clock} -period 10000000.000 -clockgroup Autoconstr_clkgroup_24 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[17]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[17]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_25 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|dqs_clkw_ca_01_inferred_clock} {n:ipsl_phy_io_Z8|dqs_clkw_ca_01_inferred_clock} -period 10000000.000 -clockgroup Autoconstr_clkgroup_26 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[18]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[18]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_27 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[19]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[19]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_28 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[20]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[20]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_29 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[21]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[21]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_30 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[22]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[22]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_31 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[23]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[23]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_32 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[24]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[24]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_33 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[25]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[25]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_34 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[27]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[27]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_35 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|dqs_90_1_inferred_clock} {n:ipsl_phy_io_Z8|dqs_90_1_inferred_clock} -period 10000000.000 -clockgroup Autoconstr_clkgroup_36 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|dqs1_clk_r_inferred_clock} {n:ipsl_phy_io_Z8|dqs1_clk_r_inferred_clock} -period 10000000.000 -clockgroup Autoconstr_clkgroup_37 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|dqs_clkw290_1_inferred_clock} {n:ipsl_phy_io_Z8|dqs_clkw290_1_inferred_clock} -period 10000000.000 -clockgroup Autoconstr_clkgroup_38 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[28]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[28]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_39 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[29]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[29]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_40 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[31]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[31]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_41 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|dqs_clkw_1_inferred_clock} {n:ipsl_phy_io_Z8|dqs_clkw_1_inferred_clock} -period 10000000.000 -clockgroup Autoconstr_clkgroup_42 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[32]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[32]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_43 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[33]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[33]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_44 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[34]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[34]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_45 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[35]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[35]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_46 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[36]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[36]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_47 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[37]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[37]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_48 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|dqs_ca_clk_r_03_inferred_clock} {n:ipsl_phy_io_Z8|dqs_ca_clk_r_03_inferred_clock} -period 10000000.000 -clockgroup Autoconstr_clkgroup_49 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[40]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[40]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_50 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|dqs_clkw_ca_03_inferred_clock} {n:ipsl_phy_io_Z8|dqs_clkw_ca_03_inferred_clock} -period 10000000.000 -clockgroup Autoconstr_clkgroup_51 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[41]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[41]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_52 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[42]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[42]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_53 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[43]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[43]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_54 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[44]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[44]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_55 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[45]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[45]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_56 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[46]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[46]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_57 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[47]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[47]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_58 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[48]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[48]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_59 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[49]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[49]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_60 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[51]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[51]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_61 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[52]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[52]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_62 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|dqs_ca_clk_r_04_inferred_clock} {n:ipsl_phy_io_Z8|dqs_ca_clk_r_04_inferred_clock} -period 10000000.000 -clockgroup Autoconstr_clkgroup_63 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[55]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[55]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_64 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|dqs_clkw_ca_04_inferred_clock} {n:ipsl_phy_io_Z8|dqs_clkw_ca_04_inferred_clock} -period 10000000.000 -clockgroup Autoconstr_clkgroup_65 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[56]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[56]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_66 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[57]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[57]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_67 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[58]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[58]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_68 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[59]} {n:ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[59]} -period 10000000.000 -clockgroup Autoconstr_clkgroup_69 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_ddrphy_dll_update_ctrl|dll_update_n_inferred_clock} {n:ipsl_ddrphy_dll_update_ctrl|dll_update_n_inferred_clock} -period 10000000.000 -clockgroup Autoconstr_clkgroup_70 -rise 0.000 -fall 5000000.000 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {video_pll|clkout0_inferred_clock} {n:video_pll|clkout0_inferred_clock} -period 5.124 -clockgroup Autoconstr_clkgroup_71 -rise 0.000 -fall 2.562 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {ipsl_hmemc_top_test|sys_clk} {p:ipsl_hmemc_top_test|sys_clk} -period 4.121 -clockgroup Autoconstr_clkgroup_72 -rise 0.000 -fall 2.060 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {video_pll|clkout1_inferred_clock} {n:video_pll|clkout1_inferred_clock} -period 1.157 -clockgroup Autoconstr_clkgroup_73 -rise 0.000 -fall 0.579 -route 0.000 
#End clock constraint
