Project Settings Project Name synplify_pro Device Name synplify_impl: Pango Logos : PGL22G Implementation Name synplify_impl Top Module ipsl_hmemc_top_test Pipelining 1 Retiming 0 Resource Sharing 1 Fanout Guide 10000 Disable I/O Insertion 0 Disable Sequential Optimizations 0 Clock Conversion 1 FSM Compiler 1 Run Status Job Name Status CPU Time Real Time Memory Date/Time (compiler) Complete 97 494 0 - 00m:01s - 2019/5/7 16:40:49 (premap) Complete 22 91 0 0m:03s 0m:03s 232MB 2019/5/7 16:40:53 (fpga_mapper) Complete 429 452 0 0m:34s 0m:44s 460MB 2019/5/7 16:41:38 Area Summary I/O ports (io_port) 78 Dedicated Rams (v_ram) 4 (48) Distributed Rams 30.00 (1110) LUTs (total_luts) 2079 (11%) Timing Summary Clock Name Req Freq Est Freq Slack ipsl_ddrphy_dll_update_ctrl|dll_update_n_inferred_clock 1.0 MHz NA NA ipsl_phy_io_Z8|IOCLK_DIV_inferred_clock 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[2] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[3] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[4] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[5] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[6] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[7] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[9] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[10] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[11] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[12] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[17] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[18] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[19] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[20] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[21] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[22] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[23] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[24] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[25] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[27] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[28] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[29] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[31] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[32] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[33] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[34] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[35] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[36] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[37] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[40] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[41] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[42] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[43] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[44] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[45] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[46] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[47] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[48] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[49] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[51] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[52] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[55] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[56] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[57] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[58] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[59] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[0] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[1] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[2] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[3] 1.0 MHz NA NA ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[4] 1.0 MHz NA NA ipsl_phy_io_Z8|dqs0_clk_r_inferred_clock 1.0 MHz NA NA ipsl_phy_io_Z8|dqs1_clk_r_inferred_clock 1.0 MHz NA NA ipsl_phy_io_Z8|dqs_90_0_inferred_clock 1.0 MHz NA NA ipsl_phy_io_Z8|dqs_90_1_inferred_clock 1.0 MHz NA NA ipsl_phy_io_Z8|dqs_ca_clk_r_01_inferred_clock 1.0 MHz NA NA ipsl_phy_io_Z8|dqs_ca_clk_r_03_inferred_clock 1.0 MHz NA NA ipsl_phy_io_Z8|dqs_ca_clk_r_04_inferred_clock 1.0 MHz NA NA ipsl_phy_io_Z8|dqs_clkw290_0_inferred_clock 1.0 MHz NA NA ipsl_phy_io_Z8|dqs_clkw290_1_inferred_clock 1.0 MHz NA NA ipsl_phy_io_Z8|dqs_clkw_0_inferred_clock 1.0 MHz NA NA ipsl_phy_io_Z8|dqs_clkw_1_inferred_clock 1.0 MHz NA NA ipsl_phy_io_Z8|dqs_clkw_ca_01_inferred_clock 1.0 MHz NA NA ipsl_phy_io_Z8|dqs_clkw_ca_03_inferred_clock 1.0 MHz NA NA ipsl_phy_io_Z8|dqs_clkw_ca_04_inferred_clock 1.0 MHz NA NA ipsl_phy_io_Z8|ioclk_01_inferred_clock 1.0 MHz 1008.1 MHz 999.008 ipsl_phy_io_Z8|ioclk_02_inferred_clock 1.0 MHz NA NA pll_50_400|clkout1_inferred_clock 1.0 MHz 120.6 MHz 991.706 pll_50_400|clkout3_inferred_clock 1.0 MHz 150.7 MHz 993.364 sys_clk 50.0 MHz 197.4 MHz 14.934 video_pll|clkout0_inferred_clock 1.0 MHz 179.2 MHz 994.419 video_pll|clkout1_inferred_clock 1.0 MHz 734.4 MHz 998.638 System 1.0 MHz 780.5 MHz 998.719 Optimizations Summary Combined Clock Conversion 1 / 75