#Build: Synplify Pro (R) P-2019.03P-Beta2, Build 3717R, Feb 25 2019
#install: C:\pango\PDS_2019.1-patch2\syn
#OS: Windows 7 6.1
#Hostname: ALINX000007-PC

# Tue May  7 16:40:48 2019

#Implementation: synplify_impl


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03P-Beta2
Install: C:\pango\PDS_2019.1-patch2\syn
OS: Windows 6.1

Hostname: ALINX000007-PC

Implementation : synplify_impl
Synopsys HDL Compiler, Version comp2019q1p1, Build 007R, Built Feb 26 2019 11:45:06

@N: :  | Running in 64-bit mode 
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03P-Beta2
Install: C:\pango\PDS_2019.1-patch2\syn
OS: Windows 6.1

Hostname: ALINX000007-PC

Implementation : synplify_impl
Synopsys Verilog Compiler, Version comp2019q1p1, Build 007R, Built Feb 26 2019 11:45:06

@N: :  | Running in 64-bit mode 
@I::"C:\pango\PDS_2019.1-patch2\syn\lib\generic\logos.v" (library work)
@I::"C:\pango\PDS_2019.1-patch2\syn\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\pango\PDS_2019.1-patch2\syn\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\pango\PDS_2019.1-patch2\syn\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\pango\PDS_2019.1-patch2\syn\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\pll\pll_50_400.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_apb_reset.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrc_reset_ctrl.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_dll_update_ctrl.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_reset_ctrl.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_training_ctrl.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_ddrphy_update_ctrl.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_hmemc_ddrc_top.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_hmemc_phy_top.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\rtl\ipsl_phy_io.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\ddr3.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\example_design\rtl\ipsl_hmemc_top_test.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\dvi_encoder.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\encode.v" (library work)
@W:CS141 : encode.v(7) | Unrecognized synthesis directive name. Verify the correct directive name.
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\dvi_tx\serdes_4b_10to1.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_cmd.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_sec_read_write.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\sd_card_top.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\sd_card\spi_master.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\aq_axi_master.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\ax_debounce.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\bmp_read.v" (library work)
@W:CS141 : bmp_read.v(111) | Unrecognized synthesis directive header. Verify the correct directive name.
@W:CS141 : bmp_read.v(116) | Unrecognized synthesis directive length. Verify the correct directive name.
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\color_bar.v" (library work)
@I:"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\color_bar.v":"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\video_define.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_read.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_fifo_write.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\frame_read_write.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\sd_card_bmp.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\src\video_timing_data.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_v1_3_afifo_64i_32o_128.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_32i_64o_256\rtl\ipml_fifo_v1_3_afifo_32i_64o_256.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\afifo_64i_32o_128.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_32i_64o_256\afifo_32i_64o_256.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\video_pll\video_pll.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_fifo_ctrl_v1_3.v" (library work)
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_64i_32o_128\rtl\ipml_sdpram_v1_3_afifo_64i_32o_128.v" (library work)
@W:CS141 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(289) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(295) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(301) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(307) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(311) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(315) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(319) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(323) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(327) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(331) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(335) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(339) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(343) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(347) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(351) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(355) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(359) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(363) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(367) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(372) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(376) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(381) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(385) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(389) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(393) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(397) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@N:CG347 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(656) | Read a parallel_case directive.
@I::"D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\source\afifo_32i_64o_256\rtl\ipml_sdpram_v1_3_afifo_32i_64o_256.v" (library work)
@W:CS141 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(289) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(295) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(301) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(307) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(311) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(315) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(319) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(323) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(327) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(331) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(335) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(339) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(343) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(347) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(351) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(355) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(359) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(363) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(367) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(372) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(376) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(381) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(385) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(389) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(393) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@W:CS141 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(397) | Unrecognized synthesis directive pap_error. Verify the correct directive name.
@N:CG347 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(656) | Read a parallel_case directive.
Verilog syntax check successful!

Compiler output is up to date.  No re-compile necessary

Selecting top level module ipsl_hmemc_top_test
@N:CG364 : logos.v(2251) | Synthesizing module GTP_PLL_E1 in library work.
Running optimization stage 1 on GTP_PLL_E1 .......
@N:CG364 : video_pll.v(4) | Synthesizing module video_pll in library work.
@W:CG781 : video_pll.v(255) | Input DUTYF on instance u_pll_e1 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : video_pll.v(261) | Input PHASEF on instance u_pll_e1 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : video_pll.v(267) | Input CPHASEF on instance u_pll_e1 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG360 : video_pll.v(104) | Removing wire clkfb, as there is no assignment to it.
@W:CG360 : video_pll.v(107) | Removing wire pfden, as there is no assignment to it.
@W:CG360 : video_pll.v(108) | Removing wire clkout0_gate, as there is no assignment to it.
@W:CG360 : video_pll.v(109) | Removing wire clkout0_2pad_gate, as there is no assignment to it.
@W:CG360 : video_pll.v(110) | Removing wire clkout1_gate, as there is no assignment to it.
@W:CG360 : video_pll.v(111) | Removing wire clkout2_gate, as there is no assignment to it.
@W:CG360 : video_pll.v(112) | Removing wire clkout3_gate, as there is no assignment to it.
@W:CG360 : video_pll.v(113) | Removing wire clkout4_gate, as there is no assignment to it.
@W:CG360 : video_pll.v(114) | Removing wire clkout5_gate, as there is no assignment to it.
@W:CG360 : video_pll.v(115) | Removing wire dyn_idiv, as there is no assignment to it.
@W:CG360 : video_pll.v(116) | Removing wire dyn_odiv0, as there is no assignment to it.
@W:CG360 : video_pll.v(117) | Removing wire dyn_odiv1, as there is no assignment to it.
@W:CG360 : video_pll.v(118) | Removing wire dyn_odiv2, as there is no assignment to it.
@W:CG360 : video_pll.v(119) | Removing wire dyn_odiv3, as there is no assignment to it.
@W:CG360 : video_pll.v(120) | Removing wire dyn_odiv4, as there is no assignment to it.
@W:CG360 : video_pll.v(121) | Removing wire dyn_fdiv, as there is no assignment to it.
@W:CG360 : video_pll.v(122) | Removing wire dyn_duty0, as there is no assignment to it.
@W:CG360 : video_pll.v(123) | Removing wire dyn_duty1, as there is no assignment to it.
@W:CG360 : video_pll.v(124) | Removing wire dyn_duty2, as there is no assignment to it.
@W:CG360 : video_pll.v(125) | Removing wire dyn_duty3, as there is no assignment to it.
@W:CG360 : video_pll.v(126) | Removing wire dyn_duty4, as there is no assignment to it.
@W:CG360 : video_pll.v(127) | Removing wire dyn_phase0, as there is no assignment to it.
@W:CG360 : video_pll.v(128) | Removing wire dyn_phase1, as there is no assignment to it.
@W:CG360 : video_pll.v(129) | Removing wire dyn_phase2, as there is no assignment to it.
@W:CG360 : video_pll.v(130) | Removing wire dyn_phase3, as there is no assignment to it.
@W:CG360 : video_pll.v(131) | Removing wire dyn_phase4, as there is no assignment to it.
@W:CG360 : video_pll.v(135) | Removing wire icp_base, as there is no assignment to it.
@W:CG360 : video_pll.v(136) | Removing wire icp_sel, as there is no assignment to it.
@W:CG360 : video_pll.v(137) | Removing wire lpfres_sel, as there is no assignment to it.
@W:CG360 : video_pll.v(138) | Removing wire cripple_sel, as there is no assignment to it.
@W:CG360 : video_pll.v(139) | Removing wire phase_sel, as there is no assignment to it.
@W:CG360 : video_pll.v(140) | Removing wire phase_dir, as there is no assignment to it.
@W:CG360 : video_pll.v(141) | Removing wire phase_step_n, as there is no assignment to it.
@W:CG360 : video_pll.v(142) | Removing wire load_phase, as there is no assignment to it.
@W:CG360 : video_pll.v(143) | Removing wire dyn_mdiv, as there is no assignment to it.
Running optimization stage 1 on video_pll .......
@N:CG364 : ax_debounce.v(32) | Synthesizing module ax_debounce in library work.
@N:CG179 : ax_debounce.v(97) | Removing redundant assignment.
Running optimization stage 1 on ax_debounce .......
@N:CG364 : bmp_read.v(28) | Synthesizing module bmp_read in library work.
Running optimization stage 1 on bmp_read .......
@W:CL271 : bmp_read.v(100) | Pruning unused bits 31 to 16 of width_16[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@A:CL282 : bmp_read.v(100) | Feedback mux created for signal width[15:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@W:CL190 : bmp_read.v(202) | Optimizing register bit state_code[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : bmp_read.v(202) | Optimizing register bit state_code[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL279 : bmp_read.v(202) | Pruning register bits 3 to 2 of state_code[3:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@N:CG364 : sd_card_sec_read_write.v(29) | Synthesizing module sd_card_sec_read_write in library work.

	SPI_LOW_SPEED_DIV=32'b00000000000000000000000011111000
	SPI_HIGH_SPEED_DIV=32'b00000000000000000000000000000000
	S_IDLE=32'b00000000000000000000000000000000
	S_CMD0=32'b00000000000000000000000000000001
	S_CMD8=32'b00000000000000000000000000000010
	S_CMD55=32'b00000000000000000000000000000011
	S_CMD41=32'b00000000000000000000000000000100
	S_CMD17=32'b00000000000000000000000000000101
	S_READ=32'b00000000000000000000000000000110
	S_CMD24=32'b00000000000000000000000000000111
	S_WRITE=32'b00000000000000000000000000001000
	S_ERR=32'b00000000000000000000000000001110
	S_WRITE_END=32'b00000000000000000000000000001111
	S_READ_END=32'b00000000000000000000000000010000
	S_WAIT_READ_WRITE=32'b00000000000000000000000000010001
	S_CMD16=32'b00000000000000000000000000010010
   Generated name = sd_card_sec_read_write_Z1
@W:CG133 : sd_card_sec_read_write.v(65) | Object read_data is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : sd_card_sec_read_write.v(66) | Object timer is declared but not assigned. Either assign a value or remove the declaration.
Running optimization stage 1 on sd_card_sec_read_write_Z1 .......
@W:CL190 : sd_card_sec_read_write.v(92) | Optimizing register bit cmd[46] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : sd_card_sec_read_write.v(92) | Optimizing register bit cmd[47] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : sd_card_sec_read_write.v(92) | Optimizing register bit cmd_data_len[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : sd_card_sec_read_write.v(92) | Optimizing register bit cmd_data_len[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : sd_card_sec_read_write.v(92) | Optimizing register bit cmd_data_len[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : sd_card_sec_read_write.v(92) | Optimizing register bit cmd_data_len[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : sd_card_sec_read_write.v(92) | Optimizing register bit cmd_data_len[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : sd_card_sec_read_write.v(92) | Optimizing register bit cmd_data_len[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : sd_card_sec_read_write.v(92) | Optimizing register bit cmd_data_len[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : sd_card_sec_read_write.v(92) | Optimizing register bit cmd_data_len[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : sd_card_sec_read_write.v(92) | Optimizing register bit cmd_data_len[9] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : sd_card_sec_read_write.v(92) | Optimizing register bit cmd_data_len[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : sd_card_sec_read_write.v(92) | Optimizing register bit cmd_data_len[11] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : sd_card_sec_read_write.v(92) | Optimizing register bit cmd_data_len[12] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : sd_card_sec_read_write.v(92) | Optimizing register bit cmd_data_len[13] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : sd_card_sec_read_write.v(92) | Optimizing register bit cmd_data_len[14] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : sd_card_sec_read_write.v(92) | Optimizing register bit cmd_data_len[15] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : sd_card_sec_read_write.v(92) | Optimizing register bit cmd_r1[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : sd_card_sec_read_write.v(92) | Optimizing register bit cmd_r1[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : sd_card_sec_read_write.v(92) | Optimizing register bit cmd_r1[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : sd_card_sec_read_write.v(92) | Optimizing register bit cmd_r1[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : sd_card_sec_read_write.v(92) | Optimizing register bit cmd_r1[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : sd_card_sec_read_write.v(92) | Optimizing register bit cmd_r1[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : sd_card_sec_read_write.v(92) | Optimizing register bit cmd_r1[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL279 : sd_card_sec_read_write.v(92) | Pruning register bits 7 to 1 of cmd_r1[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL279 : sd_card_sec_read_write.v(92) | Pruning register bits 15 to 3 of cmd_data_len[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL279 : sd_card_sec_read_write.v(92) | Pruning register bits 1 to 0 of cmd_data_len[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL279 : sd_card_sec_read_write.v(92) | Pruning register bits 47 to 46 of cmd[47:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@N:CG364 : sd_card_cmd.v(32) | Synthesizing module sd_card_cmd in library work.
Running optimization stage 1 on sd_card_cmd .......
@N:CG364 : spi_master.v(29) | Synthesizing module spi_master in library work.
Running optimization stage 1 on spi_master .......
@N:CG364 : sd_card_top.v(29) | Synthesizing module sd_card_top in library work.
Running optimization stage 1 on sd_card_top .......
@N:CG364 : sd_card_bmp.v(29) | Synthesizing module sd_card_bmp in library work.
@W:CG781 : sd_card_bmp.v(103) | Input sd_sec_write_data on instance sd_card_top_m0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
Running optimization stage 1 on sd_card_bmp .......
@N:CG364 : encode.v(46) | Synthesizing module encode in library work.
Running optimization stage 1 on encode .......
@N:CG364 : logos.v(2154) | Synthesizing module GTP_OSERDES in library work.
Running optimization stage 1 on GTP_OSERDES .......
@N:CG364 : logos.v(2212) | Synthesizing module GTP_OUTBUFT in library work.
Running optimization stage 1 on GTP_OUTBUFT .......
@N:CG364 : serdes_4b_10to1.v(3) | Synthesizing module serdes_4b_10to1 in library work.
Running optimization stage 1 on serdes_4b_10to1 .......
@N:CG364 : dvi_encoder.v(2) | Synthesizing module dvi_encoder in library work.
Running optimization stage 1 on dvi_encoder .......
@N:CG364 : color_bar.v(33) | Synthesizing module color_bar in library work.
@N:CG179 : color_bar.v(222) | Removing redundant assignment.
@N:CG179 : color_bar.v(235) | Removing redundant assignment.
@N:CG179 : color_bar.v(247) | Removing redundant assignment.
@N:CG179 : color_bar.v(259) | Removing redundant assignment.
@N:CG179 : color_bar.v(271) | Removing redundant assignment.
@N:CG179 : color_bar.v(283) | Removing redundant assignment.
@N:CG179 : color_bar.v(345) | Removing redundant assignment.
@N:CG179 : color_bar.v(346) | Removing redundant assignment.
@N:CG179 : color_bar.v(347) | Removing redundant assignment.
@W:CG133 : color_bar.v(174) | Object active_y is declared but not assigned. Either assign a value or remove the declaration.
Running optimization stage 1 on color_bar .......
@N:CG364 : video_timing_data.v(30) | Synthesizing module video_timing_data in library work.

	DATA_WIDTH=32'b00000000000000000000000000100000
   Generated name = video_timing_data_32s
Running optimization stage 1 on video_timing_data_32s .......
@A:CL282 : video_timing_data.v(63) | Feedback mux created for signal video_vs_d1. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:CL282 : video_timing_data.v(63) | Feedback mux created for signal video_hs_d1. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:CL282 : video_timing_data.v(63) | Feedback mux created for signal video_de_d1. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@N:CG364 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(20) | Synthesizing module ipml_sdpram_v1_3_afifo_32i_64o_256 in library work.

	c_SIM_DEVICE=48'b010100000100011101001100001100100011001001000111
	c_WR_ADDR_WIDTH=32'b00000000000000000000000000001001
	c_WR_DATA_WIDTH=32'b00000000000000000000000000100000
	c_RD_ADDR_WIDTH=32'b00000000000000000000000000001000
	c_RD_DATA_WIDTH=32'b00000000000000000000000001000000
	c_OUTPUT_REG=32'b00000000000000000000000000000000
	c_RD_OCE_EN=32'b00000000000000000000000000000000
	c_WR_ADDR_STROBE_EN=32'b00000000000000000000000000000000
	c_RD_ADDR_STROBE_EN=32'b00000000000000000000000000000000
	c_WR_CLK_EN=32'b00000000000000000000000000000001
	c_RD_CLK_EN=32'b00000000000000000000000000000001
	c_RD_CLK_OR_POL_INV=32'b00000000000000000000000000000000
	c_RESET_TYPE=192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010011010110010100111001000011010111110101001001000101010100110100010101010100
	c_POWER_OPT=32'b00000000000000000000000000000000
	c_INIT_FILE=32'b01001110010011110100111001000101
	c_INIT_FORMAT=24'b010000100100100101001110
	c_WR_BYTE_EN=32'b00000000000000000000000000000000
	c_BE_WIDTH=32'b00000000000000000000000000000100
	MODE_9K=32'b00000000000000000000000000000000
	MODE_18K=32'b00000000000000000000000000000001
	c_WR_BYTE_WIDTH=32'b00000000000000000000000000001000
	DATA_WIDTH_WIDE=32'b00000000000000000000000001000000
	ADDR_WIDTH_WIDE=32'b00000000000000000000000000001000
	DATA_WIDTH_NARROW=32'b00000000000000000000000000100000
	ADDR_WIDTH_NARROW=32'b00000000000000000000000000001001
	DATA_WIDTH_W2N=32'b00000000000000000000000000000000
	N_DATA_1_WIDTH=32'b00000000000000000000000000100000
	L_DATA_1_WIDTH=32'b00000000000000000000000000100000
	N_DATA_WIDTH_2_WIDE=32'b00000000000000000000000000100000
	L_DATA_WIDTH_2_WIDE=32'b00000000000000000000000000100000
	N_DATA_WIDTH_4_WIDE=32'b00000000000000000000000000100000
	L_DATA_WIDTH_4_WIDE=32'b00000000000000000000000000100000
	N_DATA_WIDTH_8_WIDE=32'b00000000000000000000000000100000
	L_DATA_WIDTH_8_WIDE=32'b00000000000000000000000000100000
	N_DATA_WIDTH_16_WIDE=32'b00000000000000000000000000100000
	L_DATA_WIDTH_16_WIDE=32'b00000000000000000000000000100000
	N_DATA_WIDTH_32_WIDE=32'b00000000000000000000000000100000
	L_DATA_WIDTH_32_WIDE=32'b00000000000000000000000000100000
	N_BYTE_DATA_1_WIDTH=32'b00000000000000000000000000100000
	L_BYTE_DATA_1_WIDTH=32'b00000000000000000000000000100000
	N_BYTE_DATA_WIDTH_2_WIDE=32'b00000000000000000000000000100000
	L_BYTE_DATA_WIDTH_2_WIDE=32'b00000000000000000000000000100000
	N_BYTE_DATA_WIDTH_4_WIDE=32'b00000000000000000000000000100000
	L_BYTE_DATA_WIDTH_4_WIDE=32'b00000000000000000000000000100000
	WIDTH_RATIO=32'b00000000000000000000000000000010
	N_DRM_DATA_WIDTH_A=32'b00000000000000000000000000010000
	L_DRM_DATA_WIDTH_A=32'b00000000000000000000000000010000
	N_DRM_DATA_WIDTH_B=32'b00000000000000000000000000100000
	L_DRM_DATA_WIDTH_B=32'b00000000000000000000000000100000
	N_BYTE_DATA_WIDTH_A=32'b00000000000000000000000000010000
	L_BYTE_DATA_WIDTH_A=32'b00000000000000000000000000010000
	N_BYTE_DATA_WIDTH_B=32'b00000000000000000000000000100000
	L_BYTE_DATA_WIDTH_B=32'b00000000000000000000000000100000
	DRM_DATA_WIDTH_A=32'b00000000000000000000000000010000
	DRM_DATA_WIDTH_B=32'b00000000000000000000000000100000
	DATA_LOOP_NUM=32'b00000000000000000000000000000010
	Q_DRM_DATA_WIDTH_B=32'b00000000000000000000000000010000
	Q_DRM_DATA_WIDTH_A=32'b00000000000000000000000000010000
	D_DRM_DATA_WIDTH_A=32'b00000000000000000000000000010000
	D_DRM_DATA_WIDTH_B=32'b00000000000000000000000000010000
	DRM_ADDR_WIDTH_A=32'b00000000000000000000000000001010
	DRM_ADDR_WIDTH_B=32'b00000000000000000000000000001001
	ADDR_WIDTH_A=32'b00000000000000000000000000001010
	CS_ADDR_WIDTH_A=32'b00000000000000000000000000000000
	ADDR_WIDTH_B=32'b00000000000000000000000000001001
	CS_ADDR_WIDTH_B=32'b00000000000000000000000000000000
	ADDR_LOOP_NUM_A=32'b00000000000000000000000000000001
	ADDR_LOOP_NUM_B=32'b00000000000000000000000000000001
	CAS_DATA_WIDTH_A=32'b00000000000000000000000000100000
	CAS_DATA_WIDTH_B=32'b00000000000000000000000001000000
	Q_CAS_DATA_WIDTH_A=32'b00000000000000000000000000100000
	Q_CAS_DATA_WIDTH_B=32'b00000000000000000000000000100000
	D_CAS_DATA_WIDTH_A=32'b00000000000000000000000000100000
	D_CAS_DATA_WIDTH_B=32'b00000000000000000000000000100000
	WR_BYTE_WIDTH_A=32'b00000000000000000000000000001000
	WR_BYTE_WIDTH_B=32'b00000000000000000000000000001000
	MASK_NUM_A=32'b00000000000000000000000000000100
	MASK_NUM_B=32'b00000000000000000000000000000100
	c_RST_TYPE=144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010011010110010100111001000011
	CS_ADDR_A_3_LSB=32'b00000000000000000000000000001000
	CS_ADDR_A_4_LSB=32'b00000000000000000000000000001000
	MODE_RATIO=32'b00000000000000000000000000000100
	CS_ADDR_B_3_LSB=32'b00000000000000000000000000000111
	CS_ADDR_B_4_LSB=32'b00000000000000000000000000000111
	RD_ADDR_SEL_LSB=32'b00000000000000000000000000001000
   Generated name = ipml_sdpram_v1_3_afifo_32i_64o_256_Z2
@W:CG390 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(450) | Repeat multiplier in concatenation evaluates to 0
@W:CG390 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(454) | Repeat multiplier in concatenation evaluates to 0
@W:CG390 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(454) | Repeat multiplier in concatenation evaluates to 0
@W:CG532 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(287) | Within an initial block, only Verilog force statements and memory $readmemh/$readmemb initialization statements are recognized, and all other content is ignored.
@N:CG364 : logos.v(1409) | Synthesizing module GTP_DRM18K in library work.
Running optimization stage 1 on GTP_DRM18K .......
@W:CG133 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(552) | Object gen_j_wd is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(1064) | Object cs_rd is declared but not assigned. Either assign a value or remove the declaration.
Running optimization stage 1 on ipml_sdpram_v1_3_afifo_32i_64o_256_Z2 .......
@W:CL169 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(1053) | Pruning unused register addr_bus_rd_invt[0:1]. Make sure that there are no unused intermediate registers.
@W:CL169 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(1044) | Pruning unused register addr_bus_rd_oce[0:1]. Make sure that there are no unused intermediate registers.
@W:CL169 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(1035) | Pruning unused register addr_bus_rd_ce[0:1]. Make sure that there are no unused intermediate registers.
@W:CL169 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(639) | Pruning unused register rd_addr_bsel_rd_invt[3:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(625) | Pruning unused register rd_addr_bsel_rd_oce[3:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(604) | Pruning unused register rd_addr_bsel_rd_ce[3:0]. Make sure that there are no unused intermediate registers.
@N:CG364 : ipml_fifo_ctrl_v1_3.v(21) | Synthesizing module ipml_fifo_ctrl_v1_3 in library work.

	c_WR_DEPTH_WIDTH=32'b00000000000000000000000000001001
	c_RD_DEPTH_WIDTH=32'b00000000000000000000000000001000
	c_FIFO_TYPE=32'b01000001010100110101100101001110
	c_ALMOST_FULL_NUM=32'b00000000000000000000000111111100
	c_ALMOST_EMPTY_NUM=32'b00000000000000000000000000000100
   Generated name = ipml_fifo_ctrl_v1_3_9s_8s_ASYN_508s_4s
@W:CG133 : ipml_fifo_ctrl_v1_3.v(73) | Object asyn_almost_full is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : ipml_fifo_ctrl_v1_3.v(75) | Object asyn_almost_empty is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : ipml_fifo_ctrl_v1_3.v(76) | Object syn_wfull is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : ipml_fifo_ctrl_v1_3.v(77) | Object syn_almost_full is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : ipml_fifo_ctrl_v1_3.v(78) | Object syn_rempty is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : ipml_fifo_ctrl_v1_3.v(79) | Object syn_almost_empty is declared but not assigned. Either assign a value or remove the declaration.
Running optimization stage 1 on ipml_fifo_ctrl_v1_3_9s_8s_ASYN_508s_4s .......
@W:CL169 : ipml_fifo_ctrl_v1_3.v(154) | Pruning unused register ASYN_CTRL.raddr_msb. Make sure that there are no unused intermediate registers.
@W:CL169 : ipml_fifo_ctrl_v1_3.v(106) | Pruning unused register ASYN_CTRL.waddr_msb. Make sure that there are no unused intermediate registers.
@W:CL265 : ipml_fifo_ctrl_v1_3.v(171) | Removing unused bit 0 of ASYN_CTRL.rwptr1[9:0]. Either assign all bits or reduce the width of the signal.
@W:CL265 : ipml_fifo_ctrl_v1_3.v(171) | Removing unused bit 0 of ASYN_CTRL.rwptr2[9:0]. Either assign all bits or reduce the width of the signal.
@W:CL265 : ipml_fifo_ctrl_v1_3.v(106) | Removing unused bit 0 of ASYN_CTRL.wptr[9:0]. Either assign all bits or reduce the width of the signal.
@N:CG364 : ipml_fifo_v1_3_afifo_32i_64o_256.v(25) | Synthesizing module ipml_fifo_v1_3_afifo_32i_64o_256 in library work.

	c_SIM_DEVICE=48'b010100000100011101001100001100100011001001000111
	c_WR_DEPTH_WIDTH=32'b00000000000000000000000000001001
	c_WR_DATA_WIDTH=32'b00000000000000000000000000100000
	c_RD_DEPTH_WIDTH=32'b00000000000000000000000000001000
	c_RD_DATA_WIDTH=32'b00000000000000000000000001000000
	c_OUTPUT_REG=32'b00000000000000000000000000000000
	c_RD_OCE_EN=32'b00000000000000000000000000000000
	c_RESET_TYPE=192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010011010110010100111001000011010111110101001001000101010100110100010101010100
	c_POWER_OPT=32'b00000000000000000000000000000000
	c_RD_CLK_OR_POL_INV=32'b00000000000000000000000000000000
	c_WR_BYTE_EN=32'b00000000000000000000000000000000
	c_BE_WIDTH=32'b00000000000000000000000000000100
	c_FIFO_TYPE=32'b01000001010100110101100101001110
	c_ALMOST_FULL_NUM=32'b00000000000000000000000111111100
	c_ALMOST_EMPTY_NUM=32'b00000000000000000000000000000100
   Generated name = ipml_fifo_v1_3_afifo_32i_64o_256_Z3
Running optimization stage 1 on ipml_fifo_v1_3_afifo_32i_64o_256_Z3 .......
@N:CG364 : afifo_32i_64o_256.v(18) | Synthesizing module afifo_32i_64o_256 in library work.
@W:CG390 : afifo_32i_64o_256.v(142) | Repeat multiplier in concatenation evaluates to 0
@W:CG360 : afifo_32i_64o_256.v(120) | Removing wire wr_byte_en, as there is no assignment to it.
@W:CG360 : afifo_32i_64o_256.v(128) | Removing wire rd_oce, as there is no assignment to it.
Running optimization stage 1 on afifo_32i_64o_256 .......
@N:CG364 : frame_fifo_write.v(31) | Synthesizing module frame_fifo_write in library work.

	MEM_DATA_BITS=32'b00000000000000000000000001000000
	ADDR_BITS=32'b00000000000000000000000000011001
	BUSRT_BITS=32'b00000000000000000000000000001010
	BURST_SIZE=32'b00000000000000000000000001000000
	ONE=256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001
	ZERO=256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
	S_IDLE=32'b00000000000000000000000000000000
	S_ACK=32'b00000000000000000000000000000001
	S_CHECK_FIFO=32'b00000000000000000000000000000010
	S_WRITE_BURST=32'b00000000000000000000000000000011
	S_WRITE_BURST_END=32'b00000000000000000000000000000100
	S_END=32'b00000000000000000000000000000101
   Generated name = frame_fifo_write_Z4
Running optimization stage 1 on frame_fifo_write_Z4 .......
@W:CL190 : frame_fifo_write.v(106) | Optimizing register bit wr_burst_len[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : frame_fifo_write.v(106) | Optimizing register bit wr_burst_len[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : frame_fifo_write.v(106) | Optimizing register bit wr_burst_len[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : frame_fifo_write.v(106) | Optimizing register bit wr_burst_len[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : frame_fifo_write.v(106) | Optimizing register bit wr_burst_len[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : frame_fifo_write.v(106) | Optimizing register bit wr_burst_len[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : frame_fifo_write.v(106) | Optimizing register bit wr_burst_len[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : frame_fifo_write.v(106) | Optimizing register bit wr_burst_len[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : frame_fifo_write.v(106) | Optimizing register bit wr_burst_len[9] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL279 : frame_fifo_write.v(106) | Pruning register bits 9 to 7 of wr_burst_len[9:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL279 : frame_fifo_write.v(106) | Pruning register bits 5 to 0 of wr_burst_len[9:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@N:CG364 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(20) | Synthesizing module ipml_sdpram_v1_3_afifo_64i_32o_128 in library work.

	c_SIM_DEVICE=48'b010100000100011101001100001100100011001001000111
	c_WR_ADDR_WIDTH=32'b00000000000000000000000000001000
	c_WR_DATA_WIDTH=32'b00000000000000000000000001000000
	c_RD_ADDR_WIDTH=32'b00000000000000000000000000001001
	c_RD_DATA_WIDTH=32'b00000000000000000000000000100000
	c_OUTPUT_REG=32'b00000000000000000000000000000000
	c_RD_OCE_EN=32'b00000000000000000000000000000000
	c_WR_ADDR_STROBE_EN=32'b00000000000000000000000000000000
	c_RD_ADDR_STROBE_EN=32'b00000000000000000000000000000000
	c_WR_CLK_EN=32'b00000000000000000000000000000001
	c_RD_CLK_EN=32'b00000000000000000000000000000001
	c_RD_CLK_OR_POL_INV=32'b00000000000000000000000000000000
	c_RESET_TYPE=192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010011010110010100111001000011010111110101001001000101010100110100010101010100
	c_POWER_OPT=32'b00000000000000000000000000000000
	c_INIT_FILE=32'b01001110010011110100111001000101
	c_INIT_FORMAT=24'b010000100100100101001110
	c_WR_BYTE_EN=32'b00000000000000000000000000000000
	c_BE_WIDTH=32'b00000000000000000000000000000100
	MODE_9K=32'b00000000000000000000000000000000
	MODE_18K=32'b00000000000000000000000000000001
	c_WR_BYTE_WIDTH=32'b00000000000000000000000000001000
	DATA_WIDTH_WIDE=32'b00000000000000000000000001000000
	ADDR_WIDTH_WIDE=32'b00000000000000000000000000001000
	DATA_WIDTH_NARROW=32'b00000000000000000000000000100000
	ADDR_WIDTH_NARROW=32'b00000000000000000000000000001001
	DATA_WIDTH_W2N=32'b00000000000000000000000000000001
	N_DATA_1_WIDTH=32'b00000000000000000000000000100000
	L_DATA_1_WIDTH=32'b00000000000000000000000000100000
	N_DATA_WIDTH_2_WIDE=32'b00000000000000000000000000100000
	L_DATA_WIDTH_2_WIDE=32'b00000000000000000000000000100000
	N_DATA_WIDTH_4_WIDE=32'b00000000000000000000000000100000
	L_DATA_WIDTH_4_WIDE=32'b00000000000000000000000000100000
	N_DATA_WIDTH_8_WIDE=32'b00000000000000000000000000100000
	L_DATA_WIDTH_8_WIDE=32'b00000000000000000000000000100000
	N_DATA_WIDTH_16_WIDE=32'b00000000000000000000000000100000
	L_DATA_WIDTH_16_WIDE=32'b00000000000000000000000000100000
	N_DATA_WIDTH_32_WIDE=32'b00000000000000000000000000100000
	L_DATA_WIDTH_32_WIDE=32'b00000000000000000000000000100000
	N_BYTE_DATA_1_WIDTH=32'b00000000000000000000000000100000
	L_BYTE_DATA_1_WIDTH=32'b00000000000000000000000000100000
	N_BYTE_DATA_WIDTH_2_WIDE=32'b00000000000000000000000000100000
	L_BYTE_DATA_WIDTH_2_WIDE=32'b00000000000000000000000000100000
	N_BYTE_DATA_WIDTH_4_WIDE=32'b00000000000000000000000000100000
	L_BYTE_DATA_WIDTH_4_WIDE=32'b00000000000000000000000000100000
	WIDTH_RATIO=32'b00000000000000000000000000000010
	N_DRM_DATA_WIDTH_A=32'b00000000000000000000000000100000
	L_DRM_DATA_WIDTH_A=32'b00000000000000000000000000100000
	N_DRM_DATA_WIDTH_B=32'b00000000000000000000000000010000
	L_DRM_DATA_WIDTH_B=32'b00000000000000000000000000010000
	N_BYTE_DATA_WIDTH_A=32'b00000000000000000000000000100000
	L_BYTE_DATA_WIDTH_A=32'b00000000000000000000000000100000
	N_BYTE_DATA_WIDTH_B=32'b00000000000000000000000000010000
	L_BYTE_DATA_WIDTH_B=32'b00000000000000000000000000010000
	DRM_DATA_WIDTH_A=32'b00000000000000000000000000100000
	DRM_DATA_WIDTH_B=32'b00000000000000000000000000010000
	DATA_LOOP_NUM=32'b00000000000000000000000000000010
	Q_DRM_DATA_WIDTH_B=32'b00000000000000000000000000010000
	Q_DRM_DATA_WIDTH_A=32'b00000000000000000000000000010000
	D_DRM_DATA_WIDTH_A=32'b00000000000000000000000000010000
	D_DRM_DATA_WIDTH_B=32'b00000000000000000000000000010000
	DRM_ADDR_WIDTH_A=32'b00000000000000000000000000001001
	DRM_ADDR_WIDTH_B=32'b00000000000000000000000000001010
	ADDR_WIDTH_A=32'b00000000000000000000000000001001
	CS_ADDR_WIDTH_A=32'b00000000000000000000000000000000
	ADDR_WIDTH_B=32'b00000000000000000000000000001010
	CS_ADDR_WIDTH_B=32'b00000000000000000000000000000000
	ADDR_LOOP_NUM_A=32'b00000000000000000000000000000001
	ADDR_LOOP_NUM_B=32'b00000000000000000000000000000001
	CAS_DATA_WIDTH_A=32'b00000000000000000000000001000000
	CAS_DATA_WIDTH_B=32'b00000000000000000000000000100000
	Q_CAS_DATA_WIDTH_A=32'b00000000000000000000000000100000
	Q_CAS_DATA_WIDTH_B=32'b00000000000000000000000000100000
	D_CAS_DATA_WIDTH_A=32'b00000000000000000000000000100000
	D_CAS_DATA_WIDTH_B=32'b00000000000000000000000000100000
	WR_BYTE_WIDTH_A=32'b00000000000000000000000000001000
	WR_BYTE_WIDTH_B=32'b00000000000000000000000000001000
	MASK_NUM_A=32'b00000000000000000000000000000100
	MASK_NUM_B=32'b00000000000000000000000000001000
	c_RST_TYPE=144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010011010110010100111001000011
	CS_ADDR_A_3_LSB=32'b00000000000000000000000000000111
	CS_ADDR_A_4_LSB=32'b00000000000000000000000000000111
	MODE_RATIO=32'b00000000000000000000000000000010
	CS_ADDR_B_3_LSB=32'b00000000000000000000000000001000
	CS_ADDR_B_4_LSB=32'b00000000000000000000000000001000
	RD_ADDR_SEL_LSB=32'b00000000000000000000000000001001
   Generated name = ipml_sdpram_v1_3_afifo_64i_32o_128_Z5
@W:CG390 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(450) | Repeat multiplier in concatenation evaluates to 0
@W:CG390 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(454) | Repeat multiplier in concatenation evaluates to 0
@W:CG390 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(454) | Repeat multiplier in concatenation evaluates to 0
@W:CG532 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(287) | Within an initial block, only Verilog force statements and memory $readmemh/$readmemb initialization statements are recognized, and all other content is ignored.
@W:CG133 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(1064) | Object cs_rd is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(1078) | Object gen_i_rd is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(1078) | Object gen_j_rd is declared but not assigned. Either assign a value or remove the declaration.
Running optimization stage 1 on ipml_sdpram_v1_3_afifo_64i_32o_128_Z5 .......
@W:CL169 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(1053) | Pruning unused register addr_bus_rd_invt[0:1]. Make sure that there are no unused intermediate registers.
@W:CL169 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(1044) | Pruning unused register addr_bus_rd_oce[0:1]. Make sure that there are no unused intermediate registers.
@W:CL169 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(1035) | Pruning unused register addr_bus_rd_ce[0:1]. Make sure that there are no unused intermediate registers.
@W:CL169 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(639) | Pruning unused register rd_addr_bsel_rd_invt[3:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(625) | Pruning unused register rd_addr_bsel_rd_oce[3:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(604) | Pruning unused register rd_addr_bsel_rd_ce[3:0]. Make sure that there are no unused intermediate registers.
@N:CG364 : ipml_fifo_ctrl_v1_3.v(21) | Synthesizing module ipml_fifo_ctrl_v1_3 in library work.

	c_WR_DEPTH_WIDTH=32'b00000000000000000000000000001000
	c_RD_DEPTH_WIDTH=32'b00000000000000000000000000001001
	c_FIFO_TYPE=32'b01000001010100110101100101001110
	c_ALMOST_FULL_NUM=32'b00000000000000000000000011111100
	c_ALMOST_EMPTY_NUM=32'b00000000000000000000000000000100
   Generated name = ipml_fifo_ctrl_v1_3_8s_9s_ASYN_252s_4s
@W:CG133 : ipml_fifo_ctrl_v1_3.v(73) | Object asyn_almost_full is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : ipml_fifo_ctrl_v1_3.v(75) | Object asyn_almost_empty is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : ipml_fifo_ctrl_v1_3.v(76) | Object syn_wfull is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : ipml_fifo_ctrl_v1_3.v(77) | Object syn_almost_full is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : ipml_fifo_ctrl_v1_3.v(78) | Object syn_rempty is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : ipml_fifo_ctrl_v1_3.v(79) | Object syn_almost_empty is declared but not assigned. Either assign a value or remove the declaration.
Running optimization stage 1 on ipml_fifo_ctrl_v1_3_8s_9s_ASYN_252s_4s .......
@W:CL169 : ipml_fifo_ctrl_v1_3.v(154) | Pruning unused register ASYN_CTRL.raddr_msb. Make sure that there are no unused intermediate registers.
@W:CL169 : ipml_fifo_ctrl_v1_3.v(106) | Pruning unused register ASYN_CTRL.waddr_msb. Make sure that there are no unused intermediate registers.
@W:CL265 : ipml_fifo_ctrl_v1_3.v(154) | Removing unused bit 0 of ASYN_CTRL.rptr[9:0]. Either assign all bits or reduce the width of the signal.
@W:CL265 : ipml_fifo_ctrl_v1_3.v(123) | Removing unused bit 0 of ASYN_CTRL.wrptr1[9:0]. Either assign all bits or reduce the width of the signal.
@W:CL265 : ipml_fifo_ctrl_v1_3.v(123) | Removing unused bit 0 of ASYN_CTRL.wrptr2[9:0]. Either assign all bits or reduce the width of the signal.
@N:CG364 : ipml_fifo_v1_3_afifo_64i_32o_128.v(25) | Synthesizing module ipml_fifo_v1_3_afifo_64i_32o_128 in library work.

	c_SIM_DEVICE=48'b010100000100011101001100001100100011001001000111
	c_WR_DEPTH_WIDTH=32'b00000000000000000000000000001000
	c_WR_DATA_WIDTH=32'b00000000000000000000000001000000
	c_RD_DEPTH_WIDTH=32'b00000000000000000000000000001001
	c_RD_DATA_WIDTH=32'b00000000000000000000000000100000
	c_OUTPUT_REG=32'b00000000000000000000000000000000
	c_RD_OCE_EN=32'b00000000000000000000000000000000
	c_RESET_TYPE=192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010011010110010100111001000011010111110101001001000101010100110100010101010100
	c_POWER_OPT=32'b00000000000000000000000000000000
	c_RD_CLK_OR_POL_INV=32'b00000000000000000000000000000000
	c_WR_BYTE_EN=32'b00000000000000000000000000000000
	c_BE_WIDTH=32'b00000000000000000000000000000100
	c_FIFO_TYPE=32'b01000001010100110101100101001110
	c_ALMOST_FULL_NUM=32'b00000000000000000000000011111100
	c_ALMOST_EMPTY_NUM=32'b00000000000000000000000000000100
   Generated name = ipml_fifo_v1_3_afifo_64i_32o_128_Z6
Running optimization stage 1 on ipml_fifo_v1_3_afifo_64i_32o_128_Z6 .......
@N:CG364 : afifo_64i_32o_128.v(18) | Synthesizing module afifo_64i_32o_128 in library work.
@W:CG390 : afifo_64i_32o_128.v(142) | Repeat multiplier in concatenation evaluates to 0
@W:CG360 : afifo_64i_32o_128.v(120) | Removing wire wr_byte_en, as there is no assignment to it.
@W:CG360 : afifo_64i_32o_128.v(128) | Removing wire rd_oce, as there is no assignment to it.
Running optimization stage 1 on afifo_64i_32o_128 .......
@N:CG364 : frame_fifo_read.v(31) | Synthesizing module frame_fifo_read in library work.

	MEM_DATA_BITS=32'b00000000000000000000000001000000
	ADDR_BITS=32'b00000000000000000000000000011001
	BUSRT_BITS=32'b00000000000000000000000000001010
	FIFO_DEPTH=32'b00000000000000000000000010000000
	BURST_SIZE=32'b00000000000000000000000001000000
	ONE=256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001
	ZERO=256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
	S_IDLE=32'b00000000000000000000000000000000
	S_ACK=32'b00000000000000000000000000000001
	S_CHECK_FIFO=32'b00000000000000000000000000000010
	S_READ_BURST=32'b00000000000000000000000000000011
	S_READ_BURST_END=32'b00000000000000000000000000000100
	S_END=32'b00000000000000000000000000000101
   Generated name = frame_fifo_read_Z7
Running optimization stage 1 on frame_fifo_read_Z7 .......
@W:CL190 : frame_fifo_read.v(107) | Optimizing register bit rd_burst_len[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : frame_fifo_read.v(107) | Optimizing register bit rd_burst_len[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : frame_fifo_read.v(107) | Optimizing register bit rd_burst_len[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : frame_fifo_read.v(107) | Optimizing register bit rd_burst_len[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : frame_fifo_read.v(107) | Optimizing register bit rd_burst_len[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : frame_fifo_read.v(107) | Optimizing register bit rd_burst_len[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : frame_fifo_read.v(107) | Optimizing register bit rd_burst_len[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : frame_fifo_read.v(107) | Optimizing register bit rd_burst_len[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : frame_fifo_read.v(107) | Optimizing register bit rd_burst_len[9] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL279 : frame_fifo_read.v(107) | Pruning register bits 9 to 7 of rd_burst_len[9:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL279 : frame_fifo_read.v(107) | Pruning register bits 5 to 0 of rd_burst_len[9:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@N:CG364 : frame_read_write.v(31) | Synthesizing module frame_read_write in library work.

	MEM_DATA_BITS=32'b00000000000000000000000001000000
	READ_DATA_BITS=32'b00000000000000000000000000100000
	WRITE_DATA_BITS=32'b00000000000000000000000000100000
	ADDR_BITS=32'b00000000000000000000000000011001
	BUSRT_BITS=32'b00000000000000000000000000001010
	BURST_SIZE=32'b00000000000000000000000001000000
   Generated name = frame_read_write_64s_32s_32s_25s_10s_64s
Running optimization stage 1 on frame_read_write_64s_32s_32s_25s_10s_64s .......
@N:CG364 : pll_50_400.v(5) | Synthesizing module pll_50_400 in library work.
@W:CG781 : pll_50_400.v(259) | Input DUTYF on instance u_pll_e1 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : pll_50_400.v(265) | Input PHASEF on instance u_pll_e1 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : pll_50_400.v(271) | Input CPHASEF on instance u_pll_e1 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG360 : pll_50_400.v(120) | Removing wire clkfb, as there is no assignment to it.
@W:CG360 : pll_50_400.v(123) | Removing wire pfden, as there is no assignment to it.
@W:CG360 : pll_50_400.v(125) | Removing wire clkout0_2pad_gate, as there is no assignment to it.
@W:CG360 : pll_50_400.v(126) | Removing wire clkout1_gate, as there is no assignment to it.
@W:CG360 : pll_50_400.v(127) | Removing wire clkout2_gate, as there is no assignment to it.
@W:CG360 : pll_50_400.v(128) | Removing wire clkout3_gate, as there is no assignment to it.
@W:CG360 : pll_50_400.v(129) | Removing wire clkout4_gate, as there is no assignment to it.
@W:CG360 : pll_50_400.v(130) | Removing wire clkout5_gate, as there is no assignment to it.
@W:CG360 : pll_50_400.v(131) | Removing wire dyn_idiv, as there is no assignment to it.
@W:CG360 : pll_50_400.v(132) | Removing wire dyn_odiv0, as there is no assignment to it.
@W:CG360 : pll_50_400.v(133) | Removing wire dyn_odiv1, as there is no assignment to it.
@W:CG360 : pll_50_400.v(134) | Removing wire dyn_odiv2, as there is no assignment to it.
@W:CG360 : pll_50_400.v(135) | Removing wire dyn_odiv3, as there is no assignment to it.
@W:CG360 : pll_50_400.v(136) | Removing wire dyn_odiv4, as there is no assignment to it.
@W:CG360 : pll_50_400.v(137) | Removing wire dyn_fdiv, as there is no assignment to it.
@W:CG360 : pll_50_400.v(138) | Removing wire dyn_duty0, as there is no assignment to it.
@W:CG360 : pll_50_400.v(139) | Removing wire dyn_duty1, as there is no assignment to it.
@W:CG360 : pll_50_400.v(140) | Removing wire dyn_duty2, as there is no assignment to it.
@W:CG360 : pll_50_400.v(141) | Removing wire dyn_duty3, as there is no assignment to it.
@W:CG360 : pll_50_400.v(142) | Removing wire dyn_duty4, as there is no assignment to it.
@W:CG360 : pll_50_400.v(143) | Removing wire dyn_phase0, as there is no assignment to it.
@W:CG360 : pll_50_400.v(144) | Removing wire dyn_phase1, as there is no assignment to it.
@W:CG360 : pll_50_400.v(145) | Removing wire dyn_phase2, as there is no assignment to it.
@W:CG360 : pll_50_400.v(146) | Removing wire dyn_phase3, as there is no assignment to it.
@W:CG360 : pll_50_400.v(147) | Removing wire dyn_phase4, as there is no assignment to it.
Running optimization stage 1 on pll_50_400 .......
@N:CG364 : ipsl_ddrphy_reset_ctrl.v(1) | Synthesizing module ipsl_ddrphy_reset_ctrl in library work.
Running optimization stage 1 on ipsl_ddrphy_reset_ctrl .......
@N:CG364 : ipsl_ddrphy_training_ctrl.v(1) | Synthesizing module ipsl_ddrphy_training_ctrl in library work.
@N:CG179 : ipsl_ddrphy_training_ctrl.v(34) | Removing redundant assignment.
Running optimization stage 1 on ipsl_ddrphy_training_ctrl .......
@N:CG364 : ipsl_ddrphy_dll_update_ctrl.v(1) | Synthesizing module ipsl_ddrphy_dll_update_ctrl in library work.
Running optimization stage 1 on ipsl_ddrphy_dll_update_ctrl .......
@N:CG364 : ipsl_ddrphy_update_ctrl.v(1) | Synthesizing module ipsl_ddrphy_update_ctrl in library work.

	DATA_WIDTH=40'b0011000100110110010000100100100101010100
	DLL_OFFSET=32'b00000000000000000000000000000010
	IDLE=32'b00000000000000000000000000000000
	REQ=32'b00000000000000000000000000000001
	UPDATE=32'b00000000000000000000000000000010
	WAIT_END=32'b00000000000000000000000000000011
	DQSH_REQ_EN=1'b1
   Generated name = ipsl_ddrphy_update_ctrl_16BIT_2s_0s_1s_2s_3s_1
@W:CG133 : ipsl_ddrphy_update_ctrl.v(44) | Object dqsi_dpi_mon_req is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : ipsl_ddrphy_update_ctrl.v(45) | Object dly_loop_mon_req is declared but not assigned. Either assign a value or remove the declaration.
Running optimization stage 1 on ipsl_ddrphy_update_ctrl_16BIT_2s_0s_1s_2s_3s_1 .......
@N:CG364 : logos.v(1316) | Synthesizing module GTP_DLL in library work.
Running optimization stage 1 on GTP_DLL .......
@N:CG364 : logos.v(696) | Synthesizing module GTP_DDRPHY in library work.
Running optimization stage 1 on GTP_DDRPHY .......
@N:CG364 : logos.v(1737) | Synthesizing module GTP_IOCLKBUF in library work.
Running optimization stage 1 on GTP_IOCLKBUF .......
@N:CG364 : logos.v(1766) | Synthesizing module GTP_IOCLKDIV in library work.
Running optimization stage 1 on GTP_IOCLKDIV .......
@N:CG364 : logos.v(195) | Synthesizing module GTP_DDC_E1 in library work.
Running optimization stage 1 on GTP_DDC_E1 .......
@N:CG364 : logos.v(1779) | Synthesizing module GTP_IODELAY in library work.
Running optimization stage 1 on GTP_IODELAY .......
@N:CG364 : logos.v(1819) | Synthesizing module GTP_ISERDES in library work.
Running optimization stage 1 on GTP_ISERDES .......
@N:CG364 : logos.v(1612) | Synthesizing module GTP_INBUFG in library work.
Running optimization stage 1 on GTP_INBUFG .......
@N:CG364 : logos.v(2175) | Synthesizing module GTP_OUTBUF in library work.
Running optimization stage 1 on GTP_OUTBUF .......
@N:CG364 : logos.v(1645) | Synthesizing module GTP_IOBUF in library work.
Running optimization stage 1 on GTP_IOBUF .......
@N:CG364 : logos.v(2226) | Synthesizing module GTP_OUTBUFTCO in library work.
Running optimization stage 1 on GTP_OUTBUFTCO .......
@N:CG364 : ipsl_phy_io.v(27) | Synthesizing module ipsl_phy_io in library work.

	DQS_GATE_LOOP=32'b01010100010100100101010101000101
	R_EXTEND=40'b0100011001000001010011000101001101000101
	CORE_CLK_SEL=1'b0
	TEST_PATTERN2=32'b01111111011111110111111101111111
	TEST_PATTERN3=32'b01010000101111000101000010111100
	T200US=32'b00000000000000001001110001000000
	MR0_DDR3=16'b0001010100100000
	MR1_DDR3=16'b0000000000010100
	MR2_DDR3=16'b0000000000000000
	MR3_DDR3=16'b0000000000000000
	MR_DDR2=16'b0000101101010011
	EMR1_DDR2=16'b0000000000011100
	EMR2_DDR2=16'b0000000000000000
	EMR3_DDR2=16'b0000000000000000
	MR_LPDDR=16'b0000000000110011
	EMR_LPDDR=16'b0000000000000000
	TMRD=32'b00000000000000000000000000000010
	TMOD=32'b00000000000000000000000000000110
	TZQINIT=32'b00000000000000000000000100000000
	TXPR=32'b00000000000000000000000000111110
	TRP=32'b00000000000000000000000000000011
	TRFC=32'b00000000000000000000000000111100
	WL_EN=32'b01010100010100100101010101000101
	DDR_TYPE=32'b01000100010001000101001000110011
	DATA_WIDTH=40'b0011000100110110010000100100100101010100
	DQS_GATE_MODE=2'b01
	WRDATA_PATH_ADJ=40'b0100011001000001010011000101001101000101
	CTRL_PATH_ADJ=40'b0100011001000001010011000101001101000101
	WL_MAX_STEP=8'b11111111
	WL_MAX_CHECK=5'b11111
	MAN_WRLVL_DQS_L=40'b0100011001000001010011000101001101000101
	MAN_WRLVL_DQS_H=40'b0100011001000001010011000101001101000101
	WL_CTRL_L=3'b001
	WL_CTRL_H=3'b001
	INIT_READ_CLK_CTRL=2'b11
	INIT_READ_CLK_CTRL_H=2'b11
	INIT_SLIP_STEP=4'b0111
	INIT_SLIP_STEP_H=4'b0111
	FORCE_READ_CLK_CTRL_L=40'b0100011001000001010011000101001101000101
	FORCE_READ_CLK_CTRL_H=40'b0100011001000001010011000101001101000101
	STOP_WITH_ERROR=40'b0100011001000001010011000101001101000101
	DQGT_DEBUG=1'b0
	WRITE_DEBUG=1'b0
	RDEL_ADJ_MAX_RANG=5'b11111
	MIN_DQSI_WIN=4'b0110
	INIT_SAMP_POSITION=8'b00000000
	INIT_SAMP_POSITION_H=8'b00000000
	FORCE_SAMP_POSITION_L=40'b0100011001000001010011000101001101000101
	FORCE_SAMP_POSITION_H=40'b0100011001000001010011000101001101000101
	RDEL_RD_CNT=19'b0000000000001000000
	T400NS=32'b00000000000000000000000001010000
	T_LPDDR=9'b000000000
	REF_CNT=8'b00110100
	APB_VLD=40'b0100011001000001010011000101001101000101
	TEST_PATTERN1=128'b00000000000000001111111111111111000000000000000011111111111111110000000000000000111111111111111100000000000000001111111111111111
	TRAIN_RST_TYPE=32'b01010100010100100101010101000101
	TXS=8'b00111110
	WL_SETTING=1'b0
	WCLK_DEL_SEL=1'b0
	INIT_WRLVL_STEP_L=8'b00000000
	INIT_WRLVL_STEP_H=8'b00000000
   Generated name = ipsl_phy_io_Z8
@N:CG364 : logos.v(1636) | Synthesizing module GTP_INV in library work.
Running optimization stage 1 on GTP_INV .......
@N:CG364 : logos.v(1661) | Synthesizing module GTP_IOBUFCO in library work.
Running optimization stage 1 on GTP_IOBUFCO .......
@W:CS263 : ipsl_phy_io.v(1147) | Port-width mismatch for port DQS_DRIFT. The port definition is 2 bits, but the actual port connection bit width is 1. Adjust either the definition or the instantiation of this port.
@W:CG781 : ipsl_phy_io.v(1199) | Input DQSI on instance dqs1_dut is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ipsl_phy_io.v(1200) | Input GATE_IN on instance dqs1_dut is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CS263 : ipsl_phy_io.v(1224) | Port-width mismatch for port DQS_DRIFT. The port definition is 2 bits, but the actual port connection bit width is 1. Adjust either the definition or the instantiation of this port.
@W:CG781 : ipsl_phy_io.v(1276) | Input DQSI on instance dqs3_dut is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ipsl_phy_io.v(1277) | Input GATE_IN on instance dqs3_dut is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ipsl_phy_io.v(1313) | Input DQSI on instance dqs4_dut is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ipsl_phy_io.v(1314) | Input GATE_IN on instance dqs4_dut is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG360 : ipsl_phy_io.v(100) | Removing wire PSLVERR, as there is no assignment to it.
@W:CG360 : ipsl_phy_io.v(174) | Removing wire DQS_DRIFT_L, as there is no assignment to it.
@W:CG360 : ipsl_phy_io.v(175) | Removing wire DQS_DRIFT_H, as there is no assignment to it.
@W:CG360 : ipsl_phy_io.v(330) | Removing wire loop_in_di, as there is no assignment to it.
@W:CG360 : ipsl_phy_io.v(331) | Removing wire loop_in_do, as there is no assignment to it.
@W:CG360 : ipsl_phy_io.v(332) | Removing wire loop_in_to, as there is no assignment to it.
@W:CG360 : ipsl_phy_io.v(333) | Removing wire loop_out_di, as there is no assignment to it.
@W:CG360 : ipsl_phy_io.v(334) | Removing wire loop_out_do, as there is no assignment to it.
@W:CG360 : ipsl_phy_io.v(335) | Removing wire loop_out_to, as there is no assignment to it.
@W:CG360 : ipsl_phy_io.v(371) | Removing wire loop_in_di_h, as there is no assignment to it.
@W:CG360 : ipsl_phy_io.v(372) | Removing wire loop_in_do_h, as there is no assignment to it.
@W:CG360 : ipsl_phy_io.v(373) | Removing wire loop_in_to_h, as there is no assignment to it.
@W:CG360 : ipsl_phy_io.v(374) | Removing wire loop_out_di_h, as there is no assignment to it.
@W:CG360 : ipsl_phy_io.v(375) | Removing wire loop_out_do_h, as there is no assignment to it.
@W:CG360 : ipsl_phy_io.v(376) | Removing wire loop_out_to_h, as there is no assignment to it.
@W:CG360 : ipsl_phy_io.v(384) | Removing wire resetn_do, as there is no assignment to it.
@W:CG360 : ipsl_phy_io.v(385) | Removing wire resetn_to, as there is no assignment to it.
Running optimization stage 1 on ipsl_phy_io_Z8 .......
@W:CL318 : ipsl_phy_io.v(100) | *Output PSLVERR has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : ipsl_phy_io.v(174) | *Output DQS_DRIFT_L has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : ipsl_phy_io.v(175) | *Output DQS_DRIFT_H has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL168 : ipsl_phy_io.v(1324) | Removing instance gtp_int_dut[54].inv_dut because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : ipsl_phy_io.v(1324) | Removing instance gtp_int_dut[53].inv_dut because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : ipsl_phy_io.v(1324) | Removing instance gtp_int_dut[50].inv_dut because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : ipsl_phy_io.v(1324) | Removing instance gtp_int_dut[39].inv_dut because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : ipsl_phy_io.v(1324) | Removing instance gtp_int_dut[38].inv_dut because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : ipsl_phy_io.v(1324) | Removing instance gtp_int_dut[30].inv_dut because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : ipsl_phy_io.v(1324) | Removing instance gtp_int_dut[26].inv_dut because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : ipsl_phy_io.v(1324) | Removing instance gtp_int_dut[16].inv_dut because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : ipsl_phy_io.v(1324) | Removing instance gtp_int_dut[15].inv_dut because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : ipsl_phy_io.v(1324) | Removing instance gtp_int_dut[14].inv_dut because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : ipsl_phy_io.v(1324) | Removing instance gtp_int_dut[13].inv_dut because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : ipsl_phy_io.v(1324) | Removing instance gtp_int_dut[8].inv_dut because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : ipsl_phy_io.v(1324) | Removing instance gtp_int_dut[1].inv_dut because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : ipsl_phy_io.v(1324) | Removing instance gtp_int_dut[0].inv_dut because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : ipsl_hmemc_phy_top.v(1) | Synthesizing module ipsl_hmemc_phy_top in library work.

	DQS_GATE_LOOP=32'b01010100010100100101010101000101
	R_EXTEND=40'b0100011001000001010011000101001101000101
	CORE_CLK_SEL=1'b0
	TEST_PATTERN2=32'b01111111011111110111111101111111
	TEST_PATTERN3=32'b01010000101111000101000010111100
	T200US=32'b00000000000000001001110001000000
	MR0_DDR3=16'b0001010100100000
	MR1_DDR3=16'b0000000000010100
	MR2_DDR3=16'b0000000000000000
	MR3_DDR3=16'b0000000000000000
	MR_DDR2=16'b0000101101010011
	EMR1_DDR2=16'b0000000000011100
	EMR2_DDR2=16'b0000000000000000
	EMR3_DDR2=16'b0000000000000000
	MR_LPDDR=16'b0000000000110011
	EMR_LPDDR=16'b0000000000000000
	PHY_TMRD=32'b00000000000000000000000000000010
	PHY_TMOD=32'b00000000000000000000000000000110
	PHY_TZQINIT=32'b00000000000000000000000100000000
	PHY_TXPR=32'b00000000000000000000000000111110
	PHY_TRP=32'b00000000000000000000000000000011
	PHY_TRFC=32'b00000000000000000000000000111100
	WL_EN=32'b01010100010100100101010101000101
	DDR_TYPE=32'b01000100010001000101001000110011
	DATA_WIDTH=40'b0011000100110110010000100100100101010100
	DQS_GATE_MODE=2'b01
	WRDATA_PATH_ADJ=40'b0100011001000001010011000101001101000101
	CTRL_PATH_ADJ=40'b0100011001000001010011000101001101000101
	WL_MAX_STEP=8'b11111111
	WL_MAX_CHECK=5'b11111
	MAN_WRLVL_DQS_L=40'b0100011001000001010011000101001101000101
	MAN_WRLVL_DQS_H=40'b0100011001000001010011000101001101000101
	WL_CTRL_L=3'b001
	WL_CTRL_H=3'b001
	INIT_READ_CLK_CTRL=2'b11
	INIT_READ_CLK_CTRL_H=2'b11
	INIT_SLIP_STEP=4'b0111
	INIT_SLIP_STEP_H=4'b0111
	FORCE_READ_CLK_CTRL_L=40'b0100011001000001010011000101001101000101
	FORCE_READ_CLK_CTRL_H=40'b0100011001000001010011000101001101000101
	STOP_WITH_ERROR=40'b0100011001000001010011000101001101000101
	DQGT_DEBUG=1'b0
	WRITE_DEBUG=1'b0
	RDEL_ADJ_MAX_RANG=5'b11111
	MIN_DQSI_WIN=4'b0110
	INIT_SAMP_POSITION=8'b00000000
	INIT_SAMP_POSITION_H=8'b00000000
	FORCE_SAMP_POSITION_L=40'b0100011001000001010011000101001101000101
	FORCE_SAMP_POSITION_H=40'b0100011001000001010011000101001101000101
	RDEL_RD_CNT=19'b0000000000001000000
	T400NS=32'b00000000000000000000000001010000
	T_LPDDR=9'b000000000
	REF_CNT=8'b00110100
	APB_VLD=40'b0100011001000001010011000101001101000101
	TEST_PATTERN1=128'b00000000000000001111111111111111000000000000000011111111111111110000000000000000111111111111111100000000000000001111111111111111
	TRAIN_RST_TYPE=32'b01010100010100100101010101000101
	PHY_TXS=8'b00111110
	WL_SETTING=1'b0
	WCLK_DEL_SEL=1'b0
	INIT_WRLVL_STEP_L=8'b00000000
	INIT_WRLVL_STEP_H=8'b00000000
	UPDATE_MASK=3'b000
   Generated name = ipsl_hmemc_phy_top_Z9
@W:CG781 : ipsl_hmemc_phy_top.v(294) | Input SRB_CORE_CLK on instance u_ipsl_phy_io is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG360 : ipsl_hmemc_phy_top.v(155) | Removing wire update_start, as there is no assignment to it.
Running optimization stage 1 on ipsl_hmemc_phy_top_Z9 .......
@N:CG364 : ipsl_ddrc_apb_reset.v(1) | Synthesizing module ipsl_ddrc_apb_reset in library work.

	TRFC_MIN=10'b0000111100
	TREFI=12'b000000110000
	T_MRD=6'b000010
	T_MOD=10'b0000000110
	DDR_TYPE=32'b01000100010001000101001000110011
	MR=16'b0001010100100000
	EMR=16'b0000000000010100
	EMR2=16'b0000000000000000
	EMR3=16'b0000000000000000
	WR2PRE=7'b0001010
	T_FAW=6'b001001
	T_RAS_MAX=7'b1111111
	T_RAS_MIN=6'b001000
	T_XP=5'b00010
	RD2PRE=6'b000100
	T_RC=7'b0001010
	WL=6'b000101
	RL=6'b000101
	RD2WR=6'b000100
	WR2RD=6'b000110
	T_RCD=5'b00001
	T_CCD=4'b0010
	T_RRD=4'b0010
	T_RP=5'b00011
	T_CKSRX=4'b0100
	T_CKSRE=4'b0110
	T_CKESR=6'b000011
	T_CKE=5'b00010
	DFI_T_RDDATA_EN=7'b0000100
	DFI_TPHY_WRLAT=6'b001001
	DATA_BUS_WIDTH=2'b00
	ADDRESS_MAPPING_SEL=32'b00000000000000000000000000000000
	MEM_ROW_ADDRESS=32'b00000000000000000000000000001111
	MEM_COLUMN_ADDRESS=32'b00000000000000000000000000001010
	MEM_BANK_ADDRESS=32'b00000000000000000000000000000011
	addrmap_bank_b0=8'b00001000
	addrmap_bank_b1=8'b00001000
	addrmap_bank_b2=8'b00001000
	addrmap_col_b2=8'b00000000
	addrmap_col_b3=8'b00000000
	addrmap_col_b4=8'b00000000
	addrmap_col_b5=8'b00000000
	addrmap_col_b6=8'b00000000
	addrmap_col_b7=8'b00000000
	addrmap_col_b8=8'b00000000
	addrmap_col_b9=8'b00000000
	addrmap_col_b10=8'b00011111
	addrmap_col_b11=8'b00011111
	addrmap_row_b0=8'b00000111
	addrmap_row_b1=8'b00000111
	addrmap_row_b2=8'b00000111
	addrmap_row_b3=8'b00000111
	addrmap_row_b4=8'b00000111
	addrmap_row_b5=8'b00000111
	addrmap_row_b6=8'b00000111
	addrmap_row_b7=8'b00000111
	addrmap_row_b8=8'b00000111
	addrmap_row_b9=8'b00000111
	addrmap_row_b10=8'b00000111
	addrmap_row_b11=8'b00000111
	addrmap_row_b12=8'b00000111
	addrmap_row_b13=8'b00000111
	addrmap_row_b14=8'b00000111
	addrmap_row_b15=8'b00011111
   Generated name = ipsl_ddrc_apb_reset_Z10
Running optimization stage 1 on ipsl_ddrc_apb_reset_Z10 .......
@N:CG364 : ipsl_ddrc_reset_ctrl.v(2) | Synthesizing module ipsl_ddrc_reset_ctrl in library work.

	TRFC_MIN=10'b0000111100
	TREFI=12'b000000110000
	T_MRD=6'b000010
	T_MOD=10'b0000000110
	DDR_TYPE=32'b01000100010001000101001000110011
	MR=16'b0001010100100000
	EMR=16'b0000000000010100
	EMR2=16'b0000000000000000
	EMR3=16'b0000000000000000
	WR2PRE=7'b0001010
	T_FAW=6'b001001
	T_RAS_MAX=7'b1111111
	T_RAS_MIN=6'b001000
	T_XP=5'b00010
	RD2PRE=6'b000100
	T_RC=7'b0001010
	WL=6'b000101
	RL=6'b000101
	RD2WR=6'b000100
	WR2RD=6'b000110
	T_RCD=5'b00001
	T_CCD=4'b0010
	T_RRD=4'b0010
	T_RP=5'b00011
	T_CKSRX=4'b0100
	T_CKSRE=4'b0110
	T_CKESR=6'b000011
	T_CKE=5'b00010
	DFI_T_RDDATA_EN=7'b0000100
	DFI_TPHY_WRLAT=6'b001001
	DATA_BUS_WIDTH=2'b00
	ADDRESS_MAPPING_SEL=32'b00000000000000000000000000000000
	MEM_ROW_ADDRESS=32'b00000000000000000000000000001111
	MEM_COLUMN_ADDRESS=32'b00000000000000000000000000001010
	MEM_BANK_ADDRESS=32'b00000000000000000000000000000011
   Generated name = ipsl_ddrc_reset_ctrl_Z11
@N:CG179 : ipsl_ddrc_reset_ctrl.v(93) | Removing redundant assignment.
@N:CG179 : ipsl_ddrc_reset_ctrl.v(122) | Removing redundant assignment.
Running optimization stage 1 on ipsl_ddrc_reset_ctrl_Z11 .......
@N:CG364 : logos.v(248) | Synthesizing module GTP_DDRC in library work.
Running optimization stage 1 on GTP_DDRC .......
@N:CG364 : ipsl_hmemc_ddrc_top.v(1) | Synthesizing module ipsl_hmemc_ddrc_top in library work.

	TRFC_MIN=10'b0000111100
	TREFI=12'b000000110000
	T_MRD=6'b000010
	T_MOD=10'b0000000110
	DDR_TYPE=32'b01000100010001000101001000110011
	MR=16'b0001010100100000
	EMR=16'b0000000000010100
	EMR2=16'b0000000000000000
	EMR3=16'b0000000000000000
	WR2PRE=7'b0001010
	T_FAW=6'b001001
	T_RAS_MAX=7'b1111111
	T_RAS_MIN=6'b001000
	T_XP=5'b00010
	RD2PRE=6'b000100
	T_RC=7'b0001010
	WL=6'b000101
	RL=6'b000101
	RD2WR=6'b000100
	WR2RD=6'b000110
	T_RCD=5'b00001
	T_CCD=4'b0010
	T_RRD=4'b0010
	T_RP=5'b00011
	T_CKSRX=4'b0100
	T_CKSRE=4'b0110
	T_CKESR=6'b000011
	T_CKE=5'b00010
	DFI_T_RDDATA_EN=7'b0000100
	DFI_TPHY_WRLAT=6'b001001
	DATA_BUS_WIDTH=2'b00
	ADDRESS_MAPPING_SEL=32'b00000000000000000000000000000000
	MEM_ROW_ADDRESS=32'b00000000000000000000000000001111
	MEM_COLUMN_ADDRESS=32'b00000000000000000000000000001010
	MEM_BANK_ADDRESS=32'b00000000000000000000000000000011
   Generated name = ipsl_hmemc_ddrc_top_Z12
Running optimization stage 1 on ipsl_hmemc_ddrc_top_Z12 .......
@N:CG364 : ddr3.v(10) | Synthesizing module ddr3 in library work.
@W:CG781 : ddr3.v(596) | Input aclk_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(597) | Input awid_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(598) | Input awaddr_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(599) | Input awlen_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(600) | Input awsize_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(601) | Input awburst_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(602) | Input awlock_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(603) | Input awvalid_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(605) | Input awurgent_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(606) | Input awpoison_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(607) | Input wdata_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(608) | Input wstrb_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(609) | Input wlast_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(610) | Input wvalid_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(615) | Input bready_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(616) | Input arid_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(617) | Input araddr_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(618) | Input arlen_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(619) | Input arsize_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(620) | Input arburst_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(621) | Input arlock_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(622) | Input arvalid_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(624) | Input arurgent_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(625) | Input arpoison_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(631) | Input rready_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(638) | Input csysreq_0 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(690) | Input aclk_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(691) | Input awid_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(692) | Input awaddr_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(693) | Input awlen_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(694) | Input awsize_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(695) | Input awburst_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(696) | Input awlock_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(697) | Input awvalid_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(699) | Input awurgent_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(700) | Input awpoison_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(701) | Input wdata_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(702) | Input wstrb_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(703) | Input wlast_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(704) | Input wvalid_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(709) | Input bready_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(710) | Input arid_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(711) | Input araddr_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(712) | Input arlen_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(713) | Input arsize_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(714) | Input arburst_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(715) | Input arlock_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(716) | Input arvalid_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(718) | Input arurgent_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(719) | Input arpoison_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(725) | Input rready_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(733) | Input csysreq_2 on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(783) | Input paddr on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(784) | Input pwdata on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(785) | Input pwrite on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(786) | Input penable on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : ddr3.v(788) | Input psel on instance u_ipsl_hmemc_ddrc_top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
Running optimization stage 1 on ddr3 .......
@N:CG364 : aq_axi_master.v(39) | Synthesizing module aq_axi_master in library work.
Running optimization stage 1 on aq_axi_master .......
@W:CL169 : aq_axi_master.v(170) | Pruning unused register reg_w_stb[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : aq_axi_master.v(170) | Pruning unused register reg_wr_status[1:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : aq_axi_master.v(170) | Pruning unused register reg_w_count[3:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : aq_axi_master.v(170) | Pruning unused register reg_r_count[3:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : aq_axi_master.v(170) | Pruning unused register wr_chkdata[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : aq_axi_master.v(170) | Pruning unused register rd_chkdata[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : aq_axi_master.v(170) | Pruning unused register resp[1:0]. Make sure that there are no unused intermediate registers.
@W:CL271 : aq_axi_master.v(342) | Pruning unused bits 2 to 0 of reg_rd_len[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : aq_axi_master.v(170) | Pruning unused bits 2 to 0 of reg_wr_len[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@A:CL282 : aq_axi_master.v(342) | Feedback mux created for signal reg_r_last. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@N:CG364 : ipsl_hmemc_top_test.v(5) | Synthesizing module ipsl_hmemc_top_test in library work.
@W:CS263 : ipsl_hmemc_top_test.v(280) | Port-width mismatch for port ddrc_rst. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
@W:CS263 : ipsl_hmemc_top_test.v(282) | Port-width mismatch for port areset_1. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
@W:CS263 : ipsl_hmemc_top_test.v(284) | Port-width mismatch for port awid_1. The port definition is 8 bits, but the actual port connection bit width is 4. Adjust either the definition or the instantiation of this port.
@W:CS263 : ipsl_hmemc_top_test.v(285) | Port-width mismatch for port awaddr_1. The port definition is 32 bits, but the actual port connection bit width is 64. Adjust either the definition or the instantiation of this port.
@W:CS263 : ipsl_hmemc_top_test.v(305) | Port-width mismatch for port arid_1. The port definition is 8 bits, but the actual port connection bit width is 4. Adjust either the definition or the instantiation of this port.
@W:CS263 : ipsl_hmemc_top_test.v(306) | Port-width mismatch for port araddr_1. The port definition is 32 bits, but the actual port connection bit width is 64. Adjust either the definition or the instantiation of this port.
@W:CS263 : ipsl_hmemc_top_test.v(310) | Port-width mismatch for port arlock_1. The port definition is 1 bits, but the actual port connection bit width is 2. Adjust either the definition or the instantiation of this port.
@W:CS263 : ipsl_hmemc_top_test.v(301) | Port-width mismatch for port bid_1. The port definition is 8 bits, but the actual port connection bit width is 4. Adjust either the definition or the instantiation of this port.
@W:CS263 : ipsl_hmemc_top_test.v(315) | Port-width mismatch for port rid_1. The port definition is 8 bits, but the actual port connection bit width is 4. Adjust either the definition or the instantiation of this port.
@W:CS263 : ipsl_hmemc_top_test.v(375) | Port-width mismatch for port M_AXI_BID. The port definition is 1 bits, but the actual port connection bit width is 4. Adjust either the definition or the instantiation of this port.
@W:CS263 : ipsl_hmemc_top_test.v(392) | Port-width mismatch for port M_AXI_RID. The port definition is 1 bits, but the actual port connection bit width is 4. Adjust either the definition or the instantiation of this port.
@W:CS263 : ipsl_hmemc_top_test.v(401) | Port-width mismatch for port WR_ADRS. The port definition is 32 bits, but the actual port connection bit width is 28. Adjust either the definition or the instantiation of this port.
@W:CS263 : ipsl_hmemc_top_test.v(402) | Port-width mismatch for port WR_LEN. The port definition is 32 bits, but the actual port connection bit width is 13. Adjust either the definition or the instantiation of this port.
@W:CS263 : ipsl_hmemc_top_test.v(410) | Port-width mismatch for port RD_ADRS. The port definition is 32 bits, but the actual port connection bit width is 28. Adjust either the definition or the instantiation of this port.
@W:CS263 : ipsl_hmemc_top_test.v(411) | Port-width mismatch for port RD_LEN. The port definition is 32 bits, but the actual port connection bit width is 13. Adjust either the definition or the instantiation of this port.
@W:CS263 : ipsl_hmemc_top_test.v(357) | Port-width mismatch for port M_AXI_AWID. The port definition is 1 bits, but the actual port connection bit width is 4. Adjust either the definition or the instantiation of this port.
@W:CS263 : ipsl_hmemc_top_test.v(358) | Port-width mismatch for port M_AXI_AWADDR. The port definition is 32 bits, but the actual port connection bit width is 64. Adjust either the definition or the instantiation of this port.
@W:CS263 : ipsl_hmemc_top_test.v(380) | Port-width mismatch for port M_AXI_ARID. The port definition is 1 bits, but the actual port connection bit width is 4. Adjust either the definition or the instantiation of this port.
@W:CS263 : ipsl_hmemc_top_test.v(381) | Port-width mismatch for port M_AXI_ARADDR. The port definition is 32 bits, but the actual port connection bit width is 64. Adjust either the definition or the instantiation of this port.
@W:CG133 : ipsl_hmemc_top_test.v(19) | Object clk_led is declared but not assigned. Either assign a value or remove the declaration.
@W:CG360 : ipsl_hmemc_top_test.v(42) | Removing wire err_flag, as there is no assignment to it.
@W:CG360 : ipsl_hmemc_top_test.v(97) | Removing wire ui_clk_sync_rst, as there is no assignment to it.
@W:CG360 : ipsl_hmemc_top_test.v(121) | Removing wire s00_axi_buser, as there is no assignment to it.
@W:CG360 : ipsl_hmemc_top_test.v(142) | Removing wire s00_axi_ruser, as there is no assignment to it.
@W:CG360 : ipsl_hmemc_top_test.v(145) | Removing wire pll_pclk, as there is no assignment to it.
Running optimization stage 1 on ipsl_hmemc_top_test .......
@W:CL318 : ipsl_hmemc_top_test.v(42) | *Output err_flag has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
Running optimization stage 2 on ipsl_hmemc_top_test .......
@A:CL153 : ipsl_hmemc_top_test.v(19) | *Unassigned bits of clk_led are referenced and tied to 0 -- simulation mismatch possible.
@W:CL156 : ipsl_hmemc_top_test.v(121) | *Input s00_axi_buser[0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : ipsl_hmemc_top_test.v(142) | *Input s00_axi_ruser[0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
Running optimization stage 2 on aq_axi_master .......
@N:CL201 : aq_axi_master.v(342) | Trying to extract state machine for register rd_state.
Extracted state machine for register rd_state
State machine has 6 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
@N:CL201 : aq_axi_master.v(170) | Trying to extract state machine for register wr_state.
Extracted state machine for register wr_state
State machine has 7 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
@N:CL159 : aq_axi_master.v(67) | Input M_AXI_BID is unused.
@N:CL159 : aq_axi_master.v(68) | Input M_AXI_BRESP is unused.
@N:CL159 : aq_axi_master.v(69) | Input M_AXI_BUSER is unused.
@N:CL159 : aq_axi_master.v(88) | Input M_AXI_RID is unused.
@N:CL159 : aq_axi_master.v(90) | Input M_AXI_RRESP is unused.
@N:CL159 : aq_axi_master.v(92) | Input M_AXI_RUSER is unused.
Running optimization stage 2 on ddr3 .......
Running optimization stage 2 on ipsl_hmemc_ddrc_top_Z12 .......
@N:CL159 : ipsl_hmemc_ddrc_top.v(215) | Input dfi_error is unused.
@N:CL159 : ipsl_hmemc_ddrc_top.v(216) | Input dfi_error_info is unused.
Running optimization stage 2 on GTP_DDRC .......
Running optimization stage 2 on ipsl_ddrc_reset_ctrl_Z11 .......
@W:CL190 : ipsl_ddrc_reset_ctrl.v(86) | Optimizing register bit rst_cnt[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : ipsl_ddrc_reset_ctrl.v(86) | Optimizing register bit rst_cnt[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : ipsl_ddrc_reset_ctrl.v(86) | Optimizing register bit rst_cnt[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : ipsl_ddrc_reset_ctrl.v(113) | Optimizing register bit ddrc_rst_cnt[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : ipsl_ddrc_reset_ctrl.v(113) | Optimizing register bit ddrc_rst_cnt[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : ipsl_ddrc_reset_ctrl.v(113) | Optimizing register bit ddrc_rst_cnt[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL279 : ipsl_ddrc_reset_ctrl.v(113) | Pruning register bits 7 to 5 of ddrc_rst_cnt[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL279 : ipsl_ddrc_reset_ctrl.v(86) | Pruning register bits 7 to 5 of rst_cnt[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
Running optimization stage 2 on ipsl_ddrc_apb_reset_Z10 .......
@W:CL246 : ipsl_ddrc_apb_reset.v(47) | Input port bits 31 to 2 of prdata[31:0] are unused. Assign logic for all port bits or change the input port size.
Running optimization stage 2 on ipsl_hmemc_phy_top_Z9 .......
Running optimization stage 2 on GTP_IOBUFCO .......
Running optimization stage 2 on GTP_INV .......
Running optimization stage 2 on ipsl_phy_io_Z8 .......
@N:CL159 : ipsl_phy_io.v(90) | Input SRB_CORE_CLK is unused.
Running optimization stage 2 on GTP_OUTBUFTCO .......
Running optimization stage 2 on GTP_IOBUF .......
Running optimization stage 2 on GTP_OUTBUF .......
Running optimization stage 2 on GTP_INBUFG .......
Running optimization stage 2 on GTP_ISERDES .......
Running optimization stage 2 on GTP_IODELAY .......
Running optimization stage 2 on GTP_DDC_E1 .......
Running optimization stage 2 on GTP_IOCLKDIV .......
Running optimization stage 2 on GTP_IOCLKBUF .......
Running optimization stage 2 on GTP_DDRPHY .......
Running optimization stage 2 on GTP_DLL .......
Running optimization stage 2 on ipsl_ddrphy_update_ctrl_16BIT_2s_0s_1s_2s_3s_1 .......
@N:CL201 : ipsl_ddrphy_update_ctrl.v(293) | Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 2 reachable states with original encodings of:
   00
   10
@W:CL247 : ipsl_ddrphy_update_ctrl.v(12) | Input port bit 2 of update_mask[2:0] is unused

Running optimization stage 2 on ipsl_ddrphy_dll_update_ctrl .......
@N:CL201 : ipsl_ddrphy_dll_update_ctrl.v(36) | Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
Running optimization stage 2 on ipsl_ddrphy_training_ctrl .......
Running optimization stage 2 on ipsl_ddrphy_reset_ctrl .......
@N:CL201 : ipsl_ddrphy_reset_ctrl.v(52) | Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 11 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
   1001
   1010
Running optimization stage 2 on pll_50_400 .......
@W:CL156 : pll_50_400.v(120) | *Input clkfb to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : pll_50_400.v(123) | *Input pfden to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : pll_50_400.v(125) | *Input clkout0_2pad_gate to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : pll_50_400.v(126) | *Input clkout1_gate to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : pll_50_400.v(127) | *Input clkout2_gate to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : pll_50_400.v(128) | *Input clkout3_gate to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : pll_50_400.v(129) | *Input clkout4_gate to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : pll_50_400.v(130) | *Input clkout5_gate to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : pll_50_400.v(131) | *Input dyn_idiv[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : pll_50_400.v(132) | *Input dyn_odiv0[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : pll_50_400.v(133) | *Input dyn_odiv1[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : pll_50_400.v(134) | *Input dyn_odiv2[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : pll_50_400.v(135) | *Input dyn_odiv3[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : pll_50_400.v(136) | *Input dyn_odiv4[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : pll_50_400.v(137) | *Input dyn_fdiv[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : pll_50_400.v(138) | *Input dyn_duty0[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : pll_50_400.v(139) | *Input dyn_duty1[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : pll_50_400.v(140) | *Input dyn_duty2[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : pll_50_400.v(141) | *Input dyn_duty3[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : pll_50_400.v(142) | *Input dyn_duty4[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : pll_50_400.v(143) | *Input dyn_phase0[2:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : pll_50_400.v(144) | *Input dyn_phase1[2:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : pll_50_400.v(145) | *Input dyn_phase2[2:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : pll_50_400.v(146) | *Input dyn_phase3[2:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : pll_50_400.v(147) | *Input dyn_phase4[2:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : pll_50_400.v(143) | *Input dyn_phase0[12:3] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : pll_50_400.v(144) | *Input dyn_phase1[12:3] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : pll_50_400.v(145) | *Input dyn_phase2[12:3] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : pll_50_400.v(146) | *Input dyn_phase3[12:3] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : pll_50_400.v(147) | *Input dyn_phase4[12:3] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
Running optimization stage 2 on frame_read_write_64s_32s_32s_25s_10s_64s .......
@W:CL156 : frame_read_write.v(112) | *Input rdusedw[15:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : frame_read_write.v(182) | *Input wrusedw[15:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
Running optimization stage 2 on frame_fifo_read_Z7 .......
@W:CL190 : frame_fifo_read.v(107) | Optimizing register bit read_cnt[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : frame_fifo_read.v(107) | Optimizing register bit read_cnt[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : frame_fifo_read.v(107) | Optimizing register bit read_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : frame_fifo_read.v(107) | Optimizing register bit read_cnt[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : frame_fifo_read.v(107) | Optimizing register bit read_cnt[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : frame_fifo_read.v(107) | Optimizing register bit read_cnt[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL279 : frame_fifo_read.v(107) | Pruning register bits 5 to 0 of read_cnt[24:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@N:CL201 : frame_fifo_read.v(107) | Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 6 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
Running optimization stage 2 on afifo_64i_32o_128 .......
Running optimization stage 2 on ipml_fifo_v1_3_afifo_64i_32o_128_Z6 .......
Running optimization stage 2 on ipml_fifo_ctrl_v1_3_8s_9s_ASYN_252s_4s .......
@W:CL260 : ipml_fifo_ctrl_v1_3.v(106) | Pruning register bit 8 of ASYN_CTRL.wptr[8:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : ipml_fifo_ctrl_v1_3.v(154) | Pruning register bit 9 of ASYN_CTRL.rptr[9:1]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
Running optimization stage 2 on ipml_sdpram_v1_3_afifo_64i_32o_128_Z5 .......
@W:CL138 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(533) | Removing register 'wr_cs_bit0_ff' because it is only assigned 0 or its original value.
@W:CL138 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(533) | Removing register 'wr_cs_bit1_bus_ff' because it is only assigned 0 or its original value.
@W:CL138 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(533) | Removing register 'wr_cs_bit2_bus_ff' because it is only assigned 0 or its original value.
@W:CL138 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(728) | Removing register 'rd_cs_bit0_ff' because it is only assigned 0 or its original value.
@W:CL138 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(728) | Removing register 'rd_cs_bit1_bus_ff' because it is only assigned 0 or its original value.
@W:CL138 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(728) | Removing register 'rd_cs_bit2_bus_ff' because it is only assigned 0 or its original value.
@W:CL156 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(748) | *Input DA_bus[17:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(749) | *Input DB_bus[17:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(748) | *Input DA_bus[35:18] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(749) | *Input DB_bus[35:18] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@N:CL159 : ipml_sdpram_v1_3_afifo_64i_32o_128.v(49) | Input wr_byte_en is unused.
Running optimization stage 2 on frame_fifo_write_Z4 .......
@W:CL190 : frame_fifo_write.v(106) | Optimizing register bit write_cnt[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : frame_fifo_write.v(106) | Optimizing register bit write_cnt[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : frame_fifo_write.v(106) | Optimizing register bit write_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : frame_fifo_write.v(106) | Optimizing register bit write_cnt[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : frame_fifo_write.v(106) | Optimizing register bit write_cnt[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : frame_fifo_write.v(106) | Optimizing register bit write_cnt[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL279 : frame_fifo_write.v(106) | Pruning register bits 5 to 0 of write_cnt[24:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@N:CL201 : frame_fifo_write.v(106) | Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 6 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
@N:CL159 : frame_fifo_write.v(45) | Input wr_burst_data_req is unused.
Running optimization stage 2 on afifo_32i_64o_256 .......
Running optimization stage 2 on ipml_fifo_v1_3_afifo_32i_64o_256_Z3 .......
Running optimization stage 2 on ipml_fifo_ctrl_v1_3_9s_8s_ASYN_508s_4s .......
@W:CL260 : ipml_fifo_ctrl_v1_3.v(154) | Pruning register bit 8 of ASYN_CTRL.rptr[8:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : ipml_fifo_ctrl_v1_3.v(106) | Pruning register bit 9 of ASYN_CTRL.wptr[9:1]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
Running optimization stage 2 on GTP_DRM18K .......
Running optimization stage 2 on ipml_sdpram_v1_3_afifo_32i_64o_256_Z2 .......
@W:CL138 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(533) | Removing register 'wr_cs_bit0_ff' because it is only assigned 0 or its original value.
@W:CL138 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(533) | Removing register 'wr_cs_bit1_bus_ff' because it is only assigned 0 or its original value.
@W:CL138 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(533) | Removing register 'wr_cs_bit2_bus_ff' because it is only assigned 0 or its original value.
@W:CL138 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(728) | Removing register 'rd_cs_bit0_ff' because it is only assigned 0 or its original value.
@W:CL138 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(728) | Removing register 'rd_cs_bit1_bus_ff' because it is only assigned 0 or its original value.
@W:CL138 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(728) | Removing register 'rd_cs_bit2_bus_ff' because it is only assigned 0 or its original value.
@W:CL156 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(748) | *Input DA_bus[17:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(749) | *Input DB_bus[17:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(748) | *Input DA_bus[35:18] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(749) | *Input DB_bus[35:18] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@N:CL159 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(49) | Input wr_byte_en is unused.
Running optimization stage 2 on video_timing_data_32s .......
Running optimization stage 2 on color_bar .......
@W:CL279 : color_bar.v(286) | Pruning register bits 7 to 1 of rgb_b_reg[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL279 : color_bar.v(286) | Pruning register bits 7 to 1 of rgb_g_reg[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL279 : color_bar.v(286) | Pruning register bits 7 to 1 of rgb_r_reg[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
Running optimization stage 2 on dvi_encoder .......
Running optimization stage 2 on serdes_4b_10to1 .......
@W:CL246 : serdes_4b_10to1.v(8) | Input port bits 1 to 0 of datain_2[9:0] are unused. Assign logic for all port bits or change the input port size.
@N:CL159 : serdes_4b_10to1.v(4) | Input clk is unused.
Running optimization stage 2 on GTP_OUTBUFT .......
Running optimization stage 2 on GTP_OSERDES .......
Running optimization stage 2 on encode .......
@W:CL260 : encode.v(108) | Pruning register bit 0 of n0q_m[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL190 : encode.v(151) | Optimizing register bit cnt[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL260 : encode.v(151) | Pruning register bit 0 of cnt[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
Running optimization stage 2 on sd_card_bmp .......
Running optimization stage 2 on sd_card_top .......
Running optimization stage 2 on spi_master .......
@N:CL201 : spi_master.v(64) | Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 6 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
Running optimization stage 2 on sd_card_cmd .......
@N:CL201 : sd_card_cmd.v(90) | Trying to extract state machine for register state.
@W:CL247 : sd_card_cmd.v(39) | Input port bit 46 of cmd[47:0] is unused

Running optimization stage 2 on sd_card_sec_read_write_Z1 .......
@N:CL201 : sd_card_sec_read_write.v(92) | Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 13 reachable states with original encodings of:
   00000
   00001
   00010
   00011
   00100
   00101
   00110
   00111
   01000
   01111
   10000
   10001
   10010
@W:CL260 : sd_card_sec_read_write.v(92) | Pruning register bit 42 of cmd[45:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL279 : sd_card_sec_read_write.v(92) | Pruning register bits 7 to 5 of cmd[45:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL260 : sd_card_sec_read_write.v(92) | Pruning register bit 2 of cmd[45:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
Running optimization stage 2 on bmp_read .......
@N:CL201 : bmp_read.v(202) | Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 5 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
Running optimization stage 2 on ax_debounce .......
Running optimization stage 2 on video_pll .......
@W:CL156 : video_pll.v(104) | *Input clkfb to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : video_pll.v(107) | *Input pfden to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : video_pll.v(108) | *Input clkout0_gate to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : video_pll.v(109) | *Input clkout0_2pad_gate to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : video_pll.v(110) | *Input clkout1_gate to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : video_pll.v(111) | *Input clkout2_gate to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : video_pll.v(112) | *Input clkout3_gate to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : video_pll.v(113) | *Input clkout4_gate to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : video_pll.v(114) | *Input clkout5_gate to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : video_pll.v(115) | *Input dyn_idiv[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : video_pll.v(116) | *Input dyn_odiv0[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : video_pll.v(117) | *Input dyn_odiv1[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : video_pll.v(118) | *Input dyn_odiv2[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : video_pll.v(119) | *Input dyn_odiv3[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : video_pll.v(120) | *Input dyn_odiv4[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : video_pll.v(121) | *Input dyn_fdiv[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : video_pll.v(122) | *Input dyn_duty0[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : video_pll.v(123) | *Input dyn_duty1[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : video_pll.v(124) | *Input dyn_duty2[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : video_pll.v(125) | *Input dyn_duty3[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : video_pll.v(126) | *Input dyn_duty4[9:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : video_pll.v(127) | *Input dyn_phase0[2:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : video_pll.v(128) | *Input dyn_phase1[2:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : video_pll.v(129) | *Input dyn_phase2[2:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : video_pll.v(130) | *Input dyn_phase3[2:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : video_pll.v(131) | *Input dyn_phase4[2:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : video_pll.v(127) | *Input dyn_phase0[12:3] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : video_pll.v(128) | *Input dyn_phase1[12:3] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : video_pll.v(129) | *Input dyn_phase2[12:3] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : video_pll.v(130) | *Input dyn_phase3[12:3] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : video_pll.v(131) | *Input dyn_phase4[12:3] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
Running optimization stage 2 on GTP_PLL_E1 .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
@L: D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\synthesize\synplify_impl\synwork\layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 92MB peak: 92MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue May  7 16:40:49 2019

###########################################################]
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03P-Beta2
Install: C:\pango\PDS_2019.1-patch2\syn
OS: Windows 6.1

Hostname: ALINX000007-PC

Implementation : synplify_impl
Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 007R, Built Feb 26 2019 11:45:06

@N: :  | Running in 64-bit mode 

Linker output is up to date. No re-linking necessary


At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 91MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue May  7 16:40:49 2019

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\synthesize\synplify_impl\synwork\synplify_comp.rt.csv

@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 18MB peak: 18MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue May  7 16:40:49 2019

###########################################################]

@A: :  | multi_srs_gen output is up to date. No run necessary. 
To force a re-synthesis, select [Resynthesize All] in menu [Run].
Click link to view previous log file.
Multi-srs Generator Report
Linked File:  synplify_multi_srs_gen.srr

Premap Report

# Tue May  7 16:40:49 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03P-Beta2
Install: C:\pango\PDS_2019.1-patch2\syn
OS: Windows 6.1

Hostname: ALINX000007-PC

Implementation : synplify_impl
Synopsys Generic Technology Pre-mapping, Version map2019q1p1, Build 1238R, Built Mar 15 2019 09:38:46


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

Reading constraint file: D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\ddr_324_left.fdc
@L: D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\synthesize\synplify_impl\synplify_scck.rpt 
Printing clock  summary report in "D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\synthesize\synplify_impl\synplify_scck.rpt" file 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 141MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 141MB)

Adding property PAP_IO_DIRECTION, value "Input", to port sys_clk
Adding property PAP_IO_LOC, value "B5", to port sys_clk
Adding property PAP_IO_VCCIO, value 3.3, to port sys_clk
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port sys_clk
Adding property PAP_IO_PULLUP, value "TRUE", to port sys_clk
Adding property PAP_IO_HYS_DRIVE_MODE, value "NOHYS", to port sys_clk
Adding property PAP_IO_DIRECTION, value "Input", to port rst_n
Adding property PAP_IO_LOC, value "U12", to port rst_n
Adding property PAP_IO_VCCIO, value 3.3, to port rst_n
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port rst_n
Adding property PAP_IO_PULLUP, value "TRUE", to port rst_n
Adding property PAP_IO_HYS_DRIVE_MODE, value "NOHYS", to port rst_n
Adding property PAP_IO_DIRECTION, value "Input", to port key
Adding property PAP_IO_LOC, value "V12", to port key
Adding property PAP_IO_VCCIO, value 3.3, to port key
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port key
Adding property PAP_IO_PULLUP, value "TRUE", to port key
Adding property PAP_IO_HYS_DRIVE_MODE, value "NOHYS", to port key
Adding property PAP_IO_DIRECTION, value "Output", to port led[0]
Adding property PAP_IO_LOC, value "U10", to port led[0]
Adding property PAP_IO_VCCIO, value 3.3, to port led[0]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[0]
Adding property PAP_IO_DRIVE, value 4, to port led[0]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[0]
Adding property PAP_IO_SLEW, value "FAST", to port led[0]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[0]
Adding property PAP_IO_DIRECTION, value "Output", to port led[1]
Adding property PAP_IO_LOC, value "V10", to port led[1]
Adding property PAP_IO_VCCIO, value 3.3, to port led[1]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[1]
Adding property PAP_IO_DRIVE, value 4, to port led[1]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[1]
Adding property PAP_IO_SLEW, value "FAST", to port led[1]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[1]
Adding property PAP_IO_DIRECTION, value "Output", to port led[2]
Adding property PAP_IO_LOC, value "U11", to port led[2]
Adding property PAP_IO_VCCIO, value 3.3, to port led[2]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[2]
Adding property PAP_IO_DRIVE, value 4, to port led[2]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[2]
Adding property PAP_IO_SLEW, value "FAST", to port led[2]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[2]
Adding property PAP_IO_DIRECTION, value "Output", to port led[3]
Adding property PAP_IO_LOC, value "V11", to port led[3]
Adding property PAP_IO_VCCIO, value 3.3, to port led[3]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[3]
Adding property PAP_IO_DRIVE, value 4, to port led[3]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[3]
Adding property PAP_IO_SLEW, value "FAST", to port led[3]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[3]
Adding property PAP_IO_DIRECTION, value "Output", to port sd_ncs
Adding property PAP_IO_LOC, value "V14", to port sd_ncs
Adding property PAP_IO_VCCIO, value 3.3, to port sd_ncs
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port sd_ncs
Adding property PAP_IO_DRIVE, value 4, to port sd_ncs
Adding property PAP_IO_PULLUP, value "TRUE", to port sd_ncs
Adding property PAP_IO_SLEW, value "FAST", to port sd_ncs
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port sd_ncs
Adding property PAP_IO_DIRECTION, value "Output", to port sd_dclk
Adding property PAP_IO_LOC, value "V13", to port sd_dclk
Adding property PAP_IO_VCCIO, value 3.3, to port sd_dclk
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port sd_dclk
Adding property PAP_IO_DRIVE, value 4, to port sd_dclk
Adding property PAP_IO_PULLUP, value "TRUE", to port sd_dclk
Adding property PAP_IO_SLEW, value "FAST", to port sd_dclk
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port sd_dclk
Adding property PAP_IO_DIRECTION, value "Output", to port sd_mosi
Adding property PAP_IO_LOC, value "U14", to port sd_mosi
Adding property PAP_IO_VCCIO, value 3.3, to port sd_mosi
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port sd_mosi
Adding property PAP_IO_DRIVE, value 4, to port sd_mosi
Adding property PAP_IO_PULLUP, value "TRUE", to port sd_mosi
Adding property PAP_IO_SLEW, value "FAST", to port sd_mosi
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port sd_mosi
Adding property PAP_IO_DIRECTION, value "Input", to port sd_miso
Adding property PAP_IO_LOC, value "U13", to port sd_miso
Adding property PAP_IO_VCCIO, value 3.3, to port sd_miso
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port sd_miso
Adding property PAP_IO_PULLUP, value "TRUE", to port sd_miso
Adding property PAP_IO_HYS_DRIVE_MODE, value "NOHYS", to port sd_miso
Adding property PAP_IO_DIRECTION, value "Output", to port clk_led
Adding property PAP_IO_LOC, value "A3", to port clk_led
Adding property PAP_IO_VCCIO, value 3.3, to port clk_led
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port clk_led
Adding property PAP_IO_DRIVE, value 4, to port clk_led
Adding property PAP_IO_PULLUP, value "TRUE", to port clk_led
Adding property PAP_IO_SLEW, value "FAST", to port clk_led
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port clk_led
Adding property PAP_IO_DIRECTION, value "Output", to port pll_lock
Adding property PAP_IO_LOC, value "B4", to port pll_lock
Adding property PAP_IO_VCCIO, value 3.3, to port pll_lock
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port pll_lock
Adding property PAP_IO_DRIVE, value 4, to port pll_lock
Adding property PAP_IO_PULLUP, value "TRUE", to port pll_lock
Adding property PAP_IO_SLEW, value "FAST", to port pll_lock
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port pll_lock
Adding property PAP_IO_DIRECTION, value "Output", to port ddr_init_done
Adding property PAP_IO_LOC, value "B2", to port ddr_init_done
Adding property PAP_IO_VCCIO, value 3.3, to port ddr_init_done
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port ddr_init_done
Adding property PAP_IO_DRIVE, value 4, to port ddr_init_done
Adding property PAP_IO_PULLUP, value "TRUE", to port ddr_init_done
Adding property PAP_IO_SLEW, value "FAST", to port ddr_init_done
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port ddr_init_done
Adding property PAP_IO_DIRECTION, value "Output", to port ddrphy_rst_done
Adding property PAP_IO_LOC, value "A2", to port ddrphy_rst_done
Adding property PAP_IO_VCCIO, value 3.3, to port ddrphy_rst_done
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port ddrphy_rst_done
Adding property PAP_IO_DRIVE, value 4, to port ddrphy_rst_done
Adding property PAP_IO_PULLUP, value "TRUE", to port ddrphy_rst_done
Adding property PAP_IO_SLEW, value "FAST", to port ddrphy_rst_done
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port ddrphy_rst_done
Adding property PAP_IO_DIRECTION, value "Input", to port pad_loop_in
Adding property PAP_IO_LOC, value "P7", to port pad_loop_in
Adding property PAP_IO_VCCIO, value 1.5, to port pad_loop_in
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_loop_in
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_loop_in
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_loop_in
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_loop_in
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_loop_in
Adding property PAP_IO_DIRECTION, value "Input", to port pad_loop_in_h
Adding property PAP_IO_LOC, value "V4", to port pad_loop_in_h
Adding property PAP_IO_VCCIO, value 1.5, to port pad_loop_in_h
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_loop_in_h
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_loop_in_h
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_loop_in_h
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_loop_in_h
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_loop_in_h
Adding property PAP_IO_DIRECTION, value "Output", to port pad_rstn_ch0
Adding property PAP_IO_LOC, value "M2", to port pad_rstn_ch0
Adding property PAP_IO_VCCIO, value 1.5, to port pad_rstn_ch0
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_rstn_ch0
Adding property PAP_IO_DRIVE, value 7.5, to port pad_rstn_ch0
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_rstn_ch0
Adding property PAP_IO_SLEW, value "FAST", to port pad_rstn_ch0
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ddr_clk_w
Adding property PAP_IO_LOC, value "U3", to port pad_ddr_clk_w
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ddr_clk_w
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_ddr_clk_w
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ddr_clk_w
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ddr_clk_w
Adding property PAP_IO_SLEW, value "FAST", to port pad_ddr_clk_w
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ddr_clkn_w
Adding property PAP_IO_LOC, value "V3", to port pad_ddr_clkn_w
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ddr_clkn_w
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_ddr_clkn_w
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ddr_clkn_w
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ddr_clkn_w
Adding property PAP_IO_SLEW, value "FAST", to port pad_ddr_clkn_w
Adding property PAP_IO_DIRECTION, value "Output", to port pad_csn_ch0
Adding property PAP_IO_LOC, value "R1", to port pad_csn_ch0
Adding property PAP_IO_VCCIO, value 1.5, to port pad_csn_ch0
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_csn_ch0
Adding property PAP_IO_DRIVE, value 7.5, to port pad_csn_ch0
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_csn_ch0
Adding property PAP_IO_SLEW, value "FAST", to port pad_csn_ch0
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[0]
Adding property PAP_IO_LOC, value "M4", to port pad_addr_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[10]
Adding property PAP_IO_LOC, value "M6", to port pad_addr_ch0[10]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[10]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[10]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[10]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[10]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[10]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[11]
Adding property PAP_IO_LOC, value "L1", to port pad_addr_ch0[11]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[11]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[11]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[11]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[11]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[11]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[12]
Adding property PAP_IO_LOC, value "K2", to port pad_addr_ch0[12]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[12]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[12]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[12]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[12]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[12]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[13]
Adding property PAP_IO_LOC, value "K1", to port pad_addr_ch0[13]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[13]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[13]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[13]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[13]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[13]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[14]
Adding property PAP_IO_LOC, value "J2", to port pad_addr_ch0[14]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[14]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[14]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[14]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[14]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[14]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[15]
Adding property PAP_IO_LOC, value "J1", to port pad_addr_ch0[15]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[15]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[15]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[15]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[15]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[15]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[1]
Adding property PAP_IO_LOC, value "M3", to port pad_addr_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[2]
Adding property PAP_IO_LOC, value "P2", to port pad_addr_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[2]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[3]
Adding property PAP_IO_LOC, value "P1", to port pad_addr_ch0[3]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[3]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[3]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[3]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[3]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[3]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[4]
Adding property PAP_IO_LOC, value "L5", to port pad_addr_ch0[4]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[4]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[4]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[4]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[4]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[4]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[5]
Adding property PAP_IO_LOC, value "M5", to port pad_addr_ch0[5]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[5]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[5]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[5]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[5]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[5]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[6]
Adding property PAP_IO_LOC, value "N2", to port pad_addr_ch0[6]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[6]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[6]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[6]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[6]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[6]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[7]
Adding property PAP_IO_LOC, value "N1", to port pad_addr_ch0[7]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[7]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[7]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[7]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[7]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[7]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[8]
Adding property PAP_IO_LOC, value "K4", to port pad_addr_ch0[8]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[8]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[8]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[8]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[8]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[8]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[9]
Adding property PAP_IO_LOC, value "M1", to port pad_addr_ch0[9]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[9]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[9]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[9]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[9]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[9]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[0]
Adding property PAP_IO_LOC, value "T8", to port pad_dq_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[0]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[0]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[10]
Adding property PAP_IO_LOC, value "U9", to port pad_dq_ch0[10]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[10]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[10]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[10]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[10]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[10]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[10]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[10]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[10]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[11]
Adding property PAP_IO_LOC, value "V7", to port pad_dq_ch0[11]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[11]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[11]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[11]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[11]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[11]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[11]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[11]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[11]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[12]
Adding property PAP_IO_LOC, value "U7", to port pad_dq_ch0[12]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[12]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[12]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[12]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[12]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[12]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[12]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[12]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[12]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[13]
Adding property PAP_IO_LOC, value "V6", to port pad_dq_ch0[13]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[13]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[13]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[13]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[13]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[13]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[13]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[13]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[13]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[14]
Adding property PAP_IO_LOC, value "U6", to port pad_dq_ch0[14]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[14]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[14]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[14]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[14]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[14]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[14]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[14]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[14]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[15]
Adding property PAP_IO_LOC, value "V5", to port pad_dq_ch0[15]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[15]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[15]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[15]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[15]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[15]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[15]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[15]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[15]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[1]
Adding property PAP_IO_LOC, value "T6", to port pad_dq_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[1]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[1]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[1]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[2]
Adding property PAP_IO_LOC, value "R6", to port pad_dq_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[2]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[2]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[2]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[2]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[3]
Adding property PAP_IO_LOC, value "R9", to port pad_dq_ch0[3]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[3]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[3]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[3]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[3]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[3]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[3]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[3]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[3]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[4]
Adding property PAP_IO_LOC, value "T9", to port pad_dq_ch0[4]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[4]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[4]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[4]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[4]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[4]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[4]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[4]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[4]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[5]
Adding property PAP_IO_LOC, value "N4", to port pad_dq_ch0[5]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[5]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[5]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[5]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[5]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[5]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[5]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[5]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[5]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[6]
Adding property PAP_IO_LOC, value "N5", to port pad_dq_ch0[6]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[6]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[6]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[6]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[6]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[6]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[6]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[6]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[6]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[7]
Adding property PAP_IO_LOC, value "P6", to port pad_dq_ch0[7]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[7]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[7]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[7]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[7]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[7]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[7]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[7]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[7]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[8]
Adding property PAP_IO_LOC, value "T4", to port pad_dq_ch0[8]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[8]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[8]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[8]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[8]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[8]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[8]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[8]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[8]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[9]
Adding property PAP_IO_LOC, value "V9", to port pad_dq_ch0[9]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[9]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[9]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[9]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[9]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[9]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[9]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[9]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[9]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqs_ch0[0]
Adding property PAP_IO_LOC, value "N6", to port pad_dqs_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqs_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqs_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqs_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqs_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqs_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqs_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqs_ch0[1]
Adding property PAP_IO_LOC, value "U8", to port pad_dqs_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqs_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqs_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqs_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqs_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqs_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqs_ch0[1]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqsn_ch0[0]
Adding property PAP_IO_LOC, value "N7", to port pad_dqsn_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqsn_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqsn_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqsn_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqsn_ch0[1]
Adding property PAP_IO_LOC, value "V8", to port pad_dqsn_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqsn_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqsn_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqsn_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_LOC, value "R8", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_LOC, value "U5", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_cke_ch0
Adding property PAP_IO_LOC, value "L4", to port pad_cke_ch0
Adding property PAP_IO_VCCIO, value 1.5, to port pad_cke_ch0
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_cke_ch0
Adding property PAP_IO_DRIVE, value 7.5, to port pad_cke_ch0
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_cke_ch0
Adding property PAP_IO_SLEW, value "FAST", to port pad_cke_ch0
Adding property PAP_IO_DIRECTION, value "Output", to port pad_odt_ch0
Adding property PAP_IO_LOC, value "V2", to port pad_odt_ch0
Adding property PAP_IO_VCCIO, value 1.5, to port pad_odt_ch0
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_odt_ch0
Adding property PAP_IO_DRIVE, value 7.5, to port pad_odt_ch0
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_odt_ch0
Adding property PAP_IO_SLEW, value "FAST", to port pad_odt_ch0
Adding property PAP_IO_DIRECTION, value "Output", to port pad_rasn_ch0
Adding property PAP_IO_LOC, value "R2", to port pad_rasn_ch0
Adding property PAP_IO_VCCIO, value 1.5, to port pad_rasn_ch0
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_rasn_ch0
Adding property PAP_IO_DRIVE, value 7.5, to port pad_rasn_ch0
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_rasn_ch0
Adding property PAP_IO_SLEW, value "FAST", to port pad_rasn_ch0
Adding property PAP_IO_DIRECTION, value "Output", to port pad_casn_ch0
Adding property PAP_IO_LOC, value "T1", to port pad_casn_ch0
Adding property PAP_IO_VCCIO, value 1.5, to port pad_casn_ch0
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_casn_ch0
Adding property PAP_IO_DRIVE, value 7.5, to port pad_casn_ch0
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_casn_ch0
Adding property PAP_IO_SLEW, value "FAST", to port pad_casn_ch0
Adding property PAP_IO_DIRECTION, value "Output", to port pad_wen_ch0
Adding property PAP_IO_LOC, value "V1", to port pad_wen_ch0
Adding property PAP_IO_VCCIO, value 1.5, to port pad_wen_ch0
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_wen_ch0
Adding property PAP_IO_DRIVE, value 7.5, to port pad_wen_ch0
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_wen_ch0
Adding property PAP_IO_SLEW, value "FAST", to port pad_wen_ch0
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[0]
Adding property PAP_IO_LOC, value "U2", to port pad_ba_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[1]
Adding property PAP_IO_LOC, value "U1", to port pad_ba_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[2]
Adding property PAP_IO_LOC, value "T2", to port pad_ba_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[2]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_loop_out
Adding property PAP_IO_LOC, value "P8", to port pad_loop_out
Adding property PAP_IO_VCCIO, value 1.5, to port pad_loop_out
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_loop_out
Adding property PAP_IO_DRIVE, value 7.5, to port pad_loop_out
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_loop_out
Adding property PAP_IO_SLEW, value "FAST", to port pad_loop_out
Adding property PAP_IO_DIRECTION, value "Output", to port pad_loop_out_h
Adding property PAP_IO_LOC, value "U4", to port pad_loop_out_h
Adding property PAP_IO_VCCIO, value 1.5, to port pad_loop_out_h
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_loop_out_h
Adding property PAP_IO_DRIVE, value 7.5, to port pad_loop_out_h
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_loop_out_h
Adding property PAP_IO_SLEW, value "FAST", to port pad_loop_out_h
Adding property PAP_IO_DIRECTION, value "Output", to port err_flag
Adding property PAP_IO_LOC, value "B1", to port err_flag
Adding property PAP_IO_VCCIO, value 3.3, to port err_flag
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port err_flag
Adding property PAP_IO_DRIVE, value 4, to port err_flag
Adding property PAP_IO_PULLUP, value "TRUE", to port err_flag
Adding property PAP_IO_SLEW, value "FAST", to port err_flag
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port err_flag
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_clk_p
Adding property PAP_IO_LOC, value "B16", to port tmds_clk_p
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_clk_p
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_clk_p
Adding property PAP_IO_DRIVE, value 12, to port tmds_clk_p
Adding property PAP_IO_NONE, value "TRUE", to port tmds_clk_p
Adding property PAP_IO_SLEW, value "FAST", to port tmds_clk_p
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_clk_p
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_clk_n
Adding property PAP_IO_LOC, value "A16", to port tmds_clk_n
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_clk_n
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_clk_n
Adding property PAP_IO_DRIVE, value 12, to port tmds_clk_n
Adding property PAP_IO_NONE, value "TRUE", to port tmds_clk_n
Adding property PAP_IO_SLEW, value "FAST", to port tmds_clk_n
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_clk_n
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_p[0]
Adding property PAP_IO_LOC, value "B14", to port tmds_data_p[0]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_p[0]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_p[0]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_p[0]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_p[0]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_p[0]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_p[0]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_p[1]
Adding property PAP_IO_LOC, value "B11", to port tmds_data_p[1]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_p[1]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_p[1]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_p[1]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_p[1]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_p[1]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_p[1]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_p[2]
Adding property PAP_IO_LOC, value "B10", to port tmds_data_p[2]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_p[2]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_p[2]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_p[2]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_p[2]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_p[2]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_p[2]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_n[0]
Adding property PAP_IO_LOC, value "A14", to port tmds_data_n[0]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_n[0]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_n[0]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_n[0]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_n[0]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_n[0]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_n[0]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_n[1]
Adding property PAP_IO_LOC, value "A11", to port tmds_data_n[1]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_n[1]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_n[1]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_n[1]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_n[1]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_n[1]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_n[1]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_n[2]
Adding property PAP_IO_LOC, value "A10", to port tmds_data_n[2]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_n[2]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_n[2]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_n[2]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_n[2]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_n[2]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_n[2]
Adding property PAP_LOC, value "PLL_82_71", to instance u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1

Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)

@N:MO111 : ipsl_hmemc_top_test.v(42) | Tristate driver err_flag (in view: work.ipsl_hmemc_top_test(verilog)) on net err_flag (in view: work.ipsl_hmemc_top_test(verilog)) has its enable tied to GND.
@N:MO111 : ipsl_phy_io.v(175) | Tristate driver DQS_DRIFT_H_1 (in view: work.ipsl_phy_io_Z8(verilog)) on net DQS_DRIFT_H_1 (in view: work.ipsl_phy_io_Z8(verilog)) has its enable tied to GND.
@N:MO111 : ipsl_phy_io.v(175) | Tristate driver DQS_DRIFT_H_2 (in view: work.ipsl_phy_io_Z8(verilog)) on net DQS_DRIFT_H_2 (in view: work.ipsl_phy_io_Z8(verilog)) has its enable tied to GND.
@N:MO111 : ipsl_phy_io.v(174) | Tristate driver DQS_DRIFT_L_1 (in view: work.ipsl_phy_io_Z8(verilog)) on net DQS_DRIFT_L_1 (in view: work.ipsl_phy_io_Z8(verilog)) has its enable tied to GND.
@N:MO111 : ipsl_phy_io.v(174) | Tristate driver DQS_DRIFT_L_2 (in view: work.ipsl_phy_io_Z8(verilog)) on net DQS_DRIFT_L_2 (in view: work.ipsl_phy_io_Z8(verilog)) has its enable tied to GND.
@N:MO111 : ipsl_phy_io.v(100) | Tristate driver PSLVERR (in view: work.ipsl_phy_io_Z8(verilog)) on net PSLVERR (in view: work.ipsl_phy_io_Z8(verilog)) has its enable tied to GND.
@W:MO171 : encode.v(135) | Sequential instance dvi_encoder_m0.encg.c0_q is reduced to a combinational gate by constant propagation. 
@W:MO171 : encode.v(135) | Sequential instance dvi_encoder_m0.encr.c0_q is reduced to a combinational gate by constant propagation. 
@W:MO171 : encode.v(135) | Sequential instance dvi_encoder_m0.encg.c1_q is reduced to a combinational gate by constant propagation. 
@W:MO171 : encode.v(135) | Sequential instance dvi_encoder_m0.encr.c1_q is reduced to a combinational gate by constant propagation. 
@W:FX1172 : serdes_4b_10to1.v(48) | User-specified initial value defined for instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[2:0] is being ignored due to limitations in architecture. 
@W:FX1172 : serdes_4b_10to1.v(48) | User-specified initial value defined for instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_3l[4:0] is being ignored due to limitations in architecture. 
@W:FX1172 : serdes_4b_10to1.v(48) | User-specified initial value defined for instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_3h[4:0] is being ignored due to limitations in architecture. 
@W:FX1172 : serdes_4b_10to1.v(48) | User-specified initial value defined for instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_2l[4:0] is being ignored due to limitations in architecture. 
@W:FX1172 : serdes_4b_10to1.v(48) | User-specified initial value defined for instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_2h[4:0] is being ignored due to limitations in architecture. 
@W:FX1172 : serdes_4b_10to1.v(48) | User-specified initial value defined for instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_1l[4:0] is being ignored due to limitations in architecture. 
@W:FX1172 : serdes_4b_10to1.v(48) | User-specified initial value defined for instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_1h[4:0] is being ignored due to limitations in architecture. 
@W:FX1172 : serdes_4b_10to1.v(48) | User-specified initial value defined for instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_0l[4:0] is being ignored due to limitations in architecture. 
@W:FX1172 : serdes_4b_10to1.v(48) | User-specified initial value defined for instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_0h[4:0] is being ignored due to limitations in architecture. 
@W:BN132 : ipsl_ddrphy_reset_ctrl.v(141) | Removing sequential instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_ddrphy_reset_ctrl.srb_ioclkdiv_rstn because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_ddrphy_reset_ctrl.srb_dqs_rstn. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : ipsl_ddrc_reset_ctrl.v(125) | Removing sequential instance u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.init_axi_reset2 because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.init_ddrc_rst. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : ipsl_ddrc_reset_ctrl.v(125) | Removing sequential instance u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.init_axi_reset1 because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.init_ddrc_rst. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : ipsl_ddrc_reset_ctrl.v(125) | Removing sequential instance u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.init_axi_reset0 because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.init_ddrc_rst. To keep the instance, apply constraint syn_preserve=1 on the instance.
Adding property PAP_IO_DIRECTION, value "Output", to port led[0]
Adding property PAP_IO_LOC, value "U10", to port led[0]
Adding property PAP_IO_VCCIO, value 3.3, to port led[0]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[0]
Adding property PAP_IO_DRIVE, value 4, to port led[0]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[0]
Adding property PAP_IO_SLEW, value "FAST", to port led[0]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[0]
Adding property PAP_IO_DIRECTION, value "Output", to port led[1]
Adding property PAP_IO_LOC, value "V10", to port led[1]
Adding property PAP_IO_VCCIO, value 3.3, to port led[1]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[1]
Adding property PAP_IO_DRIVE, value 4, to port led[1]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[1]
Adding property PAP_IO_SLEW, value "FAST", to port led[1]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[1]
Adding property PAP_IO_DIRECTION, value "Output", to port led[2]
Adding property PAP_IO_LOC, value "U11", to port led[2]
Adding property PAP_IO_VCCIO, value 3.3, to port led[2]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[2]
Adding property PAP_IO_DRIVE, value 4, to port led[2]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[2]
Adding property PAP_IO_SLEW, value "FAST", to port led[2]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[2]
Adding property PAP_IO_DIRECTION, value "Output", to port led[3]
Adding property PAP_IO_LOC, value "V11", to port led[3]
Adding property PAP_IO_VCCIO, value 3.3, to port led[3]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[3]
Adding property PAP_IO_DRIVE, value 4, to port led[3]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[3]
Adding property PAP_IO_SLEW, value "FAST", to port led[3]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[3]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[0]
Adding property PAP_IO_LOC, value "M4", to port pad_addr_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[10]
Adding property PAP_IO_LOC, value "M6", to port pad_addr_ch0[10]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[10]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[10]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[10]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[10]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[10]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[11]
Adding property PAP_IO_LOC, value "L1", to port pad_addr_ch0[11]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[11]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[11]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[11]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[11]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[11]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[12]
Adding property PAP_IO_LOC, value "K2", to port pad_addr_ch0[12]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[12]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[12]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[12]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[12]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[12]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[13]
Adding property PAP_IO_LOC, value "K1", to port pad_addr_ch0[13]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[13]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[13]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[13]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[13]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[13]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[14]
Adding property PAP_IO_LOC, value "J2", to port pad_addr_ch0[14]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[14]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[14]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[14]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[14]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[14]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[15]
Adding property PAP_IO_LOC, value "J1", to port pad_addr_ch0[15]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[15]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[15]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[15]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[15]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[15]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[1]
Adding property PAP_IO_LOC, value "M3", to port pad_addr_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[2]
Adding property PAP_IO_LOC, value "P2", to port pad_addr_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[2]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[3]
Adding property PAP_IO_LOC, value "P1", to port pad_addr_ch0[3]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[3]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[3]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[3]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[3]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[3]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[4]
Adding property PAP_IO_LOC, value "L5", to port pad_addr_ch0[4]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[4]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[4]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[4]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[4]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[4]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[5]
Adding property PAP_IO_LOC, value "M5", to port pad_addr_ch0[5]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[5]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[5]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[5]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[5]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[5]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[6]
Adding property PAP_IO_LOC, value "N2", to port pad_addr_ch0[6]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[6]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[6]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[6]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[6]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[6]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[7]
Adding property PAP_IO_LOC, value "N1", to port pad_addr_ch0[7]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[7]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[7]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[7]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[7]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[7]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[8]
Adding property PAP_IO_LOC, value "K4", to port pad_addr_ch0[8]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[8]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[8]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[8]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[8]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[8]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[9]
Adding property PAP_IO_LOC, value "M1", to port pad_addr_ch0[9]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[9]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[9]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[9]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[9]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[9]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[0]
Adding property PAP_IO_LOC, value "T8", to port pad_dq_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[0]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[0]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[10]
Adding property PAP_IO_LOC, value "U9", to port pad_dq_ch0[10]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[10]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[10]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[10]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[10]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[10]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[10]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[10]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[10]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[11]
Adding property PAP_IO_LOC, value "V7", to port pad_dq_ch0[11]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[11]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[11]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[11]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[11]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[11]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[11]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[11]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[11]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[12]
Adding property PAP_IO_LOC, value "U7", to port pad_dq_ch0[12]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[12]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[12]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[12]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[12]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[12]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[12]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[12]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[12]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[13]
Adding property PAP_IO_LOC, value "V6", to port pad_dq_ch0[13]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[13]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[13]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[13]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[13]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[13]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[13]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[13]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[13]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[14]
Adding property PAP_IO_LOC, value "U6", to port pad_dq_ch0[14]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[14]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[14]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[14]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[14]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[14]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[14]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[14]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[14]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[15]
Adding property PAP_IO_LOC, value "V5", to port pad_dq_ch0[15]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[15]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[15]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[15]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[15]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[15]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[15]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[15]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[15]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[1]
Adding property PAP_IO_LOC, value "T6", to port pad_dq_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[1]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[1]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[1]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[2]
Adding property PAP_IO_LOC, value "R6", to port pad_dq_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[2]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[2]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[2]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[2]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[3]
Adding property PAP_IO_LOC, value "R9", to port pad_dq_ch0[3]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[3]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[3]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[3]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[3]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[3]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[3]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[3]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[3]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[4]
Adding property PAP_IO_LOC, value "T9", to port pad_dq_ch0[4]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[4]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[4]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[4]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[4]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[4]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[4]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[4]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[4]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[5]
Adding property PAP_IO_LOC, value "N4", to port pad_dq_ch0[5]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[5]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[5]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[5]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[5]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[5]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[5]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[5]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[5]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[6]
Adding property PAP_IO_LOC, value "N5", to port pad_dq_ch0[6]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[6]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[6]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[6]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[6]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[6]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[6]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[6]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[6]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[7]
Adding property PAP_IO_LOC, value "P6", to port pad_dq_ch0[7]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[7]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[7]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[7]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[7]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[7]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[7]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[7]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[7]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[8]
Adding property PAP_IO_LOC, value "T4", to port pad_dq_ch0[8]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[8]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[8]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[8]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[8]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[8]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[8]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[8]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[8]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[9]
Adding property PAP_IO_LOC, value "V9", to port pad_dq_ch0[9]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[9]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[9]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[9]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[9]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[9]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[9]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[9]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[9]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqs_ch0[0]
Adding property PAP_IO_LOC, value "N6", to port pad_dqs_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqs_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqs_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqs_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqs_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqs_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqs_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqs_ch0[1]
Adding property PAP_IO_LOC, value "U8", to port pad_dqs_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqs_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqs_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqs_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqs_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqs_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqs_ch0[1]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqsn_ch0[0]
Adding property PAP_IO_LOC, value "N7", to port pad_dqsn_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqsn_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqsn_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqsn_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqsn_ch0[1]
Adding property PAP_IO_LOC, value "V8", to port pad_dqsn_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqsn_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqsn_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqsn_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_LOC, value "R8", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_LOC, value "U5", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[0]
Adding property PAP_IO_LOC, value "U2", to port pad_ba_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[1]
Adding property PAP_IO_LOC, value "U1", to port pad_ba_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[2]
Adding property PAP_IO_LOC, value "T2", to port pad_ba_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[2]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_p[0]
Adding property PAP_IO_LOC, value "B14", to port tmds_data_p[0]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_p[0]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_p[0]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_p[0]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_p[0]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_p[0]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_p[0]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_p[1]
Adding property PAP_IO_LOC, value "B11", to port tmds_data_p[1]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_p[1]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_p[1]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_p[1]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_p[1]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_p[1]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_p[1]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_p[2]
Adding property PAP_IO_LOC, value "B10", to port tmds_data_p[2]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_p[2]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_p[2]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_p[2]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_p[2]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_p[2]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_p[2]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_n[0]
Adding property PAP_IO_LOC, value "A14", to port tmds_data_n[0]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_n[0]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_n[0]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_n[0]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_n[0]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_n[0]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_n[0]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_n[1]
Adding property PAP_IO_LOC, value "A11", to port tmds_data_n[1]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_n[1]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_n[1]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_n[1]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_n[1]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_n[1]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_n[1]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_n[2]
Adding property PAP_IO_LOC, value "A10", to port tmds_data_n[2]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_n[2]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_n[2]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_n[2]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_n[2]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_n[2]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_n[2]
Adding property PAP_IO_DIRECTION, value "Output", to port led[0]
Adding property PAP_IO_LOC, value "U10", to port led[0]
Adding property PAP_IO_VCCIO, value 3.3, to port led[0]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[0]
Adding property PAP_IO_DRIVE, value 4, to port led[0]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[0]
Adding property PAP_IO_SLEW, value "FAST", to port led[0]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[0]
Adding property PAP_IO_DIRECTION, value "Output", to port led[1]
Adding property PAP_IO_LOC, value "V10", to port led[1]
Adding property PAP_IO_VCCIO, value 3.3, to port led[1]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[1]
Adding property PAP_IO_DRIVE, value 4, to port led[1]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[1]
Adding property PAP_IO_SLEW, value "FAST", to port led[1]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[1]
Adding property PAP_IO_DIRECTION, value "Output", to port led[2]
Adding property PAP_IO_LOC, value "U11", to port led[2]
Adding property PAP_IO_VCCIO, value 3.3, to port led[2]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[2]
Adding property PAP_IO_DRIVE, value 4, to port led[2]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[2]
Adding property PAP_IO_SLEW, value "FAST", to port led[2]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[2]
Adding property PAP_IO_DIRECTION, value "Output", to port led[3]
Adding property PAP_IO_LOC, value "V11", to port led[3]
Adding property PAP_IO_VCCIO, value 3.3, to port led[3]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[3]
Adding property PAP_IO_DRIVE, value 4, to port led[3]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[3]
Adding property PAP_IO_SLEW, value "FAST", to port led[3]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[3]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[0]
Adding property PAP_IO_LOC, value "M4", to port pad_addr_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[10]
Adding property PAP_IO_LOC, value "M6", to port pad_addr_ch0[10]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[10]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[10]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[10]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[10]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[10]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[11]
Adding property PAP_IO_LOC, value "L1", to port pad_addr_ch0[11]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[11]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[11]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[11]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[11]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[11]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[12]
Adding property PAP_IO_LOC, value "K2", to port pad_addr_ch0[12]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[12]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[12]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[12]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[12]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[12]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[13]
Adding property PAP_IO_LOC, value "K1", to port pad_addr_ch0[13]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[13]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[13]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[13]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[13]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[13]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[14]
Adding property PAP_IO_LOC, value "J2", to port pad_addr_ch0[14]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[14]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[14]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[14]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[14]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[14]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[15]
Adding property PAP_IO_LOC, value "J1", to port pad_addr_ch0[15]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[15]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[15]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[15]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[15]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[15]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[1]
Adding property PAP_IO_LOC, value "M3", to port pad_addr_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[2]
Adding property PAP_IO_LOC, value "P2", to port pad_addr_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[2]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[3]
Adding property PAP_IO_LOC, value "P1", to port pad_addr_ch0[3]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[3]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[3]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[3]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[3]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[3]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[4]
Adding property PAP_IO_LOC, value "L5", to port pad_addr_ch0[4]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[4]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[4]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[4]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[4]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[4]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[5]
Adding property PAP_IO_LOC, value "M5", to port pad_addr_ch0[5]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[5]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[5]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[5]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[5]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[5]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[6]
Adding property PAP_IO_LOC, value "N2", to port pad_addr_ch0[6]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[6]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[6]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[6]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[6]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[6]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[7]
Adding property PAP_IO_LOC, value "N1", to port pad_addr_ch0[7]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[7]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[7]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[7]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[7]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[7]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[8]
Adding property PAP_IO_LOC, value "K4", to port pad_addr_ch0[8]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[8]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[8]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[8]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[8]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[8]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[9]
Adding property PAP_IO_LOC, value "M1", to port pad_addr_ch0[9]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[9]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[9]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[9]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[9]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[9]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[0]
Adding property PAP_IO_LOC, value "T8", to port pad_dq_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[0]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[0]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[10]
Adding property PAP_IO_LOC, value "U9", to port pad_dq_ch0[10]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[10]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[10]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[10]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[10]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[10]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[10]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[10]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[10]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[11]
Adding property PAP_IO_LOC, value "V7", to port pad_dq_ch0[11]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[11]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[11]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[11]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[11]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[11]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[11]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[11]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[11]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[12]
Adding property PAP_IO_LOC, value "U7", to port pad_dq_ch0[12]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[12]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[12]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[12]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[12]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[12]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[12]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[12]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[12]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[13]
Adding property PAP_IO_LOC, value "V6", to port pad_dq_ch0[13]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[13]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[13]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[13]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[13]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[13]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[13]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[13]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[13]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[14]
Adding property PAP_IO_LOC, value "U6", to port pad_dq_ch0[14]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[14]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[14]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[14]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[14]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[14]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[14]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[14]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[14]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[15]
Adding property PAP_IO_LOC, value "V5", to port pad_dq_ch0[15]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[15]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[15]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[15]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[15]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[15]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[15]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[15]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[15]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[1]
Adding property PAP_IO_LOC, value "T6", to port pad_dq_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[1]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[1]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[1]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[2]
Adding property PAP_IO_LOC, value "R6", to port pad_dq_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[2]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[2]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[2]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[2]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[3]
Adding property PAP_IO_LOC, value "R9", to port pad_dq_ch0[3]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[3]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[3]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[3]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[3]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[3]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[3]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[3]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[3]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[4]
Adding property PAP_IO_LOC, value "T9", to port pad_dq_ch0[4]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[4]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[4]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[4]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[4]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[4]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[4]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[4]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[4]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[5]
Adding property PAP_IO_LOC, value "N4", to port pad_dq_ch0[5]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[5]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[5]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[5]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[5]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[5]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[5]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[5]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[5]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[6]
Adding property PAP_IO_LOC, value "N5", to port pad_dq_ch0[6]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[6]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[6]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[6]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[6]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[6]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[6]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[6]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[6]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[7]
Adding property PAP_IO_LOC, value "P6", to port pad_dq_ch0[7]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[7]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[7]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[7]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[7]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[7]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[7]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[7]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[7]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[8]
Adding property PAP_IO_LOC, value "T4", to port pad_dq_ch0[8]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[8]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[8]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[8]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[8]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[8]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[8]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[8]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[8]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[9]
Adding property PAP_IO_LOC, value "V9", to port pad_dq_ch0[9]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[9]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[9]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[9]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[9]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[9]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[9]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[9]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[9]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqs_ch0[0]
Adding property PAP_IO_LOC, value "N6", to port pad_dqs_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqs_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqs_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqs_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqs_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqs_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqs_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqs_ch0[1]
Adding property PAP_IO_LOC, value "U8", to port pad_dqs_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqs_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqs_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqs_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqs_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqs_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqs_ch0[1]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqsn_ch0[0]
Adding property PAP_IO_LOC, value "N7", to port pad_dqsn_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqsn_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqsn_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqsn_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqsn_ch0[1]
Adding property PAP_IO_LOC, value "V8", to port pad_dqsn_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqsn_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqsn_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqsn_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_LOC, value "R8", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_LOC, value "U5", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[0]
Adding property PAP_IO_LOC, value "U2", to port pad_ba_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[1]
Adding property PAP_IO_LOC, value "U1", to port pad_ba_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[2]
Adding property PAP_IO_LOC, value "T2", to port pad_ba_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[2]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_p[0]
Adding property PAP_IO_LOC, value "B14", to port tmds_data_p[0]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_p[0]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_p[0]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_p[0]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_p[0]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_p[0]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_p[0]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_p[1]
Adding property PAP_IO_LOC, value "B11", to port tmds_data_p[1]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_p[1]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_p[1]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_p[1]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_p[1]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_p[1]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_p[1]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_p[2]
Adding property PAP_IO_LOC, value "B10", to port tmds_data_p[2]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_p[2]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_p[2]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_p[2]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_p[2]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_p[2]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_p[2]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_n[0]
Adding property PAP_IO_LOC, value "A14", to port tmds_data_n[0]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_n[0]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_n[0]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_n[0]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_n[0]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_n[0]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_n[0]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_n[1]
Adding property PAP_IO_LOC, value "A11", to port tmds_data_n[1]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_n[1]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_n[1]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_n[1]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_n[1]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_n[1]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_n[1]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_n[2]
Adding property PAP_IO_LOC, value "A10", to port tmds_data_n[2]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_n[2]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_n[2]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_n[2]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_n[2]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_n[2]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_n[2]
Adding property PAP_IO_DIRECTION, value "Output", to port led[0]
Adding property PAP_IO_LOC, value "U10", to port led[0]
Adding property PAP_IO_VCCIO, value 3.3, to port led[0]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[0]
Adding property PAP_IO_DRIVE, value 4, to port led[0]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[0]
Adding property PAP_IO_SLEW, value "FAST", to port led[0]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[0]
Adding property PAP_IO_DIRECTION, value "Output", to port led[1]
Adding property PAP_IO_LOC, value "V10", to port led[1]
Adding property PAP_IO_VCCIO, value 3.3, to port led[1]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[1]
Adding property PAP_IO_DRIVE, value 4, to port led[1]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[1]
Adding property PAP_IO_SLEW, value "FAST", to port led[1]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[1]
Adding property PAP_IO_DIRECTION, value "Output", to port led[2]
Adding property PAP_IO_LOC, value "U11", to port led[2]
Adding property PAP_IO_VCCIO, value 3.3, to port led[2]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[2]
Adding property PAP_IO_DRIVE, value 4, to port led[2]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[2]
Adding property PAP_IO_SLEW, value "FAST", to port led[2]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[2]
Adding property PAP_IO_DIRECTION, value "Output", to port led[3]
Adding property PAP_IO_LOC, value "V11", to port led[3]
Adding property PAP_IO_VCCIO, value 3.3, to port led[3]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[3]
Adding property PAP_IO_DRIVE, value 4, to port led[3]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[3]
Adding property PAP_IO_SLEW, value "FAST", to port led[3]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[3]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[0]
Adding property PAP_IO_LOC, value "M4", to port pad_addr_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[10]
Adding property PAP_IO_LOC, value "M6", to port pad_addr_ch0[10]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[10]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[10]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[10]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[10]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[10]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[11]
Adding property PAP_IO_LOC, value "L1", to port pad_addr_ch0[11]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[11]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[11]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[11]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[11]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[11]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[12]
Adding property PAP_IO_LOC, value "K2", to port pad_addr_ch0[12]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[12]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[12]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[12]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[12]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[12]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[13]
Adding property PAP_IO_LOC, value "K1", to port pad_addr_ch0[13]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[13]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[13]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[13]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[13]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[13]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[14]
Adding property PAP_IO_LOC, value "J2", to port pad_addr_ch0[14]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[14]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[14]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[14]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[14]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[14]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[15]
Adding property PAP_IO_LOC, value "J1", to port pad_addr_ch0[15]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[15]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[15]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[15]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[15]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[15]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[1]
Adding property PAP_IO_LOC, value "M3", to port pad_addr_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[2]
Adding property PAP_IO_LOC, value "P2", to port pad_addr_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[2]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[3]
Adding property PAP_IO_LOC, value "P1", to port pad_addr_ch0[3]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[3]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[3]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[3]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[3]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[3]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[4]
Adding property PAP_IO_LOC, value "L5", to port pad_addr_ch0[4]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[4]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[4]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[4]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[4]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[4]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[5]
Adding property PAP_IO_LOC, value "M5", to port pad_addr_ch0[5]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[5]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[5]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[5]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[5]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[5]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[6]
Adding property PAP_IO_LOC, value "N2", to port pad_addr_ch0[6]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[6]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[6]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[6]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[6]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[6]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[7]
Adding property PAP_IO_LOC, value "N1", to port pad_addr_ch0[7]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[7]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[7]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[7]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[7]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[7]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[8]
Adding property PAP_IO_LOC, value "K4", to port pad_addr_ch0[8]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[8]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[8]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[8]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[8]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[8]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[9]
Adding property PAP_IO_LOC, value "M1", to port pad_addr_ch0[9]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[9]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[9]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[9]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[9]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[9]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[0]
Adding property PAP_IO_LOC, value "T8", to port pad_dq_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[0]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[0]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[10]
Adding property PAP_IO_LOC, value "U9", to port pad_dq_ch0[10]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[10]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[10]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[10]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[10]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[10]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[10]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[10]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[10]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[11]
Adding property PAP_IO_LOC, value "V7", to port pad_dq_ch0[11]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[11]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[11]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[11]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[11]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[11]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[11]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[11]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[11]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[12]
Adding property PAP_IO_LOC, value "U7", to port pad_dq_ch0[12]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[12]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[12]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[12]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[12]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[12]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[12]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[12]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[12]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[13]
Adding property PAP_IO_LOC, value "V6", to port pad_dq_ch0[13]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[13]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[13]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[13]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[13]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[13]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[13]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[13]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[13]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[14]
Adding property PAP_IO_LOC, value "U6", to port pad_dq_ch0[14]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[14]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[14]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[14]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[14]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[14]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[14]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[14]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[14]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[15]
Adding property PAP_IO_LOC, value "V5", to port pad_dq_ch0[15]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[15]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[15]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[15]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[15]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[15]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[15]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[15]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[15]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[1]
Adding property PAP_IO_LOC, value "T6", to port pad_dq_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[1]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[1]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[1]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[2]
Adding property PAP_IO_LOC, value "R6", to port pad_dq_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[2]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[2]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[2]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[2]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[3]
Adding property PAP_IO_LOC, value "R9", to port pad_dq_ch0[3]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[3]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[3]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[3]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[3]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[3]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[3]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[3]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[3]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[4]
Adding property PAP_IO_LOC, value "T9", to port pad_dq_ch0[4]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[4]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[4]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[4]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[4]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[4]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[4]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[4]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[4]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[5]
Adding property PAP_IO_LOC, value "N4", to port pad_dq_ch0[5]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[5]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[5]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[5]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[5]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[5]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[5]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[5]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[5]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[6]
Adding property PAP_IO_LOC, value "N5", to port pad_dq_ch0[6]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[6]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[6]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[6]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[6]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[6]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[6]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[6]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[6]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[7]
Adding property PAP_IO_LOC, value "P6", to port pad_dq_ch0[7]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[7]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[7]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[7]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[7]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[7]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[7]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[7]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[7]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[8]
Adding property PAP_IO_LOC, value "T4", to port pad_dq_ch0[8]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[8]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[8]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[8]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[8]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[8]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[8]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[8]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[8]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[9]
Adding property PAP_IO_LOC, value "V9", to port pad_dq_ch0[9]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[9]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[9]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[9]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[9]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[9]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[9]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[9]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[9]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqs_ch0[0]
Adding property PAP_IO_LOC, value "N6", to port pad_dqs_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqs_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqs_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqs_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqs_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqs_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqs_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqs_ch0[1]
Adding property PAP_IO_LOC, value "U8", to port pad_dqs_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqs_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqs_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqs_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqs_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqs_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqs_ch0[1]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqsn_ch0[0]
Adding property PAP_IO_LOC, value "N7", to port pad_dqsn_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqsn_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqsn_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqsn_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqsn_ch0[1]
Adding property PAP_IO_LOC, value "V8", to port pad_dqsn_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqsn_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqsn_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqsn_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_LOC, value "R8", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_LOC, value "U5", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[0]
Adding property PAP_IO_LOC, value "U2", to port pad_ba_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[1]
Adding property PAP_IO_LOC, value "U1", to port pad_ba_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[2]
Adding property PAP_IO_LOC, value "T2", to port pad_ba_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[2]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_p[0]
Adding property PAP_IO_LOC, value "B14", to port tmds_data_p[0]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_p[0]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_p[0]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_p[0]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_p[0]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_p[0]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_p[0]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_p[1]
Adding property PAP_IO_LOC, value "B11", to port tmds_data_p[1]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_p[1]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_p[1]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_p[1]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_p[1]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_p[1]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_p[1]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_p[2]
Adding property PAP_IO_LOC, value "B10", to port tmds_data_p[2]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_p[2]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_p[2]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_p[2]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_p[2]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_p[2]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_p[2]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_n[0]
Adding property PAP_IO_LOC, value "A14", to port tmds_data_n[0]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_n[0]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_n[0]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_n[0]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_n[0]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_n[0]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_n[0]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_n[1]
Adding property PAP_IO_LOC, value "A11", to port tmds_data_n[1]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_n[1]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_n[1]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_n[1]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_n[1]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_n[1]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_n[1]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_n[2]
Adding property PAP_IO_LOC, value "A10", to port tmds_data_n[2]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_n[2]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_n[2]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_n[2]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_n[2]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_n[2]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_n[2]
@N:BN362 : ax_debounce.v(100) | Removing sequential instance button_posedge (in view: work.ax_debounce(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : color_bar.v(286) | Removing sequential instance rgb_r_reg[0] (in view: work.color_bar(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : color_bar.v(286) | Removing sequential instance rgb_g_reg[0] (in view: work.color_bar(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : color_bar.v(286) | Removing sequential instance rgb_b_reg[0] (in view: work.color_bar(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : ipml_fifo_ctrl_v1_3.v(349) | Removing sequential instance wr_water_level[9:0] (in view: work.ipml_fifo_ctrl_v1_3_9s_8s_ASYN_508s_4s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : ipml_fifo_ctrl_v1_3.v(370) | Removing sequential instance rd_water_level[9:0] (in view: work.ipml_fifo_ctrl_v1_3_8s_9s_ASYN_252s_4s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : color_bar.v(215) | Removing sequential instance active_x[11:0] (in view: work.color_bar(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
Adding property PAP_IO_DIRECTION, value "Output", to port led[0]
Adding property PAP_IO_LOC, value "U10", to port led[0]
Adding property PAP_IO_VCCIO, value 3.3, to port led[0]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[0]
Adding property PAP_IO_DRIVE, value 4, to port led[0]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[0]
Adding property PAP_IO_SLEW, value "FAST", to port led[0]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[0]
Adding property PAP_IO_DIRECTION, value "Output", to port led[1]
Adding property PAP_IO_LOC, value "V10", to port led[1]
Adding property PAP_IO_VCCIO, value 3.3, to port led[1]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[1]
Adding property PAP_IO_DRIVE, value 4, to port led[1]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[1]
Adding property PAP_IO_SLEW, value "FAST", to port led[1]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[1]
Adding property PAP_IO_DIRECTION, value "Output", to port led[2]
Adding property PAP_IO_LOC, value "U11", to port led[2]
Adding property PAP_IO_VCCIO, value 3.3, to port led[2]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[2]
Adding property PAP_IO_DRIVE, value 4, to port led[2]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[2]
Adding property PAP_IO_SLEW, value "FAST", to port led[2]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[2]
Adding property PAP_IO_DIRECTION, value "Output", to port led[3]
Adding property PAP_IO_LOC, value "V11", to port led[3]
Adding property PAP_IO_VCCIO, value 3.3, to port led[3]
Adding property PAP_IO_STANDARD, value "LVCMOS33", to port led[3]
Adding property PAP_IO_DRIVE, value 4, to port led[3]
Adding property PAP_IO_PULLUP, value "TRUE", to port led[3]
Adding property PAP_IO_SLEW, value "FAST", to port led[3]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port led[3]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[0]
Adding property PAP_IO_LOC, value "M4", to port pad_addr_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[10]
Adding property PAP_IO_LOC, value "M6", to port pad_addr_ch0[10]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[10]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[10]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[10]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[10]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[10]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[11]
Adding property PAP_IO_LOC, value "L1", to port pad_addr_ch0[11]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[11]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[11]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[11]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[11]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[11]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[12]
Adding property PAP_IO_LOC, value "K2", to port pad_addr_ch0[12]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[12]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[12]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[12]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[12]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[12]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[13]
Adding property PAP_IO_LOC, value "K1", to port pad_addr_ch0[13]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[13]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[13]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[13]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[13]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[13]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[14]
Adding property PAP_IO_LOC, value "J2", to port pad_addr_ch0[14]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[14]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[14]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[14]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[14]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[14]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[15]
Adding property PAP_IO_LOC, value "J1", to port pad_addr_ch0[15]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[15]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[15]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[15]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[15]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[15]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[1]
Adding property PAP_IO_LOC, value "M3", to port pad_addr_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[2]
Adding property PAP_IO_LOC, value "P2", to port pad_addr_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[2]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[3]
Adding property PAP_IO_LOC, value "P1", to port pad_addr_ch0[3]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[3]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[3]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[3]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[3]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[3]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[4]
Adding property PAP_IO_LOC, value "L5", to port pad_addr_ch0[4]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[4]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[4]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[4]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[4]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[4]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[5]
Adding property PAP_IO_LOC, value "M5", to port pad_addr_ch0[5]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[5]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[5]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[5]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[5]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[5]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[6]
Adding property PAP_IO_LOC, value "N2", to port pad_addr_ch0[6]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[6]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[6]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[6]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[6]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[6]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[7]
Adding property PAP_IO_LOC, value "N1", to port pad_addr_ch0[7]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[7]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[7]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[7]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[7]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[7]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[8]
Adding property PAP_IO_LOC, value "K4", to port pad_addr_ch0[8]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[8]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[8]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[8]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[8]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[8]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_addr_ch0[9]
Adding property PAP_IO_LOC, value "M1", to port pad_addr_ch0[9]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_addr_ch0[9]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_addr_ch0[9]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_addr_ch0[9]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_addr_ch0[9]
Adding property PAP_IO_SLEW, value "FAST", to port pad_addr_ch0[9]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[0]
Adding property PAP_IO_LOC, value "T8", to port pad_dq_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[0]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[0]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[10]
Adding property PAP_IO_LOC, value "U9", to port pad_dq_ch0[10]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[10]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[10]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[10]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[10]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[10]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[10]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[10]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[10]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[11]
Adding property PAP_IO_LOC, value "V7", to port pad_dq_ch0[11]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[11]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[11]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[11]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[11]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[11]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[11]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[11]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[11]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[12]
Adding property PAP_IO_LOC, value "U7", to port pad_dq_ch0[12]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[12]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[12]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[12]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[12]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[12]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[12]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[12]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[12]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[13]
Adding property PAP_IO_LOC, value "V6", to port pad_dq_ch0[13]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[13]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[13]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[13]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[13]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[13]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[13]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[13]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[13]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[14]
Adding property PAP_IO_LOC, value "U6", to port pad_dq_ch0[14]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[14]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[14]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[14]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[14]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[14]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[14]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[14]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[14]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[15]
Adding property PAP_IO_LOC, value "V5", to port pad_dq_ch0[15]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[15]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[15]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[15]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[15]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[15]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[15]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[15]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[15]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[1]
Adding property PAP_IO_LOC, value "T6", to port pad_dq_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[1]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[1]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[1]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[2]
Adding property PAP_IO_LOC, value "R6", to port pad_dq_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[2]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[2]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[2]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[2]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[3]
Adding property PAP_IO_LOC, value "R9", to port pad_dq_ch0[3]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[3]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[3]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[3]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[3]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[3]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[3]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[3]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[3]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[4]
Adding property PAP_IO_LOC, value "T9", to port pad_dq_ch0[4]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[4]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[4]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[4]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[4]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[4]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[4]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[4]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[4]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[5]
Adding property PAP_IO_LOC, value "N4", to port pad_dq_ch0[5]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[5]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[5]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[5]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[5]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[5]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[5]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[5]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[5]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[6]
Adding property PAP_IO_LOC, value "N5", to port pad_dq_ch0[6]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[6]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[6]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[6]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[6]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[6]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[6]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[6]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[6]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[7]
Adding property PAP_IO_LOC, value "P6", to port pad_dq_ch0[7]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[7]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[7]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[7]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[7]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[7]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[7]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[7]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[7]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[8]
Adding property PAP_IO_LOC, value "T4", to port pad_dq_ch0[8]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[8]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[8]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[8]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[8]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[8]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[8]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[8]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[8]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dq_ch0[9]
Adding property PAP_IO_LOC, value "V9", to port pad_dq_ch0[9]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dq_ch0[9]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dq_ch0[9]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dq_ch0[9]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dq_ch0[9]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dq_ch0[9]
Adding property PAP_IO_VREF_MODE, value "IN", to port pad_dq_ch0[9]
Adding property PAP_IO_VREF_MODE_VALUE, value 0.5, to port pad_dq_ch0[9]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dq_ch0[9]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqs_ch0[0]
Adding property PAP_IO_LOC, value "N6", to port pad_dqs_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqs_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqs_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqs_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqs_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqs_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqs_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqs_ch0[1]
Adding property PAP_IO_LOC, value "U8", to port pad_dqs_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqs_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqs_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqs_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqs_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqs_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqs_ch0[1]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqsn_ch0[0]
Adding property PAP_IO_LOC, value "N7", to port pad_dqsn_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqsn_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqsn_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqsn_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqsn_ch0[0]
Adding property PAP_IO_DIRECTION, value "Inout", to port pad_dqsn_ch0[1]
Adding property PAP_IO_LOC, value "V8", to port pad_dqsn_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dqsn_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15D_I", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dqsn_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dqsn_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DDR_TERM_MODE, value "ON", to port pad_dqsn_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_LOC, value "R8", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dm_rdqs_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_LOC, value "U5", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_dm_rdqs_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[0]
Adding property PAP_IO_LOC, value "U2", to port pad_ba_ch0[0]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[0]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[0]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[0]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[0]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[0]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[1]
Adding property PAP_IO_LOC, value "U1", to port pad_ba_ch0[1]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[1]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[1]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[1]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[1]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[1]
Adding property PAP_IO_DIRECTION, value "Output", to port pad_ba_ch0[2]
Adding property PAP_IO_LOC, value "T2", to port pad_ba_ch0[2]
Adding property PAP_IO_VCCIO, value 1.5, to port pad_ba_ch0[2]
Adding property PAP_IO_STANDARD, value "SSTL15_I", to port pad_ba_ch0[2]
Adding property PAP_IO_DRIVE, value 7.5, to port pad_ba_ch0[2]
Adding property PAP_IO_UNUSED, value "TRUE", to port pad_ba_ch0[2]
Adding property PAP_IO_SLEW, value "FAST", to port pad_ba_ch0[2]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_p[0]
Adding property PAP_IO_LOC, value "B14", to port tmds_data_p[0]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_p[0]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_p[0]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_p[0]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_p[0]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_p[0]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_p[0]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_p[1]
Adding property PAP_IO_LOC, value "B11", to port tmds_data_p[1]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_p[1]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_p[1]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_p[1]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_p[1]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_p[1]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_p[1]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_p[2]
Adding property PAP_IO_LOC, value "B10", to port tmds_data_p[2]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_p[2]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_p[2]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_p[2]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_p[2]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_p[2]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_p[2]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_n[0]
Adding property PAP_IO_LOC, value "A14", to port tmds_data_n[0]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_n[0]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_n[0]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_n[0]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_n[0]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_n[0]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_n[0]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_n[1]
Adding property PAP_IO_LOC, value "A11", to port tmds_data_n[1]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_n[1]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_n[1]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_n[1]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_n[1]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_n[1]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_n[1]
Adding property PAP_IO_DIRECTION, value "Output", to port tmds_data_n[2]
Adding property PAP_IO_LOC, value "A10", to port tmds_data_n[2]
Adding property PAP_IO_VCCIO, value 3.3, to port tmds_data_n[2]
Adding property PAP_IO_STANDARD, value "LVTTL33", to port tmds_data_n[2]
Adding property PAP_IO_DRIVE, value 12, to port tmds_data_n[2]
Adding property PAP_IO_NONE, value "TRUE", to port tmds_data_n[2]
Adding property PAP_IO_SLEW, value "FAST", to port tmds_data_n[2]
Adding property PAP_IO_OPEN_DRAIN, value "OFF", to port tmds_data_n[2]

Encoding state machine state[4:0] (in view: work.bmp_read(verilog))
original code -> new code
   0000 -> 00001
   0001 -> 00010
   0010 -> 00100
   0011 -> 01000
   0100 -> 10000
Encoding state machine state[12:0] (in view: work.sd_card_sec_read_write_Z1(verilog))
original code -> new code
   00000 -> 0000000000001
   00001 -> 0000000000010
   00010 -> 0000000000100
   00011 -> 0000000001000
   00100 -> 0000000010000
   00101 -> 0000000100000
   00110 -> 0000001000000
   00111 -> 0000010000000
   01000 -> 0000100000000
   01111 -> 0001000000000
   10000 -> 0010000000000
   10001 -> 0100000000000
   10010 -> 1000000000000
Encoding state machine state[5:0] (in view: work.spi_master(verilog))
original code -> new code
   000 -> 000001
   001 -> 000010
   010 -> 000100
   011 -> 001000
   100 -> 010000
   101 -> 100000
Encoding state machine state[5:0] (in view: work.frame_fifo_write_Z4(verilog))
original code -> new code
   0000 -> 000001
   0001 -> 000010
   0010 -> 000100
   0011 -> 001000
   0100 -> 010000
   0101 -> 100000
Encoding state machine state[5:0] (in view: work.frame_fifo_read_Z7(verilog))
original code -> new code
   0000 -> 000001
   0001 -> 000010
   0010 -> 000100
   0011 -> 001000
   0100 -> 010000
   0101 -> 100000
Encoding state machine state[10:0] (in view: work.ipsl_ddrphy_reset_ctrl(verilog))
original code -> new code
   0000 -> 00000000001
   0001 -> 00000000010
   0010 -> 00000000100
   0011 -> 00000001000
   0100 -> 00000010000
   0101 -> 00000100000
   0110 -> 00001000000
   0111 -> 00010000000
   1000 -> 00100000000
   1001 -> 01000000000
   1010 -> 10000000000
Encoding state machine state[3:0] (in view: work.ipsl_ddrphy_dll_update_ctrl(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : ipsl_ddrphy_dll_update_ctrl.v(36) | There are no possible illegal states for state machine state[3:0] (in view: work.ipsl_ddrphy_dll_update_ctrl(verilog)); safe FSM implementation is not required.
Encoding state machine state[1:0] (in view: work.ipsl_ddrphy_update_ctrl_16BIT_2s_0s_1s_2s_3s_1(verilog))
original code -> new code
   00 -> 0
   10 -> 1
@N:MO225 : ipsl_ddrphy_update_ctrl.v(293) | There are no possible illegal states for state machine state[1:0] (in view: work.ipsl_ddrphy_update_ctrl_16BIT_2s_0s_1s_2s_3s_1(verilog)); safe FSM implementation is not required.
Encoding state machine wr_state[6:0] (in view: work.aq_axi_master(verilog))
original code -> new code
   000 -> 0000001
   001 -> 0000010
   010 -> 0000100
   011 -> 0001000
   100 -> 0010000
   101 -> 0100000
   110 -> 1000000
Encoding state machine rd_state[5:0] (in view: work.aq_axi_master(verilog))
original code -> new code
   000 -> 000001
   001 -> 000010
   010 -> 000100
   011 -> 001000
   100 -> 010000
   101 -> 100000

Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 229MB peak: 229MB)

@N:MF578 :  | Incompatible asynchronous control logic preventing generated clock conversion. 

Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 230MB peak: 230MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 230MB peak: 230MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 231MB peak: 231MB)


Finished netlist restructuring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 231MB peak: 231MB)



Clock Summary
******************

          Start                                                        Requested     Requested     Clock        Clock                    Clock
Level     Clock                                                        Frequency     Period        Type         Group                    Load 
----------------------------------------------------------------------------------------------------------------------------------------------
0 -       sys_clk                                                      50.0 MHz      20.000        declared     default_clkgroup         470  
                                                                                                                                              
0 -       System                                                       1.0 MHz       1000.000      system       system_clkgroup          2    
                                                                                                                                              
0 -       pll_50_400|clkout3_inferred_clock                            1.0 MHz       1000.000      inferred     Inferred_clkgroup_0      549  
                                                                                                                                              
0 -       video_pll|clkout0_inferred_clock                             1.0 MHz       1000.000      inferred     Inferred_clkgroup_71     245  
                                                                                                                                              
0 -       pll_50_400|clkout1_inferred_clock                            1.0 MHz       1000.000      inferred     Inferred_clkgroup_1      148  
                                                                                                                                              
0 -       video_pll|clkout1_inferred_clock                             1.0 MHz       1000.000      inferred     Inferred_clkgroup_72     59   
                                                                                                                                              
0 -       ipsl_phy_io_Z8|ioclk_01_inferred_clock                       1.0 MHz       1000.000      inferred     Inferred_clkgroup_4      19   
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_ca_clk_r_03_inferred_clock                1.0 MHz       1000.000      inferred     Inferred_clkgroup_49     12   
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_clkw_ca_03_inferred_clock                 1.0 MHz       1000.000      inferred     Inferred_clkgroup_51     12   
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs0_clk_r_inferred_clock                     1.0 MHz       1000.000      inferred     Inferred_clkgroup_10     10   
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs1_clk_r_inferred_clock                     1.0 MHz       1000.000      inferred     Inferred_clkgroup_37     10   
                                                                                                                                              
0 -       ipsl_ddrphy_dll_update_ctrl|dll_update_n_inferred_clock      1.0 MHz       1000.000      inferred     Inferred_clkgroup_70     9    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_ca_clk_r_01_inferred_clock                1.0 MHz       1000.000      inferred     Inferred_clkgroup_24     9    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_clkw290_0_inferred_clock                  1.0 MHz       1000.000      inferred     Inferred_clkgroup_12     9    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_clkw290_1_inferred_clock                  1.0 MHz       1000.000      inferred     Inferred_clkgroup_38     9    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_clkw_ca_01_inferred_clock                 1.0 MHz       1000.000      inferred     Inferred_clkgroup_26     9    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_90_0_inferred_clock                       1.0 MHz       1000.000      inferred     Inferred_clkgroup_14     8    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_90_1_inferred_clock                       1.0 MHz       1000.000      inferred     Inferred_clkgroup_36     8    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_ca_clk_r_04_inferred_clock                1.0 MHz       1000.000      inferred     Inferred_clkgroup_63     5    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_clkw_ca_04_inferred_clock                 1.0 MHz       1000.000      inferred     Inferred_clkgroup_65     5    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|IOCLK_DIV_inferred_clock                      1.0 MHz       1000.000      inferred     Inferred_clkgroup_2      2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[3]              1.0 MHz       1000.000      inferred     Inferred_clkgroup_13     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[4]              1.0 MHz       1000.000      inferred     Inferred_clkgroup_15     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[5]              1.0 MHz       1000.000      inferred     Inferred_clkgroup_16     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[6]              1.0 MHz       1000.000      inferred     Inferred_clkgroup_17     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[7]              1.0 MHz       1000.000      inferred     Inferred_clkgroup_18     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[10]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_21     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[11]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_22     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[12]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_23     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[27]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_35     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[28]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_39     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[29]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_40     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[32]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_43     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[33]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_44     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[34]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_45     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[35]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_46     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[36]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_47     2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|ioclk_02_inferred_clock                       1.0 MHz       1000.000      inferred     Inferred_clkgroup_8      2    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[2]              1.0 MHz       1000.000      inferred     Inferred_clkgroup_11     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[9]              1.0 MHz       1000.000      inferred     Inferred_clkgroup_19     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[17]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_25     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[18]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_27     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[19]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_28     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[20]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_29     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[21]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_30     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[22]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_31     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[23]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_32     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[24]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_33     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[25]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_34     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[31]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_41     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[37]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_48     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[40]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_50     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[41]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_52     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[42]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_53     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[43]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_54     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[44]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_55     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[45]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_56     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[46]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_57     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[47]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_58     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[48]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_59     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[49]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_60     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[51]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_61     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[52]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_62     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[55]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_64     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[56]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_66     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[57]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_67     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[58]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_68     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[59]             1.0 MHz       1000.000      inferred     Inferred_clkgroup_69     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[0]     1.0 MHz       1000.000      inferred     Inferred_clkgroup_3      1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[1]     1.0 MHz       1000.000      inferred     Inferred_clkgroup_5      1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[2]     1.0 MHz       1000.000      inferred     Inferred_clkgroup_6      1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[3]     1.0 MHz       1000.000      inferred     Inferred_clkgroup_7      1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[4]     1.0 MHz       1000.000      inferred     Inferred_clkgroup_9      1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_clkw_0_inferred_clock                     1.0 MHz       1000.000      inferred     Inferred_clkgroup_20     1    
                                                                                                                                              
0 -       ipsl_phy_io_Z8|dqs_clkw_1_inferred_clock                     1.0 MHz       1000.000      inferred     Inferred_clkgroup_42     1    
==============================================================================================================================================



Clock Load Summary
***********************

                                                             Clock     Source                                                                                             Clock Pin                                                                                                 Non-clock Pin                                                                   Non-clock Pin
Clock                                                        Load      Pin                                                                                                Seq Example                                                                                               Seq Example                                                                     Comb Example 
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
sys_clk                                                      470       sys_clk(port)                                                                                      frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wrptr2[8:0].C     -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
System                                                       2         -                                                                                                  u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc.ACLK_2                                                      -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
pll_50_400|clkout3_inferred_clock                            549       u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1.CLKOUT3(GTP_PLL_E1)                                         u_aq_axi_master.reg_r_last.C                                                                              -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
video_pll|clkout0_inferred_clock                             245       video_pll_m0.u_pll_e1.CLKOUT0(GTP_PLL_E1)                                                          frame_read_write_m0.read_buf.U_ipml_fifo_afifo_64i_32o_128.U_ipml_fifo_ctrl.ASYN_CTRL\.rwptr1[8:0].C      -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
pll_50_400|clkout1_inferred_clock                            148       u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1.CLKOUT1(GTP_PLL_E1)                                         u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc.PCLK                                                        -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
video_pll|clkout1_inferred_clock                             59        video_pll_m0.u_pll_e1.CLKOUT1(GTP_PLL_E1)                                                          dvi_encoder_m0.serdes_4b_10to1_m0.gtp_ogddr0.SERCLK                                                       -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|ioclk_01_inferred_clock                       19        u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclkbuf01_dut.CLKOUT(GTP_IOCLKBUF)            u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.CLKA                                         -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_ca_clk_r_03_inferred_clock                12        u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut.RCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr40_dut.SERCLK                                 -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_clkw_ca_03_inferred_clock                 12        u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut.WCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr40_dut.OCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs0_clk_r_inferred_clock                     10        u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.RCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr2_dut.SERCLK                                  -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs1_clk_r_inferred_clock                     10        u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.RCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr27_dut.SERCLK                                 -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_ddrphy_dll_update_ctrl|dll_update_n_inferred_clock      9         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_dll_update_ctrl.dll_update_n.Q[0](dffr)             u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.last_dll_step[7:0].C                           u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DLL_UPDATE_N     -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_ca_clk_r_01_inferred_clock                9         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut.RCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr17_dut.SERCLK                                 -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_clkw290_0_inferred_clock                  9         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.WCLK_DELAY(GTP_DDC_E1)                u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr2_dut.OCLK                                    -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_clkw290_1_inferred_clock                  9         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.WCLK_DELAY(GTP_DDC_E1)                u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr27_dut.OCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_clkw_ca_01_inferred_clock                 9         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut.WCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr17_dut.OCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_90_0_inferred_clock                       8         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.DQSI_DELAY(GTP_DDC_E1)                u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut.ICLK                                    -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_90_1_inferred_clock                       8         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.DQSI_DELAY(GTP_DDC_E1)                u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr27_dut.ICLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_ca_clk_r_04_inferred_clock                5         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut.RCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr55_dut.SERCLK                                 -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_clkw_ca_04_inferred_clock                 5         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut.WCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr55_dut.OCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|IOCLK_DIV_inferred_clock                      2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclkdiv_dut.CLKDIVOUT(GTP_IOCLKDIV)           u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc.CORE_DDRC_CORE_CLK                                          -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[3]              2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[3](GTP_DDRPHY)          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut.RCLK                                    -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[4]              2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[4](GTP_DDRPHY)          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr4_dut.RCLK                                    -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[5]              2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[5](GTP_DDRPHY)          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr5_dut.RCLK                                    -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[6]              2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[6](GTP_DDRPHY)          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr6_dut.RCLK                                    -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[7]              2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[7](GTP_DDRPHY)          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr7_dut.RCLK                                    -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[10]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[10](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr10_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[11]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[11](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr11_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[12]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[12](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr12_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[27]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[27](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr27_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[28]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[28](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr28_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[29]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[29](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr29_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[32]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[32](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr32_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[33]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[33](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr33_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[34]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[34](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr34_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[35]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[35](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr35_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[36]             2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[36](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr36_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|ioclk_02_inferred_clock                       2         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclkbuf02_dut.CLKOUT(GTP_IOCLKBUF)            u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut.CLKA                                         -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[2]              1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[2](GTP_DDRPHY)          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr2_dut.RCLK                                    -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[9]              1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[9](GTP_DDRPHY)          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr9_dut.RCLK                                    -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[17]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[17](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr17_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[18]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[18](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr18_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[19]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[19](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr19_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[20]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[20](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr20_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[21]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[21](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr21_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[22]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[22](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr22_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[23]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[23](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr23_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[24]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[24](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr24_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[25]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[25](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[31]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[31](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr31_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[37]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[37](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[40]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[40](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr40_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[41]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[41](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr41_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[42]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[42](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr42_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[43]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[43](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr43_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[44]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[44](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr44_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[45]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[45](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr45_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[46]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[46](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr46_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[47]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[47](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr47_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[48]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[48](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr48_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[49]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[49](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr49_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[51]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[51](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr51_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[52]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[52](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[55]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[55](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr55_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[56]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[56](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr56_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[57]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[57](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr57_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[58]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[58](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr58_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[59]             1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[59](GTP_DDRPHY)         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut.RCLK                                   -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[0]     1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[0](GTP_DDRPHY)     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.CLKB                                         -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[1]     1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[1](GTP_DDRPHY)     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut.CLKB                                         -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[2]     1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[2](GTP_DDRPHY)     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.CLKB                                         -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[3]     1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[3](GTP_DDRPHY)     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut.CLKB                                         -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[4]     1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[4](GTP_DDRPHY)     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut.CLKB                                         -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_clkw_0_inferred_clock                     1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.WCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr9_dut.OCLK                                    -                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                 
ipsl_phy_io_Z8|dqs_clkw_1_inferred_clock                     1         u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.WCLK(GTP_DDC_E1)                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr31_dut.OCLK                                   -                                                                               -            
=================================================================================================================================================================================================================================================================================================================================================================================

@W:MT531 : ipsl_hmemc_ddrc_top.v(337) | Found signal identified as System clock which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc.  Using this clock, which has no specified timing constraint, can prevent conversion of gated or generated clocks and can adversely impact design performance. 
@W:MT529 : ipml_sdpram_v1_3_afifo_32i_64o_256.v(825) | Found inferred clock pll_50_400|clkout3_inferred_clock which controls 549 sequential elements including frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_sdpram.ADDR_LOOP\[0\]\.DATA_LOOP\[1\]\.U_GTP_DRM18K. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_ddrphy_reset_ctrl.v(52) | Found inferred clock pll_50_400|clkout1_inferred_clock which controls 148 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_ddrphy_reset_ctrl.state[10]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(960) | Found inferred clock ipsl_phy_io_Z8|IOCLK_DIV_inferred_clock which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1134) | Found inferred clock ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[0] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1956) | Found inferred clock ipsl_phy_io_Z8|ioclk_01_inferred_clock which controls 19 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr36_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1171) | Found inferred clock ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[1] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1211) | Found inferred clock ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[2] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1248) | Found inferred clock ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[3] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1285) | Found inferred clock ipsl_phy_io_Z8|ioclk_02_inferred_clock which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1285) | Found inferred clock ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[4] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1597) | Found inferred clock ipsl_phy_io_Z8|dqs0_clk_r_inferred_clock which controls 10 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr12_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1332) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[2] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr2_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1597) | Found inferred clock ipsl_phy_io_Z8|dqs_clkw290_0_inferred_clock which controls 9 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr12_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1363) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[3] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr3_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1586) | Found inferred clock ipsl_phy_io_Z8|dqs_90_0_inferred_clock which controls 8 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr12_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1395) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[4] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr4_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1426) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[5] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr5_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1458) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[6] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr6_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1489) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[7] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr7_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1502) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[9] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr9_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1502) | Found inferred clock ipsl_phy_io_Z8|dqs_clkw_0_inferred_clock which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr9_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1534) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[10] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr10_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1565) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[11] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr11_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1597) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[12] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr12_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1700) | Found inferred clock ipsl_phy_io_Z8|dqs_ca_clk_r_01_inferred_clock which controls 9 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1609) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[17] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr17_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1700) | Found inferred clock ipsl_phy_io_Z8|dqs_clkw_ca_01_inferred_clock which controls 9 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1621) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[18] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr18_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1632) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[19] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr19_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1644) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[20] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr20_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1655) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[21] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr21_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1666) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[22] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr22_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1677) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[23] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr23_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1689) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[24] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr24_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1700) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[25] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1733) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[27] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr27_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1956) | Found inferred clock ipsl_phy_io_Z8|dqs_90_1_inferred_clock which controls 8 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr36_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1978) | Found inferred clock ipsl_phy_io_Z8|dqs1_clk_r_inferred_clock which controls 10 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1978) | Found inferred clock ipsl_phy_io_Z8|dqs_clkw290_1_inferred_clock which controls 9 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1765) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[28] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr28_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1796) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[29] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr29_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1809) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[31] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr31_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1809) | Found inferred clock ipsl_phy_io_Z8|dqs_clkw_1_inferred_clock which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr31_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1841) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[32] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr32_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1872) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[33] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr33_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1904) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[34] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr34_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1935) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[35] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr35_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1967) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[36] which controls 2 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr36_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1978) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[37] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(2126) | Found inferred clock ipsl_phy_io_Z8|dqs_ca_clk_r_03_inferred_clock which controls 12 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(1993) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[40] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr40_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(2126) | Found inferred clock ipsl_phy_io_Z8|dqs_clkw_ca_03_inferred_clock which controls 12 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(2006) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[41] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr41_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(2020) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[42] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr42_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(2031) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[43] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr43_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(2045) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[44] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr44_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(2056) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[45] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr45_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(2068) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[46] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr46_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(2078) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[47] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr47_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(2090) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[48] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr48_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(2101) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[49] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr49_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(2114) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[51] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr51_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(2126) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[52] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(2187) | Found inferred clock ipsl_phy_io_Z8|dqs_ca_clk_r_04_inferred_clock which controls 5 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(2140) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[55] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr55_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(2187) | Found inferred clock ipsl_phy_io_Z8|dqs_clkw_ca_04_inferred_clock which controls 5 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(2152) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[56] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr56_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(2162) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[57] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr57_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(2174) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[58] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr58_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_phy_io.v(2187) | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[59] which controls 1 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : ipsl_ddrphy_update_ctrl.v(54) | Found inferred clock ipsl_ddrphy_dll_update_ctrl|dll_update_n_inferred_clock which controls 9 sequential elements including u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.last_dll_step[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : encode.v(108) | Found inferred clock video_pll|clkout0_inferred_clock which controls 245 sequential elements including dvi_encoder_m0.encb.n0q_m[3:1]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : serdes_4b_10to1.v(48) | Found inferred clock video_pll|clkout1_inferred_clock which controls 59 sequential elements including dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[2:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 470 clock pin(s) of sequential element(s)
75 gated/generated clock tree(s) driving 1209 clock pin(s) of sequential element(s)
0 instances converted, 1209 sequential instances remain driven by gated/generated clocks

===================================== Non-Gated/Non-Generated Clocks ======================================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                    
-----------------------------------------------------------------------------------------------------------
ClockId_0_143     sys_clk             port                   470        sd_card_bmp_m0.bmp_read_m0.state[4]
===========================================================================================================
======================================================================================================================== Gated/Generated Clocks ========================================================================================================================
Clock Tree ID     Driving Element                                                                        Drive Element Type     Unconverted Fanout     Sample Instance                                                                   Explanation                    
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ClockId_0_0       u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1.CLKOUT3                                         GTP_PLL_E1             549                    u_aq_axi_master.rd_state[5]                                                       Black box on clock path        
ClockId_0_2       u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1.CLKOUT1                                         GTP_PLL_E1             148                    u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                                     Black box on clock path        
ClockId_0_3       u_ipsl_hmemc_top.aclk_0.O[0]                                                           variable               1                      u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                                     Black box on clock path        
ClockId_0_4       u_ipsl_hmemc_top.aclk_2.O[0]                                                           variable               1                      u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                                     Black box on clock path        
ClockId_0_6       u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclkdiv_dut.CLKDIVOUT             GTP_IOCLKDIV           2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut                    Black box on clock path        
ClockId_0_7       u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut.WCLK                      GTP_DDC_E1             5                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut                Clock source is invalid for GCC
ClockId_0_9       u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[59]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut                Clock source is invalid for GCC
ClockId_0_11      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut.RCLK                      GTP_DDC_E1             5                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr59_dut                Clock source is invalid for GCC
ClockId_0_13      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[58]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr58_dut                Clock source is invalid for GCC
ClockId_0_15      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[57]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr57_dut                Clock source is invalid for GCC
ClockId_0_17      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[56]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr56_dut                Clock source is invalid for GCC
ClockId_0_19      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[55]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr55_dut                Clock source is invalid for GCC
ClockId_0_21      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut.WCLK                      GTP_DDC_E1             12                     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut                Clock source is invalid for GCC
ClockId_0_23      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[52]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut                Clock source is invalid for GCC
ClockId_0_25      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut.RCLK                      GTP_DDC_E1             12                     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr52_dut                Clock source is invalid for GCC
ClockId_0_27      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[51]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr51_dut                Clock source is invalid for GCC
ClockId_0_29      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[49]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr49_dut                Clock source is invalid for GCC
ClockId_0_31      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[48]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr48_dut                Clock source is invalid for GCC
ClockId_0_33      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[47]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr47_dut                Clock source is invalid for GCC
ClockId_0_35      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[46]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr46_dut                Clock source is invalid for GCC
ClockId_0_37      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[45]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr45_dut                Clock source is invalid for GCC
ClockId_0_39      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[44]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr44_dut                Clock source is invalid for GCC
ClockId_0_41      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[43]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr43_dut                Clock source is invalid for GCC
ClockId_0_43      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[42]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr42_dut                Clock source is invalid for GCC
ClockId_0_45      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[41]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr41_dut                Clock source is invalid for GCC
ClockId_0_47      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[40]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr40_dut                Clock source is invalid for GCC
ClockId_0_49      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.WCLK_DELAY                GTP_DDC_E1             9                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut                Clock source is invalid for GCC
ClockId_0_51      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[37]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut                Clock source is invalid for GCC
ClockId_0_53      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.RCLK                      GTP_DDC_E1             10                     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr37_dut                Clock source is invalid for GCC
ClockId_0_55      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[36]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr36_dut                Clock source is invalid for GCC
ClockId_0_57      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclkbuf01_dut.CLKOUT              GTP_IOCLKBUF           19                     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr36_dut                Black box on clock path        
ClockId_0_58      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.DQSI_DELAY                GTP_DDC_E1             8                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr36_dut                Black box on clock path        
ClockId_0_60      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[35]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr35_dut                Clock source is invalid for GCC
ClockId_0_62      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[34]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr34_dut                Clock source is invalid for GCC
ClockId_0_64      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[33]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr33_dut                Clock source is invalid for GCC
ClockId_0_66      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[32]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr32_dut                Clock source is invalid for GCC
ClockId_0_68      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut.WCLK                      GTP_DDC_E1             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr31_dut                Clock source is invalid for GCC
ClockId_0_70      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[31]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr31_dut                Clock source is invalid for GCC
ClockId_0_72      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[29]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr29_dut                Clock source is invalid for GCC
ClockId_0_74      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[28]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr28_dut                Clock source is invalid for GCC
ClockId_0_76      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[27]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr27_dut                Clock source is invalid for GCC
ClockId_0_78      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut.WCLK                      GTP_DDC_E1             9                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut                Clock source is invalid for GCC
ClockId_0_80      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[25]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut                Clock source is invalid for GCC
ClockId_0_82      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut.RCLK                      GTP_DDC_E1             9                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr25_dut                Clock source is invalid for GCC
ClockId_0_84      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[24]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr24_dut                Clock source is invalid for GCC
ClockId_0_86      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[23]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr23_dut                Clock source is invalid for GCC
ClockId_0_88      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[22]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr22_dut                Clock source is invalid for GCC
ClockId_0_90      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[21]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr21_dut                Clock source is invalid for GCC
ClockId_0_92      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[20]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr20_dut                Clock source is invalid for GCC
ClockId_0_94      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[19]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr19_dut                Clock source is invalid for GCC
ClockId_0_96      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[18]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr18_dut                Clock source is invalid for GCC
ClockId_0_98      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[17]         GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr17_dut                Clock source is invalid for GCC
ClockId_0_100     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.WCLK_DELAY                GTP_DDC_E1             9                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr12_dut                Clock source is invalid for GCC
ClockId_0_102     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[12]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr12_dut                Clock source is invalid for GCC
ClockId_0_104     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.RCLK                      GTP_DDC_E1             10                     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr12_dut                Clock source is invalid for GCC
ClockId_0_106     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.DQSI_DELAY                GTP_DDC_E1             8                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr12_dut                Black box on clock path        
ClockId_0_108     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[11]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr11_dut                Clock source is invalid for GCC
ClockId_0_110     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[10]         GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr10_dut                Clock source is invalid for GCC
ClockId_0_112     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut.WCLK                      GTP_DDC_E1             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr9_dut                 Clock source is invalid for GCC
ClockId_0_114     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[9]          GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr9_dut                 Clock source is invalid for GCC
ClockId_0_116     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[7]          GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr7_dut                 Clock source is invalid for GCC
ClockId_0_118     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[6]          GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr6_dut                 Clock source is invalid for GCC
ClockId_0_120     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[5]          GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr5_dut                 Clock source is invalid for GCC
ClockId_0_122     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[4]          GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr4_dut                 Clock source is invalid for GCC
ClockId_0_124     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[3]          GTP_DDRPHY             2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr3_dut                 Clock source is invalid for GCC
ClockId_0_126     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.IOL_CLK_SYS[2]          GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_oddr2_dut                 Clock source is invalid for GCC
ClockId_0_128     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclkbuf02_dut.CLKOUT              GTP_IOCLKBUF           2                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut                      Black box on clock path        
ClockId_0_129     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[4]     GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs4_dut                      Black box on clock path        
ClockId_0_131     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[3]     GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs3_dut                      Black box on clock path        
ClockId_0_133     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[2]     GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut                      Black box on clock path        
ClockId_0_135     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[1]     GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_dut                      Black box on clock path        
ClockId_0_137     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut.DQS_CLK_REGIONAL[0]     GTP_DDRPHY             1                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut                      Black box on clock path        
ClockId_0_139     u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_dll_update_ctrl.dll_update_n.Q[0]       dffr                   8                      u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.last_dll_step[7:0]     Clock source is invalid for GCC
ClockId_0_142     video_pll_m0.u_pll_e1.CLKOUT0                                                          GTP_PLL_E1             245                    video_timing_data_m0.read_req                                                     Black box on clock path        
ClockId_0_144     video_pll_m0.u_pll_e1.CLKOUT1                                                          GTP_PLL_E1             59                     dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[2:0]                                  Black box on clock path        
========================================================================================================================================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.
@N:MO111 : ipsl_hmemc_top_test.v(42) | Tristate driver err_flag (in view: work.ipsl_hmemc_top_test(verilog)) on net err_flag (in view: work.ipsl_hmemc_top_test(verilog)) has its enable tied to GND.
@N:BN225 :  | Writing default property annotation file D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\synthesize\synplify_impl\synplify.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 232MB peak: 232MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 232MB peak: 232MB)


Finished constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 232MB peak: 232MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 152MB peak: 232MB)

Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Tue May  7 16:40:53 2019

###########################################################]

Map & Optimize Report

# Tue May  7 16:40:54 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03P-Beta2
Install: C:\pango\PDS_2019.1-patch2\syn
OS: Windows 6.1

Hostname: ALINX000007-PC

Implementation : synplify_impl
Synopsys Generic Technology Mapper, Version map2019q1p1, Build 1238R, Built Mar 15 2019 09:38:46


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 119MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 119MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 119MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 123MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 213MB peak: 213MB)

@N:MO111 :  | Tristate driver dqs_drift_l_t[0] (in view: work.ipsl_hmemc_phy_top_Z9(verilog)) on net dqs_drift_l[0] (in view: work.ipsl_hmemc_phy_top_Z9(verilog)) has its enable tied to GND. 
@N:MO111 :  | Tristate driver dqs_drift_l_t[1] (in view: work.ipsl_hmemc_phy_top_Z9(verilog)) on net dqs_drift_l[1] (in view: work.ipsl_hmemc_phy_top_Z9(verilog)) has its enable tied to GND. 
@N:MO111 :  | Tristate driver dqs_drift_h_t[0] (in view: work.ipsl_hmemc_phy_top_Z9(verilog)) on net dqs_drift_h[0] (in view: work.ipsl_hmemc_phy_top_Z9(verilog)) has its enable tied to GND. 
@N:MO111 :  | Tristate driver dqs_drift_h_t[1] (in view: work.ipsl_hmemc_phy_top_Z9(verilog)) on net dqs_drift_h[1] (in view: work.ipsl_hmemc_phy_top_Z9(verilog)) has its enable tied to GND. 
@N:MO111 : ipsl_hmemc_top_test.v(42) | Tristate driver err_flag (in view: work.ipsl_hmemc_top_test(verilog)) on net err_flag (in view: work.ipsl_hmemc_top_test(verilog)) has its enable tied to GND.
@W:BN132 : frame_fifo_write.v(81) | Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_d0[24:0] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.read_len_d0[24:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_write.v(81) | Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_d1[24:0] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[24:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.

Available hyper_sources - for debug and ip models
	None Found

@N:MT204 :  | Auto Constrain mode is disabled because clocks are defined in the SDC file 

            sys_clk


Finished RTL optimizations (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 222MB peak: 222MB)

@N:MO231 : aq_axi_master.v(170) | Found counter in view:work.ipsl_hmemc_top_test(verilog) instance u_aq_axi_master.reg_w_len[7:0] 
@N:MO231 : aq_axi_master.v(342) | Found counter in view:work.ipsl_hmemc_top_test(verilog) instance u_aq_axi_master.reg_r_len[7:0] 
@N:MO231 : aq_axi_master.v(150) | Found counter in view:work.ipsl_hmemc_top_test(verilog) instance u_aq_axi_master.rd_fifo_cnt[31:0] 
@N:MO231 : frame_fifo_read.v(107) | Found counter in view:work.ipsl_hmemc_top_test(verilog) instance frame_read_write_m0.frame_fifo_read_m0.read_cnt[24:6] 
@N:MO231 : frame_fifo_write.v(106) | Found counter in view:work.ipsl_hmemc_top_test(verilog) instance frame_read_write_m0.frame_fifo_write_m0.write_cnt[24:6] 
@N:BN362 : video_timing_data.v(83) | Removing sequential instance video_timing_data_m0.vout_data_r[24] (in view: work.ipsl_hmemc_top_test(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : video_timing_data.v(83) | Removing sequential instance video_timing_data_m0.vout_data_r[25] (in view: work.ipsl_hmemc_top_test(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : video_timing_data.v(83) | Removing sequential instance video_timing_data_m0.vout_data_r[26] (in view: work.ipsl_hmemc_top_test(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : video_timing_data.v(83) | Removing sequential instance video_timing_data_m0.vout_data_r[27] (in view: work.ipsl_hmemc_top_test(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : video_timing_data.v(83) | Removing sequential instance video_timing_data_m0.vout_data_r[28] (in view: work.ipsl_hmemc_top_test(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : video_timing_data.v(83) | Removing sequential instance video_timing_data_m0.vout_data_r[29] (in view: work.ipsl_hmemc_top_test(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : video_timing_data.v(83) | Removing sequential instance video_timing_data_m0.vout_data_r[30] (in view: work.ipsl_hmemc_top_test(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : video_timing_data.v(83) | Removing sequential instance video_timing_data_m0.vout_data_r[31] (in view: work.ipsl_hmemc_top_test(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@W:MO129 : frame_fifo_read.v(82) | Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[0] is reduced to a combinational gate by constant propagation.
@W:MO129 : frame_fifo_read.v(82) | Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[1] is reduced to a combinational gate by constant propagation.
@W:MO129 : frame_fifo_read.v(82) | Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[2] is reduced to a combinational gate by constant propagation.
@W:MO129 : frame_fifo_read.v(82) | Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[3] is reduced to a combinational gate by constant propagation.
@W:MO129 : frame_fifo_read.v(82) | Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[4] is reduced to a combinational gate by constant propagation.
@W:MO129 : frame_fifo_read.v(82) | Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[5] is reduced to a combinational gate by constant propagation.
@W:MO129 : frame_fifo_read.v(82) | Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[6] is reduced to a combinational gate by constant propagation.
@W:MO129 : frame_fifo_read.v(82) | Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[7] is reduced to a combinational gate by constant propagation.
@W:MO129 : frame_fifo_read.v(82) | Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[8] is reduced to a combinational gate by constant propagation.
@W:MO129 : frame_fifo_read.v(82) | Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[9] is reduced to a combinational gate by constant propagation.
@W:MO129 : frame_fifo_read.v(82) | Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[10] is reduced to a combinational gate by constant propagation.
@W:MO129 : frame_fifo_read.v(82) | Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[11] is reduced to a combinational gate by constant propagation.
@W:MO129 : frame_fifo_read.v(82) | Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[12] is reduced to a combinational gate by constant propagation.
@W:MO129 : frame_fifo_read.v(82) | Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[13] is reduced to a combinational gate by constant propagation.
@W:MO129 : frame_fifo_read.v(82) | Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[14] is reduced to a combinational gate by constant propagation.
@W:MO129 : frame_fifo_read.v(82) | Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[15] is reduced to a combinational gate by constant propagation.
@W:MO129 : frame_fifo_read.v(82) | Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[16] is reduced to a combinational gate by constant propagation.
@W:MO129 : frame_fifo_read.v(82) | Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[19] is reduced to a combinational gate by constant propagation.
@W:MO129 : frame_fifo_read.v(82) | Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[20] is reduced to a combinational gate by constant propagation.
@W:MO129 : frame_fifo_read.v(82) | Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[21] is reduced to a combinational gate by constant propagation.
@W:MO129 : frame_fifo_read.v(82) | Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[22] is reduced to a combinational gate by constant propagation.
@W:MO129 : frame_fifo_read.v(82) | Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[23] is reduced to a combinational gate by constant propagation.
@W:MO129 : frame_fifo_read.v(82) | Sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[24] is reduced to a combinational gate by constant propagation.
@N:MF179 : aq_axi_master.v(166) | Found 32 by 32 bit equality operator ('==') u_aq_axi_master.un1_rd_fifo_cnt_1 (in view: work.ipsl_hmemc_top_test(verilog))
@W:MO160 : frame_fifo_write.v(106) | Register bit frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[5] (in view view:work.ipsl_hmemc_top_test(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : frame_fifo_write.v(106) | Register bit frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[4] (in view view:work.ipsl_hmemc_top_test(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : frame_fifo_write.v(106) | Register bit frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[3] (in view view:work.ipsl_hmemc_top_test(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : frame_fifo_write.v(106) | Register bit frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[2] (in view view:work.ipsl_hmemc_top_test(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : frame_fifo_write.v(106) | Register bit frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[1] (in view view:work.ipsl_hmemc_top_test(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : frame_fifo_write.v(106) | Register bit frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[0] (in view view:work.ipsl_hmemc_top_test(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : frame_fifo_read.v(107) | Register bit frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[5] (in view view:work.ipsl_hmemc_top_test(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : frame_fifo_read.v(107) | Register bit frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[4] (in view view:work.ipsl_hmemc_top_test(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : frame_fifo_read.v(107) | Register bit frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[3] (in view view:work.ipsl_hmemc_top_test(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : frame_fifo_read.v(107) | Register bit frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[2] (in view view:work.ipsl_hmemc_top_test(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : frame_fifo_read.v(107) | Register bit frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[1] (in view view:work.ipsl_hmemc_top_test(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : frame_fifo_read.v(107) | Register bit frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[0] (in view view:work.ipsl_hmemc_top_test(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@N:BN362 : frame_fifo_read.v(107) | Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[0] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_read.v(107) | Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[1] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_read.v(107) | Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[2] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_read.v(107) | Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[3] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_read.v(107) | Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[4] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_read.v(107) | Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[5] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_read.v(107) | Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[6] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_read.v(107) | Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[7] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_read.v(107) | Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[8] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_read.v(107) | Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[9] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_read.v(107) | Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[10] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_read.v(107) | Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[11] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_read.v(107) | Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[12] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_read.v(107) | Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[13] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_read.v(107) | Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[14] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_read.v(107) | Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[15] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_read.v(107) | Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[16] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_read.v(107) | Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[19] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_read.v(107) | Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[20] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_read.v(107) | Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[21] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_read.v(107) | Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[22] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_read.v(107) | Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[23] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_read.v(107) | Removing sequential instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[24] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_write.v(106) | Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[0] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_write.v(106) | Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[1] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_write.v(106) | Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[2] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_write.v(106) | Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[3] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_write.v(106) | Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[4] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_write.v(106) | Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[5] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_write.v(106) | Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[6] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_write.v(106) | Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[7] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_write.v(106) | Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[8] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_write.v(106) | Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[9] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_write.v(106) | Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[10] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_write.v(106) | Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[11] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_write.v(106) | Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[12] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_write.v(106) | Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[13] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_write.v(106) | Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[14] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_write.v(106) | Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[15] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_write.v(106) | Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[16] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_write.v(106) | Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[19] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_write.v(106) | Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[20] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_write.v(106) | Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[21] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_write.v(106) | Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[22] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_write.v(106) | Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[23] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : frame_fifo_write.v(106) | Removing sequential instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[24] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@W:BN132 : frame_fifo_read.v(82) | Removing instance frame_read_write_m0.frame_fifo_read_m0.read_len_d0[18] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.read_len_d0[17]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_read.v(82) | Removing instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[18] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.read_len_d1[17]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_write.v(106) | Removing instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[18] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.write_len_latch[17]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_read.v(107) | Removing instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[18] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.read_len_latch[17]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N:MO231 : ax_debounce.v(73) | Found counter in view:work.ax_debounce(verilog) instance q_reg[31:0] 
@N:MO231 : bmp_read.v(143) | Found counter in view:work.bmp_read(verilog) instance bmp_len_cnt[31:0] 
@N:MO231 : bmp_read.v(85) | Found counter in view:work.bmp_read(verilog) instance rd_cnt[9:0] 
@W:BN132 : sd_card_sec_read_write.v(92) | Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[15] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : sd_card_sec_read_write.v(92) | Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[14] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : sd_card_sec_read_write.v(92) | Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[13] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : sd_card_sec_read_write.v(92) | Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[12] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : sd_card_sec_read_write.v(92) | Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[11] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : sd_card_sec_read_write.v(92) | Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[9] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : sd_card_sec_read_write.v(92) | Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[8] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : sd_card_sec_read_write.v(92) | Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[2] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : sd_card_sec_read_write.v(92) | Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[1] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : sd_card_sec_read_write.v(92) | Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[10] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : sd_card_sec_read_write.v(92) | Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[7] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : sd_card_sec_read_write.v(92) | Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[6] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : sd_card_sec_read_write.v(92) | Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[5] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : sd_card_sec_read_write.v(92) | Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[4] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_sec_read_write_m0.spi_clk_div[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N:BN362 : sd_card_sec_read_write.v(92) | Removing sequential instance sd_card_sec_read_write_m0.spi_clk_div[0] (in view: work.sd_card_top(verilog)) because it does not drive other instances.
@N:MO231 : sd_card_cmd.v(90) | Found counter in view:work.sd_card_cmd(verilog) instance byte_cnt[15:0] 
@N:MO231 : sd_card_cmd.v(90) | Found counter in view:work.sd_card_cmd(verilog) instance wr_data_cnt[9:0] 
@N:MF179 : sd_card_cmd.v(212) | Found 16 by 16 bit equality operator ('==') state56 (in view: work.sd_card_cmd(verilog))
@N:MO231 : spi_master.v(119) | Found counter in view:work.spi_master(verilog) instance clk_cnt[15:0] 
@N:MO231 : spi_master.v(129) | Found counter in view:work.spi_master(verilog) instance clk_edge_cnt[4:0] 
@N:MF179 : spi_master.v(82) | Found 16 by 16 bit equality operator ('==') next_state15 (in view: work.spi_master(verilog))
@N:BN362 : encode.v(151) | Removing sequential instance dout[0] (in view: work.encode_0_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : encode.v(151) | Removing sequential instance dout[1] (in view: work.encode_0_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : encode.v(135) | Removing sequential instance q_m_reg[0] (in view: work.encode_0_0(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
@N:BN362 : encode.v(135) | Removing sequential instance q_m_reg[1] (in view: work.encode_0_0(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
@W:BN132 : serdes_4b_10to1.v(48) | Removing instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_3l[4] because it is equivalent to instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_3h[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : serdes_4b_10to1.v(48) | Removing instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_3l[3] because it is equivalent to instance dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_3h[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N:MF179 :  | Found 9 by 9 bit equality operator ('==') ASYN_CTRL\.asyn_rempty_2 (in view: work.ipml_fifo_ctrl_v1_3_9s_8s_ASYN_508s_4s(verilog)) 
@N:MF179 : ipml_fifo_ctrl_v1_3.v(207) | Found 9 by 9 bit equality operator ('==') ASYN_CTRL\.un8_asyn_wfull (in view: work.ipml_fifo_ctrl_v1_3_9s_8s_ASYN_508s_4s(verilog))
@N:MF179 :  | Found 10 by 10 bit equality operator ('==') ASYN_CTRL\.asyn_rempty_5 (in view: work.ipml_fifo_ctrl_v1_3_8s_9s_ASYN_252s_4s(verilog)) 
@N:MO231 : ipsl_ddrphy_reset_ctrl.v(52) | Found counter in view:work.ipsl_ddrphy_reset_ctrl(verilog) instance cnt[7:0] 
@W:BN132 : ipsl_ddrphy_update_ctrl.v(293) | Removing instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.ddrphy_update_comp_val_l[1] because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.ddrphy_update_comp_val_h[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N:MO231 : ipsl_ddrphy_update_ctrl.v(121) | Found counter in view:work.ipsl_ddrphy_update_ctrl_16BIT_2s_0s_1s_2s_3s_1(verilog) instance dqs_drift_h_cnt[7:0] 
@N:MO231 : ipsl_ddrphy_update_ctrl.v(102) | Found counter in view:work.ipsl_ddrphy_update_ctrl_16BIT_2s_0s_1s_2s_3s_1(verilog) instance dqs_drift_l_cnt[7:0] 
@N:BN362 : ipsl_ddrphy_update_ctrl.v(293) | Removing sequential instance ddrphy_update_comp_val_h[1] (in view: work.ipsl_ddrphy_update_ctrl_16BIT_2s_0s_1s_2s_3s_1(verilog)) because it does not drive other instances.
@N:MO231 : ipsl_ddrc_reset_ctrl.v(113) | Found counter in view:work.ipsl_hmemc_ddrc_top_Z12(verilog) instance u_ipsl_ddrc_reset_ctrl.ddrc_rst_cnt[4:0] 
@N:MO231 : ipsl_ddrc_reset_ctrl.v(86) | Found counter in view:work.ipsl_hmemc_ddrc_top_Z12(verilog) instance u_ipsl_ddrc_reset_ctrl.rst_cnt[4:0] 
@N:MO231 : ipsl_ddrc_apb_reset.v(387) | Found counter in view:work.ipsl_ddrc_apb_reset_Z10(verilog) instance cnt[6:0] 

Starting factoring (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:06s; Memory used current: 227MB peak: 227MB)

@W:BN132 : sd_card_cmd.v(90) | Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[15] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : sd_card_cmd.v(90) | Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[14] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : sd_card_cmd.v(90) | Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[13] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : sd_card_cmd.v(90) | Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[12] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : sd_card_cmd.v(90) | Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[11] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : sd_card_cmd.v(90) | Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[9] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : sd_card_cmd.v(90) | Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[8] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : sd_card_cmd.v(90) | Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[2] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : sd_card_cmd.v(90) | Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[1] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : sd_card_cmd.v(90) | Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[10] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : sd_card_cmd.v(90) | Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[7] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : sd_card_cmd.v(90) | Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[6] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : sd_card_cmd.v(90) | Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[5] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : sd_card_cmd.v(90) | Removing instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[4] because it is equivalent to instance sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.clk_div[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N:BN362 : sd_card_cmd.v(90) | Removing sequential instance sd_card_top_m0.sd_card_cmd_m0.clk_div[0] (in view: work.sd_card_bmp(verilog)) because it does not drive other instances.
@W:BN132 : ipsl_ddrphy_update_ctrl.v(121) | Removing instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_h_d1[1] because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_h_d1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : ipsl_ddrphy_update_ctrl.v(102) | Removing instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_l_d1[1] because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_h_d1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : ipsl_ddrphy_update_ctrl.v(102) | Removing instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_l_d1[0] because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_h_d1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : ipsl_ddrphy_update_ctrl.v(121) | Removing instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_h_now[1] because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_h_now[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : ipsl_ddrphy_update_ctrl.v(102) | Removing instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_l_now[1] because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_l_now[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : ipsl_ddrphy_update_ctrl.v(293) | Removing instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_h_last[1] because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_h_last[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : ipsl_ddrphy_update_ctrl.v(293) | Removing instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_l_last[1] because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dqs_drift_l_last[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : ipsl_ddrphy_update_ctrl.v(293) | Removing instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.ddrphy_update_comp_dir_l because it is equivalent to instance u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.ddrphy_update_comp_dir_h. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N:BN362 : ipsl_ddrphy_update_ctrl.v(121) | Removing sequential instance u_ddrphy_update_ctrl.dqs_drift_h_d1[0] (in view: work.ipsl_hmemc_phy_top_Z9(verilog)) because it does not drive other instances.
@W:BN132 : encode.v(135) | Removing instance dvi_encoder_m0.encr.de_q because it is equivalent to instance dvi_encoder_m0.encg.de_q. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : encode.v(135) | Removing instance dvi_encoder_m0.encg.de_q because it is equivalent to instance dvi_encoder_m0.encb.de_q. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : encode.v(135) | Removing instance dvi_encoder_m0.encr.de_reg because it is equivalent to instance dvi_encoder_m0.encg.de_reg. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : encode.v(135) | Removing instance dvi_encoder_m0.encg.de_reg because it is equivalent to instance dvi_encoder_m0.encb.de_reg. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N:BN362 : ipml_fifo_ctrl_v1_3.v(370) | Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rd_water_level[0] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : ipml_fifo_ctrl_v1_3.v(370) | Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rd_water_level[1] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : ipml_fifo_ctrl_v1_3.v(370) | Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rd_water_level[2] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : ipml_fifo_ctrl_v1_3.v(370) | Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rd_water_level[3] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : ipml_fifo_ctrl_v1_3.v(370) | Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rd_water_level[4] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : ipml_fifo_ctrl_v1_3.v(370) | Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rd_water_level[5] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : ipml_fifo_ctrl_v1_3.v(349) | Removing sequential instance frame_read_write_m0.read_buf.U_ipml_fifo_afifo_64i_32o_128.U_ipml_fifo_ctrl.wr_water_level[0] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : ipml_fifo_ctrl_v1_3.v(349) | Removing sequential instance frame_read_write_m0.read_buf.U_ipml_fifo_afifo_64i_32o_128.U_ipml_fifo_ctrl.wr_water_level[1] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : ipml_fifo_ctrl_v1_3.v(349) | Removing sequential instance frame_read_write_m0.read_buf.U_ipml_fifo_afifo_64i_32o_128.U_ipml_fifo_ctrl.wr_water_level[2] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : ipml_fifo_ctrl_v1_3.v(349) | Removing sequential instance frame_read_write_m0.read_buf.U_ipml_fifo_afifo_64i_32o_128.U_ipml_fifo_ctrl.wr_water_level[3] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : ipml_fifo_ctrl_v1_3.v(349) | Removing sequential instance frame_read_write_m0.read_buf.U_ipml_fifo_afifo_64i_32o_128.U_ipml_fifo_ctrl.wr_water_level[4] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : ipml_fifo_ctrl_v1_3.v(349) | Removing sequential instance frame_read_write_m0.read_buf.U_ipml_fifo_afifo_64i_32o_128.U_ipml_fifo_ctrl.wr_water_level[5] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
Auto Dissolve of u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top (inst of view:work.ipsl_hmemc_phy_top_Z9(verilog))

Finished factoring (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:06s; Memory used current: 238MB peak: 238MB)

@N:BN362 : ipml_fifo_ctrl_v1_3.v(106) | Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0_0[1] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : ipml_fifo_ctrl_v1_3.v(106) | Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0_0[2] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : ipml_fifo_ctrl_v1_3.v(106) | Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0_0[3] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : ipml_fifo_ctrl_v1_3.v(106) | Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0_0[4] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : ipml_fifo_ctrl_v1_3.v(106) | Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0_0[5] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : ipml_fifo_ctrl_v1_3.v(106) | Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0_0[6] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : ipml_fifo_ctrl_v1_3.v(106) | Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0_0[7] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : ipml_fifo_ctrl_v1_3.v(106) | Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0_0[8] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : ipml_fifo_ctrl_v1_3.v(106) | Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0_0[9] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : ipml_fifo_ctrl_v1_3.v(106) | Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0[1] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : ipml_fifo_ctrl_v1_3.v(106) | Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0[2] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : ipml_fifo_ctrl_v1_3.v(106) | Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0[3] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : ipml_fifo_ctrl_v1_3.v(106) | Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0[4] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : ipml_fifo_ctrl_v1_3.v(106) | Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0[5] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : ipml_fifo_ctrl_v1_3.v(106) | Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0[6] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : ipml_fifo_ctrl_v1_3.v(106) | Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0[7] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : ipml_fifo_ctrl_v1_3.v(106) | Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0[8] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : ipml_fifo_ctrl_v1_3.v(106) | Removing sequential instance frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin_0[9] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : color_bar.v(205) | Removing sequential instance video_timing_data_m0.color_bar_m0.h_cnt_0[6] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : color_bar.v(205) | Removing sequential instance video_timing_data_m0.color_bar_m0.h_cnt_0[7] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : color_bar.v(205) | Removing sequential instance video_timing_data_m0.color_bar_m0.h_cnt_0[8] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : color_bar.v(205) | Removing sequential instance video_timing_data_m0.color_bar_m0.h_cnt_0[9] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : color_bar.v(205) | Removing sequential instance video_timing_data_m0.color_bar_m0.h_cnt_0[10] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : color_bar.v(205) | Removing sequential instance video_timing_data_m0.color_bar_m0.h_cnt_0[11] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : color_bar.v(205) | Removing sequential instance video_timing_data_m0.color_bar_m0.h_cnt_1[6] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.
@N:BN362 : color_bar.v(205) | Removing sequential instance video_timing_data_m0.color_bar_m0.h_cnt_1[7] (in view: work.ipsl_hmemc_top_test(verilog)) because it does not drive other instances.

Only the first 100 messages of id 'BN362' are reported. To see all messages use 'report_messages -log D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\synthesize\synplify_impl\synlog\synplify_fpga_mapper.srr -id BN362' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {BN362} -count unlimited' in the Tcl shell.

Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:10s; Memory used current: 373MB peak: 373MB)

@W:BN132 : frame_fifo_read.v(107) | Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[0] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_read.v(107) | Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[1] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_read.v(107) | Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[2] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_read.v(107) | Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[3] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_read.v(107) | Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[4] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_read.v(107) | Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[5] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_read.v(107) | Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[6] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_read.v(107) | Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[7] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_read.v(107) | Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[8] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_read.v(107) | Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[9] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[9]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_read.v(107) | Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[10] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_read.v(107) | Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[11] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_read.v(107) | Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[12] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_read.v(107) | Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[13] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_read.v(107) | Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[14] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_read.v(107) | Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[15] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_read.v(107) | Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[16] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[16]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_read.v(107) | Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[17] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[17]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_read.v(107) | Removing instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr_0[18] because it is equivalent to instance frame_read_write_m0.frame_fifo_read_m0.rd_burst_addr[18]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_write.v(106) | Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[0] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_write.v(106) | Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[1] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_write.v(106) | Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[2] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_write.v(106) | Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[3] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_write.v(106) | Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[4] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_write.v(106) | Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[5] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_write.v(106) | Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[6] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_write.v(106) | Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[7] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_write.v(106) | Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[8] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_write.v(106) | Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[9] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[9]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_write.v(106) | Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[10] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_write.v(106) | Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[11] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_write.v(106) | Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[12] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_write.v(106) | Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[13] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_write.v(106) | Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[14] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_write.v(106) | Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[15] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_write.v(106) | Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[16] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[16]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_write.v(106) | Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[17] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[17]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : frame_fifo_write.v(106) | Removing instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr_0[18] because it is equivalent to instance frame_read_write_m0.frame_fifo_write_m0.wr_burst_addr[18]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : bmp_read.v(202) | Removing instance sd_card_bmp_m0.bmp_read_m0.sd_sec_read_addr_0[0] because it is equivalent to instance sd_card_bmp_m0.bmp_read_m0.sd_sec_read_addr[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : bmp_read.v(202) | Removing instance sd_card_bmp_m0.bmp_read_m0.sd_sec_read_addr_0[1] because it is equivalent to instance sd_card_bmp_m0.bmp_read_m0.sd_sec_read_addr[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : bmp_read.v(202) | Removing instance sd_card_bmp_m0.bmp_read_m0.sd_sec_read_addr_0[2] because it is equivalent to instance sd_card_bmp_m0.bmp_read_m0.sd_sec_read_addr[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : color_bar.v(225) | Removing instance video_timing_data_m0.color_bar_m0.v_cnt_0[1] because it is equivalent to instance video_timing_data_m0.color_bar_m0.v_cnt[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : color_bar.v(225) | Removing instance video_timing_data_m0.color_bar_m0.v_cnt_0[2] because it is equivalent to instance video_timing_data_m0.color_bar_m0.v_cnt[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : color_bar.v(225) | Removing instance video_timing_data_m0.color_bar_m0.v_cnt_0[5] because it is equivalent to instance video_timing_data_m0.color_bar_m0.v_cnt[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : color_bar.v(225) | Removing instance video_timing_data_m0.color_bar_m0.v_cnt_0[8] because it is equivalent to instance video_timing_data_m0.color_bar_m0.v_cnt[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : color_bar.v(225) | Removing instance video_timing_data_m0.color_bar_m0.v_cnt_0[9] because it is equivalent to instance video_timing_data_m0.color_bar_m0.v_cnt[9]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : aq_axi_master.v(342) | Removing instance u_aq_axi_master.reg_rd_adrs_0[0] because it is equivalent to instance u_aq_axi_master.reg_rd_adrs[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : aq_axi_master.v(342) | Removing instance u_aq_axi_master.reg_rd_adrs_0[1] because it is equivalent to instance u_aq_axi_master.reg_rd_adrs[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : aq_axi_master.v(342) | Removing instance u_aq_axi_master.reg_rd_adrs_0[2] because it is equivalent to instance u_aq_axi_master.reg_rd_adrs[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : aq_axi_master.v(342) | Removing instance u_aq_axi_master.reg_rd_adrs_0[3] because it is equivalent to instance u_aq_axi_master.reg_rd_adrs[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : aq_axi_master.v(342) | Removing instance u_aq_axi_master.reg_rd_adrs_0[4] because it is equivalent to instance u_aq_axi_master.reg_rd_adrs[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.

Only the first 100 messages of id 'BN132' are reported. To see all messages use 'report_messages -log D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\synthesize\synplify_impl\synlog\synplify_fpga_mapper.srr -id BN132' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {BN132} -count unlimited' in the Tcl shell.

Starting Early Timing Optimization (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:11s; Memory used current: 373MB peak: 373MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:12s; Memory used current: 373MB peak: 374MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:13s; Memory used current: 373MB peak: 374MB)

@W:FX553 : ipsl_ddrc_apb_reset.v(115) | Could not implement Block ROM for u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.data_2[43:3].
@N:FX214 : ipsl_ddrc_apb_reset.v(115) | Generating ROM u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.data_2[43:3] (in view: work.ipsl_hmemc_ddrc_top_Z12(verilog)).

Finished preparing to map (Real Time elapsed 0h:00m:19s; CPU Time elapsed 0h:00m:15s; Memory used current: 374MB peak: 374MB)


Finished technology mapping (Real Time elapsed 0h:00m:20s; CPU Time elapsed 0h:00m:16s; Memory used current: 421MB peak: 421MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:16s		    13.14ns		1952 /      1168

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:21s; CPU Time elapsed 0h:00m:17s; Memory used current: 421MB peak: 421MB)

@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   

Finished restoring hierarchy (Real Time elapsed 0h:00m:30s; CPU Time elapsed 0h:00m:23s; Memory used current: 422MB peak: 422MB)


Start Writing Netlists (Real Time elapsed 0h:00m:31s; CPU Time elapsed 0h:00m:24s; Memory used current: 349MB peak: 423MB)

Writing Analyst data base D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\synthesize\synplify_impl\synwork\synplify_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:40s; CPU Time elapsed 0h:00m:31s; Memory used current: 436MB peak: 436MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:42s; CPU Time elapsed 0h:00m:33s; Memory used current: 460MB peak: 460MB)

@N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:43s; CPU Time elapsed 0h:00m:33s; Memory used current: 460MB peak: 460MB)


Start final timing analysis (Real Time elapsed 0h:00m:43s; CPU Time elapsed 0h:00m:34s; Memory used current: 418MB peak: 460MB)

@N:MT615 :  | Found clock sys_clk with period 20.00ns  
@W:MT420 :  | Found inferred clock pll_50_400|clkout3_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_pll_50_400.ui_clk[0]. 
@W:MT420 :  | Found inferred clock pll_50_400|clkout1_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_pll_50_400.pll_pclk. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|IOCLK_DIV_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrc_core_clk. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[0] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_dqs_clk_regional[0]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|ioclk_01_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclk_01. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[1] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_dqs_clk_regional[1]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[2] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_dqs_clk_regional[2]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[3] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_dqs_clk_regional[3]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|ioclk_02_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclk_02. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[4] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_dqs_clk_regional[4]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|dqs0_clk_r_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_clk_r. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[2] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[2]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|dqs_clkw290_0_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw290_0. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[3] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[3]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|dqs_90_0_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_90_0. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[4] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[4]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[5] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[5]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[6] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[6]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[7] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[7]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[9] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[9]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|dqs_clkw_0_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw_0. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[10] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[10]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[11] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[11]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[12] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[12]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|dqs_ca_clk_r_01_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_ca_clk_r_01. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[17] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[17]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|dqs_clkw_ca_01_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw_ca_01. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[18] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[18]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[19] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[19]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[20] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[20]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[21] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[21]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[22] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[22]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[23] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[23]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[24] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[24]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[25] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[25]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[27] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[27]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|dqs_90_1_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_90_1. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|dqs1_clk_r_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs1_clk_r. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|dqs_clkw290_1_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw290_1. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[28] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[28]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[29] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[29]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[31] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[31]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|dqs_clkw_1_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw_1. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[32] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[32]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[33] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[33]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[34] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[34]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[35] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[35]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[36] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[36]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[37] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[37]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|dqs_ca_clk_r_03_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_ca_clk_r_03. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[40] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[40]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|dqs_clkw_ca_03_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw_ca_03. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[41] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[41]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[42] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[42]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[43] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[43]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[44] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[44]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[45] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[45]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[46] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[46]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[47] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[47]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[48] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[48]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[49] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[49]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[51] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[51]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[52] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[52]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|dqs_ca_clk_r_04_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_ca_clk_r_04. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[55] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[55]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|dqs_clkw_ca_04_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs_clkw_ca_04. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[56] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[56]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[57] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[57]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[58] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[58]. 
@W:MT420 :  | Found inferred clock ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[59] with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.buffer_clk_sys[59]. 
@W:MT420 :  | Found inferred clock ipsl_ddrphy_dll_update_ctrl|dll_update_n_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_dll_update_ctrl.dll_update_n[0]. 
@W:MT420 :  | Found inferred clock video_pll|clkout0_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net video_pll_m0.video_clk[0]. 
@W:MT420 :  | Found inferred clock video_pll|clkout1_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net video_pll_m0.video_clk5x. 


##### START OF TIMING REPORT #####[
# Timing report written on Tue May  7 16:41:38 2019
#


Top view:               ipsl_hmemc_top_test
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        3
Constraint File(s):    D:\example_ziguang\sd_picture_hdmi _ddrtest\ipcore\ddr3\pnr\ctrl_phy_22\ddr_324_left.fdc
                       
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: 14.934

                                                             Requested     Estimated      Requested     Estimated                 Clock        Clock               
Starting Clock                                               Frequency     Frequency      Period        Period        Slack       Type         Group               
-------------------------------------------------------------------------------------------------------------------------------------------------------------------
ipsl_ddrphy_dll_update_ctrl|dll_update_n_inferred_clock      1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_70
ipsl_phy_io_Z8|IOCLK_DIV_inferred_clock                      1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_2 
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[2]              1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_11
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[3]              1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_13
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[4]              1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_15
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[5]              1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_16
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[6]              1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_17
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[7]              1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_18
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[9]              1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_19
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[10]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_21
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[11]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_22
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[12]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_23
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[17]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_25
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[18]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_27
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[19]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_28
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[20]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_29
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[21]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_30
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[22]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_31
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[23]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_32
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[24]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_33
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[25]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_34
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[27]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_35
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[28]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_39
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[29]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_40
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[31]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_41
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[32]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_43
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[33]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_44
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[34]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_45
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[35]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_46
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[36]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_47
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[37]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_48
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[40]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_50
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[41]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_52
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[42]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_53
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[43]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_54
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[44]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_55
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[45]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_56
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[46]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_57
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[47]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_58
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[48]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_59
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[49]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_60
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[51]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_61
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[52]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_62
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[55]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_64
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[56]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_66
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[57]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_67
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[58]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_68
ipsl_phy_io_Z8|buffer_clk_sys_inferred_clock[59]             1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_69
ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[0]     1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_3 
ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[1]     1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_5 
ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[2]     1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_6 
ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[3]     1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_7 
ipsl_phy_io_Z8|buffer_dqs_clk_regional_inferred_clock[4]     1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_9 
ipsl_phy_io_Z8|dqs0_clk_r_inferred_clock                     1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_10
ipsl_phy_io_Z8|dqs1_clk_r_inferred_clock                     1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_37
ipsl_phy_io_Z8|dqs_90_0_inferred_clock                       1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_14
ipsl_phy_io_Z8|dqs_90_1_inferred_clock                       1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_36
ipsl_phy_io_Z8|dqs_ca_clk_r_01_inferred_clock                1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_24
ipsl_phy_io_Z8|dqs_ca_clk_r_03_inferred_clock                1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_49
ipsl_phy_io_Z8|dqs_ca_clk_r_04_inferred_clock                1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_63
ipsl_phy_io_Z8|dqs_clkw290_0_inferred_clock                  1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_12
ipsl_phy_io_Z8|dqs_clkw290_1_inferred_clock                  1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_38
ipsl_phy_io_Z8|dqs_clkw_0_inferred_clock                     1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_20
ipsl_phy_io_Z8|dqs_clkw_1_inferred_clock                     1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_42
ipsl_phy_io_Z8|dqs_clkw_ca_01_inferred_clock                 1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_26
ipsl_phy_io_Z8|dqs_clkw_ca_03_inferred_clock                 1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_51
ipsl_phy_io_Z8|dqs_clkw_ca_04_inferred_clock                 1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_65
ipsl_phy_io_Z8|ioclk_01_inferred_clock                       1.0 MHz       1008.1 MHz     1000.000      0.992         999.008     inferred     Inferred_clkgroup_4 
ipsl_phy_io_Z8|ioclk_02_inferred_clock                       1.0 MHz       NA             1000.000      NA            NA          inferred     Inferred_clkgroup_8 
pll_50_400|clkout1_inferred_clock                            1.0 MHz       120.6 MHz      1000.000      8.294         991.706     inferred     Inferred_clkgroup_1 
pll_50_400|clkout3_inferred_clock                            1.0 MHz       150.7 MHz      1000.000      6.636         993.364     inferred     Inferred_clkgroup_0 
sys_clk                                                      50.0 MHz      197.4 MHz      20.000        5.066         14.934      declared     default_clkgroup    
video_pll|clkout0_inferred_clock                             1.0 MHz       179.2 MHz      1000.000      5.580         994.419     inferred     Inferred_clkgroup_71
video_pll|clkout1_inferred_clock                             1.0 MHz       734.4 MHz      1000.000      1.362         998.638     inferred     Inferred_clkgroup_72
System                                                       1.0 MHz       780.5 MHz      1000.000      1.281         998.719     system       system_clkgroup     
===================================================================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform





Clock Relationships
*******************

Clocks                                                                                                            |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                                 Ending                                                   |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                                   System                                                   |  1000.000    998.719  |  No paths    -      |  No paths    -      |  No paths    -    
System                                                   pll_50_400|clkout1_inferred_clock                        |  1000.000    999.731  |  No paths    -      |  No paths    -      |  No paths    -    
System                                                   ipsl_ddrphy_dll_update_ctrl|dll_update_n_inferred_clock  |  1000.000    999.731  |  No paths    -      |  No paths    -      |  No paths    -    
sys_clk                                                  sys_clk                                                  |  20.000      14.934   |  No paths    -      |  No paths    -      |  No paths    -    
sys_clk                                                  pll_50_400|clkout3_inferred_clock                        |  Diff grp    -        |  No paths    -      |  No paths    -      |  No paths    -    
pll_50_400|clkout3_inferred_clock                        sys_clk                                                  |  Diff grp    -        |  No paths    -      |  No paths    -      |  No paths    -    
pll_50_400|clkout3_inferred_clock                        pll_50_400|clkout3_inferred_clock                        |  1000.000    993.364  |  No paths    -      |  No paths    -      |  No paths    -    
pll_50_400|clkout3_inferred_clock                        video_pll|clkout0_inferred_clock                         |  Diff grp    -        |  No paths    -      |  No paths    -      |  No paths    -    
pll_50_400|clkout1_inferred_clock                        System                                                   |  1000.000    999.133  |  No paths    -      |  No paths    -      |  No paths    -    
pll_50_400|clkout1_inferred_clock                        pll_50_400|clkout1_inferred_clock                        |  1000.000    991.706  |  No paths    -      |  No paths    -      |  No paths    -    
pll_50_400|clkout1_inferred_clock                        ipsl_phy_io_Z8|IOCLK_DIV_inferred_clock                  |  Diff grp    -        |  No paths    -      |  No paths    -      |  No paths    -    
ipsl_phy_io_Z8|IOCLK_DIV_inferred_clock                  pll_50_400|clkout1_inferred_clock                        |  Diff grp    -        |  No paths    -      |  No paths    -      |  No paths    -    
ipsl_phy_io_Z8|ioclk_01_inferred_clock                   ipsl_phy_io_Z8|ioclk_01_inferred_clock                   |  1000.000    999.008  |  No paths    -      |  No paths    -      |  No paths    -    
ipsl_ddrphy_dll_update_ctrl|dll_update_n_inferred_clock  pll_50_400|clkout1_inferred_clock                        |  Diff grp    -        |  No paths    -      |  No paths    -      |  No paths    -    
video_pll|clkout0_inferred_clock                         pll_50_400|clkout3_inferred_clock                        |  Diff grp    -        |  No paths    -      |  No paths    -      |  No paths    -    
video_pll|clkout0_inferred_clock                         video_pll|clkout0_inferred_clock                         |  1000.000    994.420  |  No paths    -      |  No paths    -      |  No paths    -    
video_pll|clkout0_inferred_clock                         video_pll|clkout1_inferred_clock                         |  Diff grp    -        |  No paths    -      |  No paths    -      |  No paths    -    
video_pll|clkout1_inferred_clock                         video_pll|clkout1_inferred_clock                         |  1000.000    998.638  |  No paths    -      |  No paths    -      |  No paths    -    
==========================================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: ipsl_phy_io_Z8|ioclk_01_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                                 Starting                                                                                               Arrival            
Instance                                                         Reference                                  Type           Pin                Net                       Time        Slack  
                                                                 Clock                                                                                                                     
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut     ipsl_phy_io_Z8|ioclk_01_inferred_clock     GTP_DDC_E1     IFIFO_RADDR[0]     dqs_ififo_rpoint_0[0]     0.464       999.008
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut     ipsl_phy_io_Z8|ioclk_01_inferred_clock     GTP_DDC_E1     IFIFO_RADDR[1]     dqs_ififo_rpoint_0[1]     0.464       999.008
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut     ipsl_phy_io_Z8|ioclk_01_inferred_clock     GTP_DDC_E1     IFIFO_RADDR[2]     dqs_ififo_rpoint_0[2]     0.464       999.008
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut     ipsl_phy_io_Z8|ioclk_01_inferred_clock     GTP_DDC_E1     IFIFO_RADDR[0]     dqs_ififo_rpoint_1[0]     0.464       999.008
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut     ipsl_phy_io_Z8|ioclk_01_inferred_clock     GTP_DDC_E1     IFIFO_RADDR[1]     dqs_ififo_rpoint_1[1]     0.464       999.008
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs2_dut     ipsl_phy_io_Z8|ioclk_01_inferred_clock     GTP_DDC_E1     IFIFO_RADDR[2]     dqs_ififo_rpoint_1[2]     0.464       999.008
===========================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                      Starting                                                                                          Required            
Instance                                                              Reference                                  Type            Pin          Net                       Time         Slack  
                                                                      Clock                                                                                                                 
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut     ipsl_phy_io_Z8|ioclk_01_inferred_clock     GTP_ISERDES     RADDR[0]     dqs_ififo_rpoint_0[0]     999.880      999.008
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut     ipsl_phy_io_Z8|ioclk_01_inferred_clock     GTP_ISERDES     RADDR[1]     dqs_ififo_rpoint_0[1]     999.880      999.008
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut     ipsl_phy_io_Z8|ioclk_01_inferred_clock     GTP_ISERDES     RADDR[2]     dqs_ififo_rpoint_0[2]     999.880      999.008
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr4_dut     ipsl_phy_io_Z8|ioclk_01_inferred_clock     GTP_ISERDES     RADDR[0]     dqs_ififo_rpoint_0[0]     999.880      999.008
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr4_dut     ipsl_phy_io_Z8|ioclk_01_inferred_clock     GTP_ISERDES     RADDR[1]     dqs_ififo_rpoint_0[1]     999.880      999.008
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr4_dut     ipsl_phy_io_Z8|ioclk_01_inferred_clock     GTP_ISERDES     RADDR[2]     dqs_ififo_rpoint_0[2]     999.880      999.008
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr5_dut     ipsl_phy_io_Z8|ioclk_01_inferred_clock     GTP_ISERDES     RADDR[0]     dqs_ififo_rpoint_0[0]     999.880      999.008
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr5_dut     ipsl_phy_io_Z8|ioclk_01_inferred_clock     GTP_ISERDES     RADDR[1]     dqs_ififo_rpoint_0[1]     999.880      999.008
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr5_dut     ipsl_phy_io_Z8|ioclk_01_inferred_clock     GTP_ISERDES     RADDR[2]     dqs_ififo_rpoint_0[2]     999.880      999.008
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr6_dut     ipsl_phy_io_Z8|ioclk_01_inferred_clock     GTP_ISERDES     RADDR[0]     dqs_ififo_rpoint_0[0]     999.880      999.008
============================================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      1000.000
    - Setup time:                            0.120
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         999.880

    - Propagation time:                      0.872
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 999.008

    Number of logic level(s):                0
    Starting point:                          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut / IFIFO_RADDR[0]
    Ending point:                            u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut / RADDR[0]
    The start point is clocked by            ipsl_phy_io_Z8|ioclk_01_inferred_clock [rising] on pin CLKA
    The end   point is clocked by            ipsl_phy_io_Z8|ioclk_01_inferred_clock [rising] on pin DESCLK

Instance / Net                                                                        Pin                Pin               Arrival     No. of    
Name                                                                  Type            Name               Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut          GTP_DDC_E1      IFIFO_RADDR[0]     Out     0.464     0.464       -         
dqs_ififo_rpoint_0[0]                                                 Net             -                  -       0.408     -           8         
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut     GTP_ISERDES     RADDR[0]           In      -         0.872       -         
=================================================================================================================================================
Total path delay (propagation time + setup) of 0.992 is 0.584(58.9%) logic and 0.408(41.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      1000.000
    - Setup time:                            0.120
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         999.880

    - Propagation time:                      0.872
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 999.008

    Number of logic level(s):                0
    Starting point:                          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut / IFIFO_RADDR[1]
    Ending point:                            u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut / RADDR[1]
    The start point is clocked by            ipsl_phy_io_Z8|ioclk_01_inferred_clock [rising] on pin CLKA
    The end   point is clocked by            ipsl_phy_io_Z8|ioclk_01_inferred_clock [rising] on pin DESCLK

Instance / Net                                                                        Pin                Pin               Arrival     No. of    
Name                                                                  Type            Name               Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut          GTP_DDC_E1      IFIFO_RADDR[1]     Out     0.464     0.464       -         
dqs_ififo_rpoint_0[1]                                                 Net             -                  -       0.408     -           8         
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut     GTP_ISERDES     RADDR[1]           In      -         0.872       -         
=================================================================================================================================================
Total path delay (propagation time + setup) of 0.992 is 0.584(58.9%) logic and 0.408(41.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      1000.000
    - Setup time:                            0.120
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         999.880

    - Propagation time:                      0.872
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 999.008

    Number of logic level(s):                0
    Starting point:                          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut / IFIFO_RADDR[2]
    Ending point:                            u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut / RADDR[2]
    The start point is clocked by            ipsl_phy_io_Z8|ioclk_01_inferred_clock [rising] on pin CLKA
    The end   point is clocked by            ipsl_phy_io_Z8|ioclk_01_inferred_clock [rising] on pin DESCLK

Instance / Net                                                                        Pin                Pin               Arrival     No. of    
Name                                                                  Type            Name               Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dqs0_dut          GTP_DDC_E1      IFIFO_RADDR[2]     Out     0.464     0.464       -         
dqs_ififo_rpoint_0[2]                                                 Net             -                  -       0.408     -           8         
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.iol_iddr3_dut     GTP_ISERDES     RADDR[2]           In      -         0.872       -         
=================================================================================================================================================
Total path delay (propagation time + setup) of 0.992 is 0.584(58.9%) logic and 0.408(41.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: pll_50_400|clkout1_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                                                                Starting                                                                         Arrival            
Instance                                                                                        Reference                             Type           Pin     Net                 Time        Slack  
                                                                                                Clock                                                                                               
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[1]      pll_50_400|clkout1_inferred_clock     GTP_DFF_CE     Q       cnt[1]              0.290       991.706
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[0]      pll_50_400|clkout1_inferred_clock     GTP_DFF_CE     Q       cnt[0]              0.290       991.754
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[4]      pll_50_400|clkout1_inferred_clock     GTP_DFF_CE     Q       cnt[4]              0.290       992.061
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[5]      pll_50_400|clkout1_inferred_clock     GTP_DFF_CE     Q       cnt[5]              0.290       992.084
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[3]      pll_50_400|clkout1_inferred_clock     GTP_DFF_CE     Q       cnt[3]              0.290       992.191
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[2]      pll_50_400|clkout1_inferred_clock     GTP_DFF_CE     Q       cnt[2]              0.290       992.239
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[6]      pll_50_400|clkout1_inferred_clock     GTP_DFF_CE     Q       cnt[6]              0.290       993.840
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.ddrc_init_start                   pll_50_400|clkout1_inferred_clock     GTP_DFF_PE     Q       ddrc_init_start     0.290       995.070
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.psel        pll_50_400|clkout1_inferred_clock     GTP_DFF_C      Q       init_psel           0.290       995.277
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.penable     pll_50_400|clkout1_inferred_clock     GTP_DFF_C      Q       init_penable        0.290       995.709
====================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                   Starting                                                                            Required            
Instance                                                           Reference                             Type           Pin          Net               Time         Slack  
                                                                   Clock                                                                                                   
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut     pll_50_400|clkout1_inferred_clock     GTP_DDRPHY     PWRITE       ddrc_pwrite       996.782      991.706
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                      pll_50_400|clkout1_inferred_clock     GTP_DDRC       PWRITE       ddrc_pwrite       996.782      991.706
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut     pll_50_400|clkout1_inferred_clock     GTP_DDRPHY     PADDR[2]     ddrc_paddr[2]     998.089      992.784
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                      pll_50_400|clkout1_inferred_clock     GTP_DDRC       PADDR[2]     ddrc_paddr[2]     998.089      992.784
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut     pll_50_400|clkout1_inferred_clock     GTP_DDRPHY     PADDR[7]     ddrc_paddr[7]     997.967      992.835
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                      pll_50_400|clkout1_inferred_clock     GTP_DDRC       PADDR[7]     ddrc_paddr[7]     997.967      992.835
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut     pll_50_400|clkout1_inferred_clock     GTP_DDRPHY     PADDR[9]     ddrc_paddr[9]     998.195      992.889
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                      pll_50_400|clkout1_inferred_clock     GTP_DDRC       PADDR[9]     ddrc_paddr[9]     998.195      992.889
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut     pll_50_400|clkout1_inferred_clock     GTP_DDRPHY     PADDR[5]     ddrc_paddr[5]     998.127      992.891
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                      pll_50_400|clkout1_inferred_clock     GTP_DDRC       PADDR[5]     ddrc_paddr[5]     998.127      992.891
===========================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      1000.000
    - Setup time:                            3.218
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         996.782

    - Propagation time:                      5.077
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 991.706

    Number of logic level(s):                3
    Starting point:                          u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[1] / Q
    Ending point:                            u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut / PWRITE
    The start point is clocked by            pll_50_400|clkout1_inferred_clock [rising] on pin CLK
    The end   point is clocked by            pll_50_400|clkout1_inferred_clock [rising] on pin PCLK

Instance / Net                                                                                                        Pin        Pin               Arrival     No. of    
Name                                                                                                   Type           Name       Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[1]             GTP_DFF_CE     Q          Out     0.290     0.290       -         
cnt[1]                                                                                                 Net            -          -       2.773     -           81        
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.un2_pwrite_0_0     GTP_LUT3       I1         In      -         3.063       -         
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.un2_pwrite_0_0     GTP_LUT3       Z          Out     0.306     3.369       -         
un2_pwrite_0_0                                                                                         Net            -          -       0.269     -           1         
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.un2_pwrite         GTP_LUT5       I4         In      -         3.638       -         
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.un2_pwrite         GTP_LUT5       Z          Out     0.176     3.813       -         
un2_pwrite                                                                                             Net            -          -       0.798     -           48        
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.ddrc_pwrite                              GTP_LUT2       I1         In      -         4.612       -         
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.ddrc_pwrite                              GTP_LUT2       Z          Out     0.176     4.788       -         
ddrc_pwrite                                                                                            Net            -          -       0.289     -           2         
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut                                         GTP_DDRPHY     PWRITE     In      -         5.077       -         
=========================================================================================================================================================================
Total path delay (propagation time + setup) of 8.294 is 4.166(50.2%) logic and 4.128(49.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      1000.000
    - Setup time:                            3.218
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         996.782

    - Propagation time:                      5.077
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 991.706

    Number of logic level(s):                3
    Starting point:                          u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[1] / Q
    Ending point:                            u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc / PWRITE
    The start point is clocked by            pll_50_400|clkout1_inferred_clock [rising] on pin CLK
    The end   point is clocked by            pll_50_400|clkout1_inferred_clock [rising] on pin PCLK

Instance / Net                                                                                                        Pin        Pin               Arrival     No. of    
Name                                                                                                   Type           Name       Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[1]             GTP_DFF_CE     Q          Out     0.290     0.290       -         
cnt[1]                                                                                                 Net            -          -       2.773     -           81        
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.un2_pwrite_0_0     GTP_LUT3       I1         In      -         3.063       -         
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.un2_pwrite_0_0     GTP_LUT3       Z          Out     0.306     3.369       -         
un2_pwrite_0_0                                                                                         Net            -          -       0.269     -           1         
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.un2_pwrite         GTP_LUT5       I4         In      -         3.638       -         
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.un2_pwrite         GTP_LUT5       Z          Out     0.176     3.813       -         
un2_pwrite                                                                                             Net            -          -       0.798     -           48        
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.ddrc_pwrite                              GTP_LUT2       I1         In      -         4.612       -         
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.ddrc_pwrite                              GTP_LUT2       Z          Out     0.176     4.788       -         
ddrc_pwrite                                                                                            Net            -          -       0.289     -           2         
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                                                          GTP_DDRC       PWRITE     In      -         5.077       -         
=========================================================================================================================================================================
Total path delay (propagation time + setup) of 8.294 is 4.166(50.2%) logic and 4.128(49.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      1000.000
    - Setup time:                            3.218
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         996.782

    - Propagation time:                      5.028
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 991.754

    Number of logic level(s):                3
    Starting point:                          u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[0] / Q
    Ending point:                            u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut / PWRITE
    The start point is clocked by            pll_50_400|clkout1_inferred_clock [rising] on pin CLK
    The end   point is clocked by            pll_50_400|clkout1_inferred_clock [rising] on pin PCLK

Instance / Net                                                                                                        Pin        Pin               Arrival     No. of    
Name                                                                                                   Type           Name       Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.cnt[0]             GTP_DFF_CE     Q          Out     0.290     0.290       -         
cnt[0]                                                                                                 Net            -          -       2.780     -           82        
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.un2_pwrite_0_0     GTP_LUT3       I0         In      -         3.070       -         
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.un2_pwrite_0_0     GTP_LUT3       Z          Out     0.251     3.321       -         
un2_pwrite_0_0                                                                                         Net            -          -       0.269     -           1         
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.un2_pwrite         GTP_LUT5       I4         In      -         3.589       -         
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.u_ipsl_ddrc_apb_reset.un2_pwrite         GTP_LUT5       Z          Out     0.176     3.765       -         
un2_pwrite                                                                                             Net            -          -       0.798     -           48        
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.ddrc_pwrite                              GTP_LUT2       I1         In      -         4.564       -         
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ipsl_ddrc_reset_ctrl.ddrc_pwrite                              GTP_LUT2       Z          Out     0.176     4.740       -         
ddrc_pwrite                                                                                            Net            -          -       0.289     -           2         
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ddrphy_dut                                         GTP_DDRPHY     PWRITE     In      -         5.028       -         
=========================================================================================================================================================================
Total path delay (propagation time + setup) of 8.246 is 4.111(49.9%) logic and 4.135(50.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: pll_50_400|clkout3_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                                                                    Starting                                                                             Arrival            
Instance                                                                                            Reference                             Type          Pin          Net                 Time        Slack  
                                                                                                    Clock                                                                                                   
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                                                       pll_50_400|clkout3_inferred_clock     GTP_DDRC      WREADY_1     wready_1            0.968       993.364
u_aq_axi_master.reg_wvalid                                                                          pll_50_400|clkout3_inferred_clock     GTP_DFF_C     Q            s00_axi_wvalid      0.290       993.828
u_aq_axi_master.rd_fifo_enable                                                                      pll_50_400|clkout3_inferred_clock     GTP_DFF_C     Q            rd_fifo_enable      0.290       993.897
u_aq_axi_master.rd_first_data                                                                       pll_50_400|clkout3_inferred_clock     GTP_DFF_C     Q            rd_first_data       0.290       994.137
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                                                       pll_50_400|clkout3_inferred_clock     GTP_DDRC      RVALID_1     rvalid_1            0.784       994.506
u_aq_axi_master.reg_arvalid                                                                         pll_50_400|clkout3_inferred_clock     GTP_DFF_C     Q            s00_axi_arvalid     0.290       994.853
u_aq_axi_master.reg_awvalid                                                                         pll_50_400|clkout3_inferred_clock     GTP_DFF_C     Q            s00_axi_awvalid     0.290       994.864
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.rbin[0]     pll_50_400|clkout3_inferred_clock     GTP_DFF_C     Q            rd_addr[0]          0.290       995.086
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.rbin[1]     pll_50_400|clkout3_inferred_clock     GTP_DFF_C     Q            rd_addr[1]          0.290       995.120
frame_read_write_m0.read_buf.U_ipml_fifo_afifo_64i_32o_128.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin[0]      pll_50_400|clkout3_inferred_clock     GTP_DFF_C     Q            wr_addr[0]          0.290       995.132
============================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                                        Starting                                                                                      Required            
Instance                                                                                                Reference                             Type           Pin     Net                              Time         Slack  
                                                                                                        Clock                                                                                                             
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty     pll_50_400|clkout3_inferred_clock     GTP_DFF_P      D       asyn_rempty_2_NE_i_0             1000.020     993.364
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rd_water_level[8]          pll_50_400|clkout3_inferred_clock     GTP_DFF_C      D       un1_rd_water_level_2_s_8_Z       1000.023     994.241
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rd_water_level[7]          pll_50_400|clkout3_inferred_clock     GTP_DFF_C      D       un1_rd_water_level_2_cry_7_Z     1000.023     994.275
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rd_water_level[6]          pll_50_400|clkout3_inferred_clock     GTP_DFF_C      D       un1_rd_water_level_2_cry_6_Z     1000.023     994.309
frame_read_write_m0.read_buf.U_ipml_fifo_afifo_64i_32o_128.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_wfull       pll_50_400|clkout3_inferred_clock     GTP_DFF_C      D       asyn_wfull_5                     1000.020     994.506
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.rptr[7]         pll_50_400|clkout3_inferred_clock     GTP_DFF_C      D       N_47_i                           1000.023     994.570
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.rptr[6]         pll_50_400|clkout3_inferred_clock     GTP_DFF_C      D       N_48_i                           1000.023     994.604
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.rptr[5]         pll_50_400|clkout3_inferred_clock     GTP_DFF_C      D       N_49_i                           1000.023     994.638
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.rptr[4]         pll_50_400|clkout3_inferred_clock     GTP_DFF_C      D       N_50_i                           1000.023     994.672
u_aq_axi_master.rd_fifo_cnt[0]                                                                          pll_50_400|clkout3_inferred_clock     GTP_DFF_CE     CE      rd_fifo_cnte                     999.645      994.675
==========================================================================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      1000.000
    - Setup time:                            -0.020
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1000.020

    - Propagation time:                      6.656
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 993.364

    Number of logic level(s):                14
    Starting point:                          u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc / WREADY_1
    Ending point:                            frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty / D
    The start point is clocked by            pll_50_400|clkout3_inferred_clock [rising] on pin ACLK_1
    The end   point is clocked by            pll_50_400|clkout3_inferred_clock [rising] on pin CLK

Instance / Net                                                                                                                       Pin          Pin               Arrival     No. of    
Name                                                                                                               Type              Name         Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                                                                      GTP_DDRC          WREADY_1     Out     0.968     0.968       -         
wready_1                                                                                                           Net               -            -       0.308     -           3         
u_aq_axi_master.rd_fifo_cntlde_0_o2                                                                                GTP_LUT4          I0           In      -         1.276       -         
u_aq_axi_master.rd_fifo_cntlde_0_o2                                                                                GTP_LUT4          Z            Out     0.251     1.527       -         
wr_burst_data_req                                                                                                  Net               -            -       2.511     -           37        
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_0_cy                       GTP_LUT5CARRY     I3           In      -         4.038       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_0_cy                       GTP_LUT5CARRY     COUT         Out     0.346     4.384       -         
rbnext_cry_0_cy                                                                                                    Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_0                          GTP_LUT5CARRY     CIN          In      -         4.384       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_0                          GTP_LUT5CARRY     COUT         Out     0.034     4.418       -         
rbnext_cry_0                                                                                                       Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_1                          GTP_LUT5CARRY     CIN          In      -         4.418       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_1                          GTP_LUT5CARRY     COUT         Out     0.034     4.452       -         
rbnext_cry_1                                                                                                       Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_2                          GTP_LUT5CARRY     CIN          In      -         4.452       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_2                          GTP_LUT5CARRY     COUT         Out     0.034     4.486       -         
rbnext_cry_2                                                                                                       Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_3                          GTP_LUT5CARRY     CIN          In      -         4.486       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_3                          GTP_LUT5CARRY     COUT         Out     0.034     4.520       -         
rbnext_cry_3                                                                                                       Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_4                          GTP_LUT5CARRY     CIN          In      -         4.520       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_4                          GTP_LUT5CARRY     COUT         Out     0.034     4.554       -         
rbnext_cry_4                                                                                                       Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_5                          GTP_LUT5CARRY     CIN          In      -         4.554       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_5                          GTP_LUT5CARRY     COUT         Out     0.034     4.588       -         
rbnext_cry_5                                                                                                       Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_6                          GTP_LUT5CARRY     CIN          In      -         4.588       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_6                          GTP_LUT5CARRY     COUT         Out     0.034     4.622       -         
rbnext_cry_6                                                                                                       Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_7                          GTP_LUT5CARRY     CIN          In      -         4.622       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_7                          GTP_LUT5CARRY     COUT         Out     0.034     4.656       -         
rbnext_cry_7                                                                                                       Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_s_8                            GTP_LUT5CARRY     CIN          In      -         4.656       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_s_8                            GTP_LUT5CARRY     Z            Out     0.232     4.888       -         
rbnext[8]                                                                                                          Net               -            -       0.328     -           4         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty_2_8_i_1_x2     GTP_LUT2          I1           In      -         5.216       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty_2_8_i_1_x2     GTP_LUT2          Z            Out     0.176     5.392       -         
dsp_join_kb_42[8]                                                                                                  Net               -            -       0.269     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty_2_NE_0_1       GTP_LUT5          I1           In      -         5.661       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty_2_NE_0_1       GTP_LUT5          Z            Out     0.306     5.967       -         
asyn_rempty_2_NE_0_1                                                                                               Net               -            -       0.269     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty_2_NE_i         GTP_LUT5          I3           In      -         6.236       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty_2_NE_i         GTP_LUT5          Z            Out     0.420     6.656       -         
asyn_rempty_2_NE_i_0                                                                                               Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty                GTP_DFF_P         D            In      -         6.656       -         
==========================================================================================================================================================================================
Total path delay (propagation time + setup) of 6.636 is 2.951(44.5%) logic and 3.685(55.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      1000.000
    - Setup time:                            -0.023
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1000.023

    - Propagation time:                      6.316
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 993.707

    Number of logic level(s):                10
    Starting point:                          u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc / WREADY_1
    Ending point:                            frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty / D
    The start point is clocked by            pll_50_400|clkout3_inferred_clock [rising] on pin ACLK_1
    The end   point is clocked by            pll_50_400|clkout3_inferred_clock [rising] on pin CLK

Instance / Net                                                                                                                          Pin          Pin               Arrival     No. of    
Name                                                                                                                  Type              Name         Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                                                                         GTP_DDRC          WREADY_1     Out     0.968     0.968       -         
wready_1                                                                                                              Net               -            -       0.308     -           3         
u_aq_axi_master.rd_fifo_cntlde_0_o2                                                                                   GTP_LUT4          I0           In      -         1.276       -         
u_aq_axi_master.rd_fifo_cntlde_0_o2                                                                                   GTP_LUT4          Z            Out     0.251     1.527       -         
wr_burst_data_req                                                                                                     Net               -            -       2.511     -           37        
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_0_cy                          GTP_LUT5CARRY     I3           In      -         4.038       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_0_cy                          GTP_LUT5CARRY     COUT         Out     0.346     4.384       -         
rbnext_cry_0_cy                                                                                                       Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_0                             GTP_LUT5CARRY     CIN          In      -         4.384       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_0                             GTP_LUT5CARRY     COUT         Out     0.034     4.418       -         
rbnext_cry_0                                                                                                          Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_1                             GTP_LUT5CARRY     CIN          In      -         4.418       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_1                             GTP_LUT5CARRY     COUT         Out     0.034     4.452       -         
rbnext_cry_1                                                                                                          Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_2                             GTP_LUT5CARRY     CIN          In      -         4.452       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_2                             GTP_LUT5CARRY     COUT         Out     0.034     4.486       -         
rbnext_cry_2                                                                                                          Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_3                             GTP_LUT5CARRY     CIN          In      -         4.486       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_3                             GTP_LUT5CARRY     COUT         Out     0.034     4.520       -         
rbnext_cry_3                                                                                                          Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_4                             GTP_LUT5CARRY     CIN          In      -         4.520       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_4                             GTP_LUT5CARRY     Z            Out     0.232     4.752       -         
N_148                                                                                                                 Net               -            -       0.348     -           5         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty_2_4_0_a3_0_x2     GTP_LUT3          I0           In      -         5.100       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty_2_4_0_a3_0_x2     GTP_LUT3          Z            Out     0.251     5.351       -         
N_62_i                                                                                                                Net               -            -       0.269     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty_2_NE_1            GTP_LUT5          I0           In      -         5.620       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty_2_NE_1            GTP_LUT5          Z            Out     0.251     5.871       -         
asyn_rempty_2_NE_1                                                                                                    Net               -            -       0.269     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty_2_NE_i            GTP_LUT5          I4           In      -         6.139       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty_2_NE_i            GTP_LUT5          Z            Out     0.176     6.316       -         
asyn_rempty_2_NE_i_0                                                                                                  Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty                   GTP_DFF_P         D            In      -         6.316       -         
=============================================================================================================================================================================================
Total path delay (propagation time + setup) of 6.292 is 2.588(41.1%) logic and 3.705(58.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      1000.000
    - Setup time:                            -0.020
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1000.020

    - Propagation time:                      6.277
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 993.743

    Number of logic level(s):                11
    Starting point:                          u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc / WREADY_1
    Ending point:                            frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty / D
    The start point is clocked by            pll_50_400|clkout3_inferred_clock [rising] on pin ACLK_1
    The end   point is clocked by            pll_50_400|clkout3_inferred_clock [rising] on pin CLK

Instance / Net                                                                                                                     Pin          Pin               Arrival     No. of    
Name                                                                                                             Type              Name         Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_ddrc_top.u_ddrc                                                                    GTP_DDRC          WREADY_1     Out     0.968     0.968       -         
wready_1                                                                                                         Net               -            -       0.308     -           3         
u_aq_axi_master.rd_fifo_cntlde_0_o2                                                                              GTP_LUT4          I0           In      -         1.276       -         
u_aq_axi_master.rd_fifo_cntlde_0_o2                                                                              GTP_LUT4          Z            Out     0.251     1.527       -         
wr_burst_data_req                                                                                                Net               -            -       2.511     -           37        
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_0_cy                     GTP_LUT5CARRY     I3           In      -         4.038       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_0_cy                     GTP_LUT5CARRY     COUT         Out     0.346     4.384       -         
rbnext_cry_0_cy                                                                                                  Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_0                        GTP_LUT5CARRY     CIN          In      -         4.384       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_0                        GTP_LUT5CARRY     COUT         Out     0.034     4.418       -         
rbnext_cry_0                                                                                                     Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_1                        GTP_LUT5CARRY     CIN          In      -         4.418       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_1                        GTP_LUT5CARRY     COUT         Out     0.034     4.452       -         
rbnext_cry_1                                                                                                     Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_2                        GTP_LUT5CARRY     CIN          In      -         4.452       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_2                        GTP_LUT5CARRY     COUT         Out     0.034     4.486       -         
rbnext_cry_2                                                                                                     Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_3                        GTP_LUT5CARRY     CIN          In      -         4.486       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_3                        GTP_LUT5CARRY     COUT         Out     0.034     4.520       -         
rbnext_cry_3                                                                                                     Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_4                        GTP_LUT5CARRY     CIN          In      -         4.520       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_4                        GTP_LUT5CARRY     COUT         Out     0.034     4.554       -         
rbnext_cry_4                                                                                                     Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_5                        GTP_LUT5CARRY     CIN          In      -         4.554       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_5                        GTP_LUT5CARRY     COUT         Out     0.034     4.588       -         
rbnext_cry_5                                                                                                     Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_6                        GTP_LUT5CARRY     CIN          In      -         4.588       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.rbnext_cry_6                        GTP_LUT5CARRY     Z            Out     0.232     4.820       -         
rbnext[6]                                                                                                        Net               -            -       0.348     -           5         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty_2_NE_0_1     GTP_LUT5          I3           In      -         5.168       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty_2_NE_0_1     GTP_LUT5          Z            Out     0.420     5.588       -         
asyn_rempty_2_NE_0_1                                                                                             Net               -            -       0.269     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty_2_NE_i       GTP_LUT5          I3           In      -         5.857       -         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty_2_NE_i       GTP_LUT5          Z            Out     0.420     6.277       -         
asyn_rempty_2_NE_i_0                                                                                             Net               -            -       0.000     -           1         
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_rempty              GTP_DFF_P         D            In      -         6.277       -         
========================================================================================================================================================================================
Total path delay (propagation time + setup) of 6.257 is 2.821(45.1%) logic and 3.436(54.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: sys_clk
====================================



Starting Points with Worst Slack
********************************

                                                                                                    Starting                                                   Arrival           
Instance                                                                                            Reference     Type           Pin     Net                   Time        Slack 
                                                                                                    Clock                                                                        
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[1]                                               sys_clk       GTP_DFF_CE     Q       state[1]              0.290       14.934
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[0]                                               sys_clk       GTP_DFF_CE     Q       state[0]              0.290       15.032
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[4]                                               sys_clk       GTP_DFF_CE     Q       state[4]              0.290       15.127
sd_card_bmp_m0.sd_card_top_m0.spi_master_m0.MISO_shift[1]                                           sys_clk       GTP_DFF_CE     Q       spi_data_out[1]       0.290       15.147
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin[0]     sys_clk       GTP_DFF_C      Q       dsp_join_kb_40[0]     0.290       15.157
sd_card_bmp_m0.sd_card_top_m0.spi_master_m0.MISO_shift[2]                                           sys_clk       GTP_DFF_CE     Q       spi_data_out[2]       0.290       15.162
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.byte_cnt[14]                                           sys_clk       GTP_DFF_CE     Q       byte_cnt[14]          0.290       15.221
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin[1]     sys_clk       GTP_DFF_C      Q       dsp_join_kb_40[1]     0.290       15.226
sd_card_bmp_m0.sd_card_top_m0.spi_master_m0.MISO_shift[0]                                           sys_clk       GTP_DFF_CE     Q       spi_data_out[0]       0.290       15.257
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.wbin[2]     sys_clk       GTP_DFF_C      Q       dsp_join_kb_40[2]     0.290       15.260
=================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                                       Starting                                                         Required           
Instance                                                                                               Reference     Type           Pin     Net                         Time         Slack 
                                                                                                       Clock                                                                               
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[0]                                                  sys_clk       GTP_DFF_CE     CE      un1_CS_reg_1_sqmuxa_i_0     19.636       14.934
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[1]                                                  sys_clk       GTP_DFF_CE     CE      un1_CS_reg_1_sqmuxa_i_0     19.636       14.934
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[2]                                                  sys_clk       GTP_DFF_CE     CE      un1_CS_reg_1_sqmuxa_i_0     19.636       14.934
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[3]                                                  sys_clk       GTP_DFF_CE     CE      un1_CS_reg_1_sqmuxa_i_0     19.636       14.934
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[4]                                                  sys_clk       GTP_DFF_CE     CE      un1_CS_reg_1_sqmuxa_i_0     19.636       14.934
frame_read_write_m0.write_buf.U_ipml_fifo_afifo_32i_64o_256.U_ipml_fifo_ctrl.ASYN_CTRL\.asyn_wfull     sys_clk       GTP_DFF_C      D       asyn_wfull_2                20.020       15.157
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.byte_cnt[0]                                               sys_clk       GTP_DFF_CE     D       byte_cnt_lm[0]              20.023       15.340
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.byte_cnt[1]                                               sys_clk       GTP_DFF_CE     D       byte_cnt_lm[1]              20.023       15.340
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.byte_cnt[2]                                               sys_clk       GTP_DFF_CE     D       byte_cnt_lm[2]              20.023       15.340
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.byte_cnt[3]                                               sys_clk       GTP_DFF_CE     D       byte_cnt_lm[3]              20.023       15.340
===========================================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      20.000
    - Setup time:                            0.364
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         19.636

    - Propagation time:                      4.702
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     14.934

    Number of logic level(s):                6
    Starting point:                          sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[1] / Q
    Ending point:                            sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[0] / CE
    The start point is clocked by            sys_clk [rising] on pin CLK
    The end   point is clocked by            sys_clk [rising] on pin CLK

Instance / Net                                                                          Pin      Pin               Arrival     No. of    
Name                                                                     Type           Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[1]                    GTP_DFF_CE     Q        Out     0.290     0.290       -         
state[1]                                                                 Net            -        -       0.750     -           26        
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state134_1_0                GTP_LUT3       I1       In      -         1.040       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state134_1_0                GTP_LUT3       Z        Out     0.306     1.346       -         
state134_1_0                                                             Net            -        -       0.328     -           4         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.CS_reg_1_sqmuxa             GTP_LUT4       I1       In      -         1.674       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.CS_reg_1_sqmuxa             GTP_LUT4       Z        Out     0.306     1.980       -         
CS_reg_1_sqmuxa                                                          Net            -        -       0.289     -           2         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_0_0     GTP_LUT4       I0       In      -         2.269       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_0_0     GTP_LUT4       Z        Out     0.251     2.520       -         
un1_CS_reg_1_sqmuxa_0_0                                                  Net            -        -       0.269     -           1         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_3_0     GTP_LUT5       I2       In      -         2.788       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_3_0     GTP_LUT5       Z        Out     0.416     3.204       -         
un1_CS_reg_1_sqmuxa_3_0                                                  Net            -        -       0.269     -           1         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_1_1     GTP_LUT5       I1       In      -         3.473       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_1_1     GTP_LUT5       Z        Out     0.306     3.779       -         
un1_CS_reg_1_sqmuxa_1_1                                                  Net            -        -       0.269     -           1         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_i       GTP_LUT5       I1       In      -         4.048       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_i       GTP_LUT5       Z        Out     0.306     4.354       -         
un1_CS_reg_1_sqmuxa_i_0                                                  Net            -        -       0.348     -           5         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[0]                    GTP_DFF_CE     CE       In      -         4.702       -         
=========================================================================================================================================
Total path delay (propagation time + setup) of 5.066 is 2.545(50.2%) logic and 2.521(49.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      20.000
    - Setup time:                            0.364
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         19.636

    - Propagation time:                      4.702
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     14.934

    Number of logic level(s):                6
    Starting point:                          sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[1] / Q
    Ending point:                            sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[1] / CE
    The start point is clocked by            sys_clk [rising] on pin CLK
    The end   point is clocked by            sys_clk [rising] on pin CLK

Instance / Net                                                                          Pin      Pin               Arrival     No. of    
Name                                                                     Type           Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[1]                    GTP_DFF_CE     Q        Out     0.290     0.290       -         
state[1]                                                                 Net            -        -       0.750     -           26        
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state134_1_0                GTP_LUT3       I1       In      -         1.040       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state134_1_0                GTP_LUT3       Z        Out     0.306     1.346       -         
state134_1_0                                                             Net            -        -       0.328     -           4         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.CS_reg_1_sqmuxa             GTP_LUT4       I1       In      -         1.674       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.CS_reg_1_sqmuxa             GTP_LUT4       Z        Out     0.306     1.980       -         
CS_reg_1_sqmuxa                                                          Net            -        -       0.289     -           2         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_0_0     GTP_LUT4       I0       In      -         2.269       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_0_0     GTP_LUT4       Z        Out     0.251     2.520       -         
un1_CS_reg_1_sqmuxa_0_0                                                  Net            -        -       0.269     -           1         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_3_0     GTP_LUT5       I2       In      -         2.788       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_3_0     GTP_LUT5       Z        Out     0.416     3.204       -         
un1_CS_reg_1_sqmuxa_3_0                                                  Net            -        -       0.269     -           1         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_1_1     GTP_LUT5       I1       In      -         3.473       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_1_1     GTP_LUT5       Z        Out     0.306     3.779       -         
un1_CS_reg_1_sqmuxa_1_1                                                  Net            -        -       0.269     -           1         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_i       GTP_LUT5       I1       In      -         4.048       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_i       GTP_LUT5       Z        Out     0.306     4.354       -         
un1_CS_reg_1_sqmuxa_i_0                                                  Net            -        -       0.348     -           5         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[1]                    GTP_DFF_CE     CE       In      -         4.702       -         
=========================================================================================================================================
Total path delay (propagation time + setup) of 5.066 is 2.545(50.2%) logic and 2.521(49.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      20.000
    - Setup time:                            0.364
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         19.636

    - Propagation time:                      4.702
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     14.934

    Number of logic level(s):                6
    Starting point:                          sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[1] / Q
    Ending point:                            sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[2] / CE
    The start point is clocked by            sys_clk [rising] on pin CLK
    The end   point is clocked by            sys_clk [rising] on pin CLK

Instance / Net                                                                          Pin      Pin               Arrival     No. of    
Name                                                                     Type           Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[1]                    GTP_DFF_CE     Q        Out     0.290     0.290       -         
state[1]                                                                 Net            -        -       0.750     -           26        
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state134_1_0                GTP_LUT3       I1       In      -         1.040       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state134_1_0                GTP_LUT3       Z        Out     0.306     1.346       -         
state134_1_0                                                             Net            -        -       0.328     -           4         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.CS_reg_1_sqmuxa             GTP_LUT4       I1       In      -         1.674       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.CS_reg_1_sqmuxa             GTP_LUT4       Z        Out     0.306     1.980       -         
CS_reg_1_sqmuxa                                                          Net            -        -       0.289     -           2         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_0_0     GTP_LUT4       I0       In      -         2.269       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_0_0     GTP_LUT4       Z        Out     0.251     2.520       -         
un1_CS_reg_1_sqmuxa_0_0                                                  Net            -        -       0.269     -           1         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_3_0     GTP_LUT5       I2       In      -         2.788       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_3_0     GTP_LUT5       Z        Out     0.416     3.204       -         
un1_CS_reg_1_sqmuxa_3_0                                                  Net            -        -       0.269     -           1         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_1_1     GTP_LUT5       I1       In      -         3.473       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_1_1     GTP_LUT5       Z        Out     0.306     3.779       -         
un1_CS_reg_1_sqmuxa_1_1                                                  Net            -        -       0.269     -           1         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_i       GTP_LUT5       I1       In      -         4.048       -         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.un1_CS_reg_1_sqmuxa_i       GTP_LUT5       Z        Out     0.306     4.354       -         
un1_CS_reg_1_sqmuxa_i_0                                                  Net            -        -       0.348     -           5         
sd_card_bmp_m0.sd_card_top_m0.sd_card_cmd_m0.state[2]                    GTP_DFF_CE     CE       In      -         4.702       -         
=========================================================================================================================================
Total path delay (propagation time + setup) of 5.066 is 2.545(50.2%) logic and 2.521(49.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: video_pll|clkout0_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                 Starting                                                                       Arrival            
Instance                         Reference                            Type        Pin     Net                   Time        Slack  
                                 Clock                                                                                             
-----------------------------------------------------------------------------------------------------------------------------------
dvi_encoder_m0.encb.n0q_m[0]     video_pll|clkout0_inferred_clock     GTP_DFF     Q       dsp_join_kb_23[1]     0.290       994.419
dvi_encoder_m0.encb.n1q_m[1]     video_pll|clkout0_inferred_clock     GTP_DFF     Q       n1q_m[1]              0.290       994.514
dvi_encoder_m0.encg.n0q_m[0]     video_pll|clkout0_inferred_clock     GTP_DFF     Q       dsp_join_kb_37[1]     0.290       994.589
dvi_encoder_m0.encr.n0q_m[0]     video_pll|clkout0_inferred_clock     GTP_DFF     Q       dsp_join_kb_30[1]     0.290       994.589
dvi_encoder_m0.encg.n1q_m[1]     video_pll|clkout0_inferred_clock     GTP_DFF     Q       n1q_m[1]              0.290       994.684
dvi_encoder_m0.encr.n1q_m[1]     video_pll|clkout0_inferred_clock     GTP_DFF     Q       n1q_m[1]              0.290       994.684
dvi_encoder_m0.encb.n1q_m[3]     video_pll|clkout0_inferred_clock     GTP_DFF     Q       n1q_m[3]              0.290       994.715
dvi_encoder_m0.encb.n0q_m[2]     video_pll|clkout0_inferred_clock     GTP_DFF     Q       dsp_join_kb_23[3]     0.290       994.718
dvi_encoder_m0.encb.n1q_m[2]     video_pll|clkout0_inferred_clock     GTP_DFF     Q       n1q_m[2]              0.290       994.719
dvi_encoder_m0.encr.n0q_m[2]     video_pll|clkout0_inferred_clock     GTP_DFF     Q       dsp_join_kb_30[3]     0.290       994.812
===================================================================================================================================


Ending Points with Worst Slack
******************************

                               Starting                                                                      Required            
Instance                       Reference                            Type          Pin     Net                Time         Slack  
                               Clock                                                                                             
---------------------------------------------------------------------------------------------------------------------------------
dvi_encoder_m0.encb.cnt[4]     video_pll|clkout0_inferred_clock     GTP_DFF_C     D       un10_s_4_Z_1       1000.023     994.419
dvi_encoder_m0.encb.cnt[3]     video_pll|clkout0_inferred_clock     GTP_DFF_C     D       un10_cry_3_Z_1     1000.023     994.453
dvi_encoder_m0.encb.cnt[2]     video_pll|clkout0_inferred_clock     GTP_DFF_C     D       un10_cry_2_Z_1     1000.023     994.487
dvi_encoder_m0.encr.cnt[4]     video_pll|clkout0_inferred_clock     GTP_DFF_C     D       un10_s_4_Z_0       1000.023     994.589
dvi_encoder_m0.encg.cnt[4]     video_pll|clkout0_inferred_clock     GTP_DFF_C     D       un10_s_4_Z         1000.023     994.589
dvi_encoder_m0.encg.cnt[3]     video_pll|clkout0_inferred_clock     GTP_DFF_C     D       un10_cry_3_Z       1000.023     994.623
dvi_encoder_m0.encr.cnt[3]     video_pll|clkout0_inferred_clock     GTP_DFF_C     D       un10_cry_3_Z_0     1000.023     994.623
dvi_encoder_m0.encb.cnt[1]     video_pll|clkout0_inferred_clock     GTP_DFF_C     D       un10_cry_1_Z_1     1000.020     994.644
dvi_encoder_m0.encr.cnt[2]     video_pll|clkout0_inferred_clock     GTP_DFF_C     D       un10_cry_2_Z_0     1000.020     994.776
dvi_encoder_m0.encg.cnt[2]     video_pll|clkout0_inferred_clock     GTP_DFF_C     D       un10_cry_2_Z       1000.020     994.776
=================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      1000.000
    - Setup time:                            -0.023
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1000.023

    - Propagation time:                      5.604
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 994.419

    Number of logic level(s):                12
    Starting point:                          dvi_encoder_m0.encb.n0q_m[0] / Q
    Ending point:                            dvi_encoder_m0.encb.cnt[4] / D
    The start point is clocked by            video_pll|clkout0_inferred_clock [rising] on pin CLK
    The end   point is clocked by            video_pll|clkout0_inferred_clock [rising] on pin CLK

Instance / Net                                                  Pin      Pin               Arrival     No. of    
Name                                          Type              Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------
dvi_encoder_m0.encb.n0q_m[0]                  GTP_DFF           Q        Out     0.290     0.290       -         
dsp_join_kb_23[1]                             Net               -        -       0.368     -           6         
dvi_encoder_m0.encb.un4_decision3_ac0_3_0     GTP_LUT2          I0       In      -         0.658       -         
dvi_encoder_m0.encb.un4_decision3_ac0_3_0     GTP_LUT2          Z        Out     0.251     0.909       -         
un4_decision3_ac0_3_0                         Net               -        -       0.269     -           1         
dvi_encoder_m0.encb.un4_decision3_c4          GTP_LUT5          I4       In      -         1.178       -         
dvi_encoder_m0.encb.un4_decision3_c4          GTP_LUT5          Z        Out     0.176     1.354       -         
un4_decision3_c4_1                            Net               -        -       0.269     -           1         
dvi_encoder_m0.encb.un1_decision3[0]          GTP_LUT5          I3       In      -         1.623       -         
dvi_encoder_m0.encb.un1_decision3[0]          GTP_LUT5          Z        Out     0.420     2.042       -         
N_450                                         Net               -        -       0.328     -           4         
dvi_encoder_m0.encb.cnt_3_sqmuxa              GTP_LUT3          I0       In      -         2.371       -         
dvi_encoder_m0.encb.cnt_3_sqmuxa              GTP_LUT3          Z        Out     0.251     2.622       -         
cnt_3_sqmuxa                                  Net               -        -       0.448     -           10        
dvi_encoder_m0.encb.un10_4_axb_0_1            GTP_LUT3          I1       In      -         3.070       -         
dvi_encoder_m0.encb.un10_4_axb_0_1            GTP_LUT3          Z        Out     0.306     3.376       -         
un10_4_axb_0_1                                Net               -        -       0.269     -           1         
dvi_encoder_m0.encb.un10_4_axb_0              GTP_LUT4          I3       In      -         3.644       -         
dvi_encoder_m0.encb.un10_4_axb_0              GTP_LUT4          Z        Out     0.176     3.820       -         
un10_4_axb_0                                  Net               -        -       0.269     -           1         
dvi_encoder_m0.encb.un10_4_cry_0_0            GTP_LUT5CARRY     I3       In      -         4.089       -         
dvi_encoder_m0.encb.un10_4_cry_0_0            GTP_LUT5CARRY     COUT     Out     0.346     4.435       -         
un10_4_cry_0_0                                Net               -        -       0.000     -           1         
dvi_encoder_m0.encb.un10_4_cry_1              GTP_LUT5CARRY     CIN      In      -         4.435       -         
dvi_encoder_m0.encb.un10_4_cry_1              GTP_LUT5CARRY     Z        Out     0.232     4.667       -         
un10_4[1]                                     Net               -        -       0.289     -           2         
dvi_encoder_m0.encb.un10_cry_1                GTP_LUT5CARRY     I2       In      -         4.955       -         
dvi_encoder_m0.encb.un10_cry_1                GTP_LUT5CARRY     COUT     Out     0.348     5.303       -         
un10_cry_1                                    Net               -        -       0.000     -           1         
dvi_encoder_m0.encb.un10_cry_2                GTP_LUT5CARRY     CIN      In      -         5.303       -         
dvi_encoder_m0.encb.un10_cry_2                GTP_LUT5CARRY     COUT     Out     0.034     5.338       -         
un10_cry_2                                    Net               -        -       0.000     -           1         
dvi_encoder_m0.encb.un10_cry_3                GTP_LUT5CARRY     CIN      In      -         5.338       -         
dvi_encoder_m0.encb.un10_cry_3                GTP_LUT5CARRY     COUT     Out     0.034     5.372       -         
un10_cry_3                                    Net               -        -       0.000     -           1         
dvi_encoder_m0.encb.un10_s_4                  GTP_LUT5CARRY     CIN      In      -         5.372       -         
dvi_encoder_m0.encb.un10_s_4                  GTP_LUT5CARRY     Z        Out     0.232     5.604       -         
un10_s_4_Z_1                                  Net               -        -       0.000     -           1         
dvi_encoder_m0.encb.cnt[4]                    GTP_DFF_C         D        In      -         5.604       -         
=================================================================================================================
Total path delay (propagation time + setup) of 5.580 is 3.073(55.1%) logic and 2.508(44.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      1000.000
    - Setup time:                            -0.023
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1000.023

    - Propagation time:                      5.601
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 994.422

    Number of logic level(s):                12
    Starting point:                          dvi_encoder_m0.encb.n0q_m[0] / Q
    Ending point:                            dvi_encoder_m0.encb.cnt[4] / D
    The start point is clocked by            video_pll|clkout0_inferred_clock [rising] on pin CLK
    The end   point is clocked by            video_pll|clkout0_inferred_clock [rising] on pin CLK

Instance / Net                                                  Pin      Pin               Arrival     No. of    
Name                                          Type              Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------
dvi_encoder_m0.encb.n0q_m[0]                  GTP_DFF           Q        Out     0.290     0.290       -         
dsp_join_kb_23[1]                             Net               -        -       0.368     -           6         
dvi_encoder_m0.encb.un4_decision3_ac0_3_0     GTP_LUT2          I0       In      -         0.658       -         
dvi_encoder_m0.encb.un4_decision3_ac0_3_0     GTP_LUT2          Z        Out     0.251     0.909       -         
un4_decision3_ac0_3_0                         Net               -        -       0.269     -           1         
dvi_encoder_m0.encb.un4_decision3_c4          GTP_LUT5          I4       In      -         1.178       -         
dvi_encoder_m0.encb.un4_decision3_c4          GTP_LUT5          Z        Out     0.176     1.354       -         
un4_decision3_c4_1                            Net               -        -       0.269     -           1         
dvi_encoder_m0.encb.un1_decision3[0]          GTP_LUT5          I3       In      -         1.623       -         
dvi_encoder_m0.encb.un1_decision3[0]          GTP_LUT5          Z        Out     0.420     2.042       -         
N_450                                         Net               -        -       0.328     -           4         
dvi_encoder_m0.encb.cnt_3_sqmuxa              GTP_LUT3          I0       In      -         2.371       -         
dvi_encoder_m0.encb.cnt_3_sqmuxa              GTP_LUT3          Z        Out     0.251     2.622       -         
cnt_3_sqmuxa                                  Net               -        -       0.448     -           10        
dvi_encoder_m0.encb.un10_4_axb_0_1            GTP_LUT3          I1       In      -         3.070       -         
dvi_encoder_m0.encb.un10_4_axb_0_1            GTP_LUT3          Z        Out     0.306     3.376       -         
un10_4_axb_0_1                                Net               -        -       0.269     -           1         
dvi_encoder_m0.encb.un10_4_axb_0              GTP_LUT4          I3       In      -         3.644       -         
dvi_encoder_m0.encb.un10_4_axb_0              GTP_LUT4          Z        Out     0.176     3.820       -         
un10_4_axb_0                                  Net               -        -       0.269     -           1         
dvi_encoder_m0.encb.un10_4_cry_0_0            GTP_LUT5CARRY     I3       In      -         4.089       -         
dvi_encoder_m0.encb.un10_4_cry_0_0            GTP_LUT5CARRY     COUT     Out     0.346     4.435       -         
un10_4_cry_0_0                                Net               -        -       0.000     -           1         
dvi_encoder_m0.encb.un10_4_cry_1              GTP_LUT5CARRY     CIN      In      -         4.435       -         
dvi_encoder_m0.encb.un10_4_cry_1              GTP_LUT5CARRY     Z        Out     0.232     4.667       -         
un10_4[1]                                     Net               -        -       0.289     -           2         
dvi_encoder_m0.encb.un10_cry_1                GTP_LUT5CARRY     I3       In      -         4.955       -         
dvi_encoder_m0.encb.un10_cry_1                GTP_LUT5CARRY     COUT     Out     0.346     5.301       -         
un10_cry_1                                    Net               -        -       0.000     -           1         
dvi_encoder_m0.encb.un10_cry_2                GTP_LUT5CARRY     CIN      In      -         5.301       -         
dvi_encoder_m0.encb.un10_cry_2                GTP_LUT5CARRY     COUT     Out     0.034     5.335       -         
un10_cry_2                                    Net               -        -       0.000     -           1         
dvi_encoder_m0.encb.un10_cry_3                GTP_LUT5CARRY     CIN      In      -         5.335       -         
dvi_encoder_m0.encb.un10_cry_3                GTP_LUT5CARRY     COUT     Out     0.034     5.369       -         
un10_cry_3                                    Net               -        -       0.000     -           1         
dvi_encoder_m0.encb.un10_s_4                  GTP_LUT5CARRY     CIN      In      -         5.369       -         
dvi_encoder_m0.encb.un10_s_4                  GTP_LUT5CARRY     Z        Out     0.232     5.601       -         
un10_s_4_Z_1                                  Net               -        -       0.000     -           1         
dvi_encoder_m0.encb.cnt[4]                    GTP_DFF_C         D        In      -         5.601       -         
=================================================================================================================
Total path delay (propagation time + setup) of 5.578 is 3.071(55.0%) logic and 2.508(45.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      1000.000
    - Setup time:                            -0.023
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1000.023

    - Propagation time:                      5.569
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 994.454

    Number of logic level(s):                11
    Starting point:                          dvi_encoder_m0.encb.n0q_m[0] / Q
    Ending point:                            dvi_encoder_m0.encb.cnt[3] / D
    The start point is clocked by            video_pll|clkout0_inferred_clock [rising] on pin CLK
    The end   point is clocked by            video_pll|clkout0_inferred_clock [rising] on pin CLK

Instance / Net                                                  Pin      Pin               Arrival     No. of    
Name                                          Type              Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------
dvi_encoder_m0.encb.n0q_m[0]                  GTP_DFF           Q        Out     0.290     0.290       -         
dsp_join_kb_23[1]                             Net               -        -       0.368     -           6         
dvi_encoder_m0.encb.un4_decision3_ac0_3_0     GTP_LUT2          I0       In      -         0.658       -         
dvi_encoder_m0.encb.un4_decision3_ac0_3_0     GTP_LUT2          Z        Out     0.251     0.909       -         
un4_decision3_ac0_3_0                         Net               -        -       0.269     -           1         
dvi_encoder_m0.encb.un4_decision3_c4          GTP_LUT5          I4       In      -         1.178       -         
dvi_encoder_m0.encb.un4_decision3_c4          GTP_LUT5          Z        Out     0.176     1.354       -         
un4_decision3_c4_1                            Net               -        -       0.269     -           1         
dvi_encoder_m0.encb.un1_decision3[0]          GTP_LUT5          I3       In      -         1.623       -         
dvi_encoder_m0.encb.un1_decision3[0]          GTP_LUT5          Z        Out     0.420     2.042       -         
N_450                                         Net               -        -       0.328     -           4         
dvi_encoder_m0.encb.cnt_3_sqmuxa              GTP_LUT3          I0       In      -         2.371       -         
dvi_encoder_m0.encb.cnt_3_sqmuxa              GTP_LUT3          Z        Out     0.251     2.622       -         
cnt_3_sqmuxa                                  Net               -        -       0.448     -           10        
dvi_encoder_m0.encb.un10_4_axb_0_1            GTP_LUT3          I1       In      -         3.070       -         
dvi_encoder_m0.encb.un10_4_axb_0_1            GTP_LUT3          Z        Out     0.306     3.376       -         
un10_4_axb_0_1                                Net               -        -       0.269     -           1         
dvi_encoder_m0.encb.un10_4_axb_0              GTP_LUT4          I3       In      -         3.644       -         
dvi_encoder_m0.encb.un10_4_axb_0              GTP_LUT4          Z        Out     0.176     3.820       -         
un10_4_axb_0                                  Net               -        -       0.269     -           1         
dvi_encoder_m0.encb.un10_4_cry_0_0            GTP_LUT5CARRY     I3       In      -         4.089       -         
dvi_encoder_m0.encb.un10_4_cry_0_0            GTP_LUT5CARRY     COUT     Out     0.346     4.435       -         
un10_4_cry_0_0                                Net               -        -       0.000     -           1         
dvi_encoder_m0.encb.un10_4_cry_1              GTP_LUT5CARRY     CIN      In      -         4.435       -         
dvi_encoder_m0.encb.un10_4_cry_1              GTP_LUT5CARRY     Z        Out     0.232     4.667       -         
un10_4[1]                                     Net               -        -       0.289     -           2         
dvi_encoder_m0.encb.un10_cry_1                GTP_LUT5CARRY     I2       In      -         4.955       -         
dvi_encoder_m0.encb.un10_cry_1                GTP_LUT5CARRY     COUT     Out     0.348     5.303       -         
un10_cry_1                                    Net               -        -       0.000     -           1         
dvi_encoder_m0.encb.un10_cry_2                GTP_LUT5CARRY     CIN      In      -         5.303       -         
dvi_encoder_m0.encb.un10_cry_2                GTP_LUT5CARRY     COUT     Out     0.034     5.338       -         
un10_cry_2                                    Net               -        -       0.000     -           1         
dvi_encoder_m0.encb.un10_cry_3                GTP_LUT5CARRY     CIN      In      -         5.338       -         
dvi_encoder_m0.encb.un10_cry_3                GTP_LUT5CARRY     Z        Out     0.232     5.569       -         
un10_cry_3_Z_1                                Net               -        -       0.000     -           1         
dvi_encoder_m0.encb.cnt[3]                    GTP_DFF_C         D        In      -         5.569       -         
=================================================================================================================
Total path delay (propagation time + setup) of 5.546 is 3.039(54.8%) logic and 2.508(45.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: video_pll|clkout1_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                       Starting                                                                        Arrival            
Instance                                               Reference                            Type          Pin     Net                  Time        Slack  
                                                       Clock                                                                                              
----------------------------------------------------------------------------------------------------------------------------------------------------------
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[2]         video_pll|clkout1_inferred_clock     GTP_DFF_R     Q       TMDS_mod5[2]         0.290       998.638
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_0h[0]     video_pll|clkout1_inferred_clock     GTP_DFF       Q       TMDS_shift_0h[0]     0.290       999.030
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_0l[0]     video_pll|clkout1_inferred_clock     GTP_DFF       Q       TMDS_shift_0l[0]     0.290       999.030
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_1h[0]     video_pll|clkout1_inferred_clock     GTP_DFF       Q       TMDS_shift_1h[0]     0.290       999.030
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_1l[0]     video_pll|clkout1_inferred_clock     GTP_DFF       Q       TMDS_shift_1l[0]     0.290       999.030
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_2h[0]     video_pll|clkout1_inferred_clock     GTP_DFF_R     Q       TMDS_shift_2h[0]     0.290       999.030
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_2l[0]     video_pll|clkout1_inferred_clock     GTP_DFF_R     Q       TMDS_shift_2l[0]     0.290       999.030
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_3h[0]     video_pll|clkout1_inferred_clock     GTP_DFF_R     Q       TMDS_shift_3h[0]     0.290       999.030
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_3l[0]     video_pll|clkout1_inferred_clock     GTP_DFF_R     Q       TMDS_shift_3l[0]     0.290       999.030
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[0]         video_pll|clkout1_inferred_clock     GTP_DFF_R     Q       CO0                  0.290       999.038
==========================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                       Starting                                                                     Required            
Instance                                               Reference                            Type           Pin     Net              Time         Slack  
                                                       Clock                                                                                            
--------------------------------------------------------------------------------------------------------------------------------------------------------
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[0]         video_pll|clkout1_inferred_clock     GTP_DFF_R      R       TMDS_mod5[2]     999.693      998.638
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[1]         video_pll|clkout1_inferred_clock     GTP_DFF_RE     R       TMDS_mod5[2]     999.693      998.638
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[2]         video_pll|clkout1_inferred_clock     GTP_DFF_R      R       TMDS_mod5[2]     999.693      998.638
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_2h[0]     video_pll|clkout1_inferred_clock     GTP_DFF_R      R       TMDS_mod5[2]     999.693      998.638
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_2l[0]     video_pll|clkout1_inferred_clock     GTP_DFF_R      R       TMDS_mod5[2]     999.693      998.638
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_3h[0]     video_pll|clkout1_inferred_clock     GTP_DFF_R      R       TMDS_mod5[2]     999.693      998.638
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_3h[1]     video_pll|clkout1_inferred_clock     GTP_DFF_R      R       TMDS_mod5[2]     999.693      998.638
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_3h[2]     video_pll|clkout1_inferred_clock     GTP_DFF_R      R       TMDS_mod5[2]     999.693      998.638
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_3l[0]     video_pll|clkout1_inferred_clock     GTP_DFF_R      R       TMDS_mod5[2]     999.693      998.638
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_3l[1]     video_pll|clkout1_inferred_clock     GTP_DFF_R      R       TMDS_mod5[2]     999.693      998.638
========================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      1000.000
    - Setup time:                            0.307
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         999.693

    - Propagation time:                      1.055
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 998.638

    Number of logic level(s):                0
    Starting point:                          dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[2] / Q
    Ending point:                            dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[0] / R
    The start point is clocked by            video_pll|clkout1_inferred_clock [rising] on pin CLK
    The end   point is clocked by            video_pll|clkout1_inferred_clock [rising] on pin CLK

Instance / Net                                                   Pin      Pin               Arrival     No. of    
Name                                               Type          Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[2]     GTP_DFF_R     Q        Out     0.290     0.290       -         
TMDS_mod5[2]                                       Net           -        -       0.765     -           41        
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[0]     GTP_DFF_R     R        In      -         1.055       -         
==================================================================================================================
Total path delay (propagation time + setup) of 1.362 is 0.597(43.8%) logic and 0.765(56.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      1000.000
    - Setup time:                            0.307
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         999.693

    - Propagation time:                      1.055
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 998.638

    Number of logic level(s):                0
    Starting point:                          dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[2] / Q
    Ending point:                            dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[1] / R
    The start point is clocked by            video_pll|clkout1_inferred_clock [rising] on pin CLK
    The end   point is clocked by            video_pll|clkout1_inferred_clock [rising] on pin CLK

Instance / Net                                                    Pin      Pin               Arrival     No. of    
Name                                               Type           Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[2]     GTP_DFF_R      Q        Out     0.290     0.290       -         
TMDS_mod5[2]                                       Net            -        -       0.765     -           41        
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[1]     GTP_DFF_RE     R        In      -         1.055       -         
===================================================================================================================
Total path delay (propagation time + setup) of 1.362 is 0.597(43.8%) logic and 0.765(56.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      1000.000
    - Setup time:                            0.307
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         999.693

    - Propagation time:                      1.055
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 998.638

    Number of logic level(s):                0
    Starting point:                          dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[2] / Q
    Ending point:                            dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_3h[2] / R
    The start point is clocked by            video_pll|clkout1_inferred_clock [rising] on pin CLK
    The end   point is clocked by            video_pll|clkout1_inferred_clock [rising] on pin CLK

Instance / Net                                                       Pin      Pin               Arrival     No. of    
Name                                                   Type          Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_mod5[2]         GTP_DFF_R     Q        Out     0.290     0.290       -         
TMDS_mod5[2]                                           Net           -        -       0.765     -           41        
dvi_encoder_m0.serdes_4b_10to1_m0.TMDS_shift_3h[2]     GTP_DFF_R     R        In      -         1.055       -         
======================================================================================================================
Total path delay (propagation time + setup) of 1.362 is 0.597(43.8%) logic and 0.765(56.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                                         Starting                                                            Arrival            
Instance                                                 Reference     Type           Pin               Net                  Time        Slack  
                                                         Clock                                                                                  
------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1                   System        GTP_PLL_E1     CLKOUT0           pll_phy_clk          0.000       998.719
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy     System        GTP_DLL        DELAY_STEP[0]     dll_step_copy[0]     0.000       999.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy     System        GTP_DLL        DELAY_STEP[1]     dll_step_copy[1]     0.000       999.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy     System        GTP_DLL        DELAY_STEP[2]     dll_step_copy[2]     0.000       999.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy     System        GTP_DLL        DELAY_STEP[3]     dll_step_copy[3]     0.000       999.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy     System        GTP_DLL        DELAY_STEP[4]     dll_step_copy[4]     0.000       999.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy     System        GTP_DLL        DELAY_STEP[5]     dll_step_copy[5]     0.000       999.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy     System        GTP_DLL        DELAY_STEP[6]     dll_step_copy[6]     0.000       999.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy     System        GTP_DLL        DELAY_STEP[7]     dll_step_copy[7]     0.000       999.731
u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1                   System        GTP_PLL_E1     LOCK              pll_lock_c           0.000       999.731
================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                   Starting                                                   Required            
Instance                                                                           Reference     Type          Pin       Net                  Time         Slack  
                                                                                   Clock                                                                          
------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dll_hmemc_dut                  System        GTP_DLL       CLKIN     ioclk_01_i           1000.000     998.719
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy                               System        GTP_DLL       CLKIN     pll_phy_clk          1000.000     999.692
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[0]     System        GTP_DFF_C     D         dll_step_copy[0]     1000.020     999.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[1]     System        GTP_DFF_C     D         dll_step_copy[1]     1000.020     999.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[2]     System        GTP_DFF_C     D         dll_step_copy[2]     1000.020     999.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[3]     System        GTP_DFF_C     D         dll_step_copy[3]     1000.020     999.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[4]     System        GTP_DFF_C     D         dll_step_copy[4]     1000.020     999.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[5]     System        GTP_DFF_C     D         dll_step_copy[5]     1000.020     999.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[6]     System        GTP_DFF_C     D         dll_step_copy[6]     1000.020     999.731
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[7]     System        GTP_DFF_C     D         dll_step_copy[7]     1000.020     999.731
==================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      1000.000
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         1000.000

    - Propagation time:                      1.281
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 998.719

    Number of logic level(s):                1
    Starting point:                          u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1 / CLKOUT0
    Ending point:                            u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dll_hmemc_dut / CLKIN
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                                                          Pin         Pin               Arrival     No. of    
Name                                                                   Type             Name        Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1                                 GTP_PLL_E1       CLKOUT0     Out     0.000     0.000       -         
pll_phy_clk                                                            Net              -           -       0.308     -           3         
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclkbuf01_dut     GTP_IOCLKBUF     CLKIN       In      -         0.308       -         
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.ioclkbuf01_dut     GTP_IOCLKBUF     CLKOUT      Out     0.306     0.615       -         
ioclk_01_i                                                             Net              -           -       0.667     -           21        
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ipsl_phy_io.dll_hmemc_dut      GTP_DLL          CLKIN       In      -         1.281       -         
============================================================================================================================================
Total path delay (propagation time + setup) of 1.281 is 0.306(23.9%) logic and 0.975(76.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      1000.000
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         1000.000

    - Propagation time:                      0.308
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 999.692

    Number of logic level(s):                0
    Starting point:                          u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1 / CLKOUT0
    Ending point:                            u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy / CLKIN
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                                          Pin         Pin               Arrival     No. of    
Name                                                     Type           Name        Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_pll_50_400.u_pll_e1                   GTP_PLL_E1     CLKOUT0     Out     0.000     0.000       -         
pll_phy_clk                                              Net            -           -       0.308     -           3         
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy     GTP_DLL        CLKIN       In      -         0.308       -         
============================================================================================================================
Total path delay (propagation time + setup) of 0.308 is 0.000(0.0%) logic and 0.308(100.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      1000.000
    - Setup time:                            -0.020
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1000.020

    - Propagation time:                      0.289
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 999.731

    Number of logic level(s):                0
    Starting point:                          u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy / DELAY_STEP[0]
    Ending point:                            u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[0] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            pll_50_400|clkout1_inferred_clock [rising] on pin CLK

Instance / Net                                                                                   Pin               Pin               Arrival     No. of    
Name                                                                               Type          Name              Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------------------------
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.I_GTP_DLL_copy                               GTP_DLL       DELAY_STEP[0]     Out     0.000     0.000       -         
dll_step_copy[0]                                                                   Net           -                 -       0.289     -           2         
u_ipsl_hmemc_top.u_ipsl_hmemc_phy_top.u_ddrphy_update_ctrl.dll_step_copy_d1[0]     GTP_DFF_C     D                 In      -         0.289       -         
===========================================================================================================================================================
Total path delay (propagation time + setup) of 0.269 is -0.020(-7.4%) logic and 0.289(107.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied

Finished final timing analysis (Real Time elapsed 0h:00m:44s; CPU Time elapsed 0h:00m:34s; Memory used current: 420MB peak: 460MB)


Finished timing report (Real Time elapsed 0h:00m:44s; CPU Time elapsed 0h:00m:34s; Memory used current: 420MB peak: 460MB)

---------------------------------------
Resource Usage Report for ipsl_hmemc_top_test 

Mapping to part: pgl22gbg324-7
Cell usage:
GTP_DDC_E1      5 uses
GTP_DDRC        1 use
GTP_DDRPHY      1 use
GTP_DFF         122 uses
GTP_DFF_C       482 uses
GTP_DFF_CE      491 uses
GTP_DFF_E       19 uses
GTP_DFF_P       20 uses
GTP_DFF_PE      19 uses
GTP_DFF_R       9 uses
GTP_DFF_RE      1 use
GTP_DFF_S       1 use
GTP_DLL         2 uses
GTP_DRM18K      4 uses
GTP_GRS         1 use
GTP_INV         69 uses
GTP_IOCLKBUF    2 uses
GTP_IOCLKDIV    1 use
GTP_IODELAY     16 uses
GTP_ISERDES     16 uses
GTP_LUT2        432 uses
GTP_LUT3        356 uses
GTP_LUT4        237 uses
GTP_LUT5        336 uses
GTP_LUT5CARRY   658 uses
GTP_OSERDES     54 uses
GTP_PLL_E1      2 uses
GTP_ROM64X1     30 uses

I/O ports: 78
GTP_INBUF      4 uses
GTP_INBUFG     2 uses
GTP_IOBUF      16 uses
GTP_IOBUFCO    2 uses
GTP_OUTBUF     13 uses
GTP_OUTBUFT    37 uses
GTP_OUTBUFTCO  1 use


RAM/ROM usage summary

Distributed Rams : 30.00 of 1110 (2.70%)


Mapping Summary:
Total LUTs: 2079 of 17536 (11.86%)
	LUTs as dram: 0 of 4440 (0.00%)
	LUTs as logic: 2079 
Total Registers: 1164 of 26304 (4.43%)

DRM18K:
Total DRM18K =  4 of 48 (8.33%)

APMs:
Total APMs =  0.00 of 30 (0.00%)

Total I/O primitives =  75 of 240 (31.25%)


 Number of unique control sets:              71
 CLK(clkout3_i), C(rst_n_c_i_0), P(GND), CE(VCC)		: 125
 CLK(clkout3_i), C(GND), P(GND), CE(VCC)		: 1
 CLK(clkout3_i), C(GND), P(rst_n_c_i_0), CE(VCC)		: 4
 CLK(clkout3_i), C(rst_n_c_i_0), P(GND), CE(N_490_i_0)		: 2
 CLK(clkout3_i), C(rst_n_c_i_0), P(GND), CE(rd_state_0_sqmuxa)		: 2
 CLK(clkout3_i), C(rst_n_c_i_0), P(GND), CE(un1_M_AXI_AWLOCK_15_0)		: 21
 CLK(clkout3_i), C(rst_n_c_i_0), P(GND), CE(reg_rd_lence[0])		: 2
 CLK(clkout3_i), C(rst_n_c_i_0), P(GND), CE(un1_MASTER_RST_2_0_0)		: 21
 CLK(clkout3_i), C(rst_n_c_i_0), P(GND), CE(reg_wr_lence[0])		: 2
 CLK(clkout3_i), C(rst_n_c_i_0), P(GND), CE(reg_w_lene)		: 8
 CLK(clkout3_i), C(rst_n_c_i_0), P(GND), CE(reg_r_lene)		: 8
 CLK(clkout3_i), C(rst_n_c_i_0), P(GND), CE(rd_fifo_cnte)		: 32
 CLK(clkout1_i), C(global_reset_i_0), P(GND), CE(dll_step_copy_synced4_NE_i_0)		: 8
 CLK(clkout1_i), C(GND), P(global_reset_i_0), CE(VCC)		: 5
 CLK(clkout1_i), C(global_reset_i_0), P(GND), CE(VCC)		: 41
 CLK(dll_update_n_i), C(global_reset_i_0), P(GND), CE(VCC)		: 8
 CLK(clkout1_i), C(GND), P(GND), CE(VCC)		: 34
 CLK(clkout1_i), C(GND), P(global_reset_i_0), CE(N_82_i_0)		: 1
 CLK(clkout1_i), C(global_reset_i_0), P(GND), CE(N_82_i_0)		: 1
 CLK(clkout1_i), C(rst_n_c_i_0), P(GND), CE(VCC)		: 17
 CLK(clkout1_i), C(GND), P(rst_n_c_i_0), CE(VCC)		: 1
 CLK(clkout1_i), C(rst_n_c_i_0), P(GND), CE(N_6_i_0)		: 8
 CLK(clkout1_i), C(presetn_i_0), P(GND), CE(VCC)		: 3
 CLK(clkout1_i), C(presetn_i_0), P(GND), CE(cnte)		: 7
 CLK(clkout1_i), C(resetn_i_0), P(GND), CE(un1_init_preset8_0_a2)		: 1
 CLK(clkout1_i), C(GND), P(resetn_i_0), CE(un1_init_preset8_0_a2)		: 1
 CLK(clkout1_i), C(GND), P(resetn_i_0), CE(VCC)		: 1
 CLK(clkout1_i), C(GND), P(resetn_i_0), CE(ddrc_init_done)		: 1
 CLK(clkout1_i), C(resetn_i_0), P(GND), CE(ddrc_init_done)		: 1
 CLK(clkout1_i), C(resetn_i_0), P(GND), CE(ddrc_rst_cnte)		: 5
 CLK(clkout1_i), C(resetn_i_0), P(GND), CE(rst_cnt7)		: 5
 CLK(clkout3_i), C(rst_n_c_i_0), P(GND), CE(read_cnte)		: 19
 CLK(clkout0_i), C(read_fifo_aclr), P(GND), CE(VCC)		: 36
 CLK(clkout3_i), C(read_fifo_aclr), P(GND), CE(VCC)		: 39
 CLK(clkout0_i), C(GND), P(read_fifo_aclr), CE(VCC)		: 1
 CLK(clkout3_i), C(rst_n_c_i_0), P(GND), CE(write_cnte)		: 19
 CLK(clkout3_i), C(write_fifo_aclr), P(GND), CE(VCC)		: 38
 CLK(sys_clk_c[0]), C(write_fifo_aclr), P(GND), CE(VCC)		: 37
 CLK(clkout3_i), C(GND), P(write_fifo_aclr), CE(VCC)		: 1
 CLK(clkout0_i), C(rst_n_c_i_0), P(GND), CE(VCC)		: 87
 CLK(clkout0_i), C(rst_n_c_i_0), P(GND), CE(hs_reg5)		: 12
 CLK(clkout0_i), C(GND), P(GND), CE(rst_n_c)		: 3
 CLK(clkout1_i), R(TMDS_mod5[2]), S(GND), CE(CO0)		: 1
 CLK(clkout1_i), R(TMDS_mod5[2]), S(GND), CE(VCC)		: 9
 CLK(clkout0_i), C(GND), P(GND), CE(VCC)		: 88
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(N_54_i_0)		: 8
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(N_52_i_0)		: 8
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(clk_edge_cnte)		: 6
 CLK(sys_clk_c[0]), C(GND), P(rst_n_c_i_0), CE(VCC)		: 7
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(VCC)		: 51
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(un1_CS_reg_1_sqmuxa_i_0)		: 5
 CLK(sys_clk_c[0]), C(GND), P(rst_n_c_i_0), CE(N_95_i_0)		: 8
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(block_read_data5)		: 8
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(byte_cnte)		: 16
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(state_i_0[4])		: 10
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(N_165_i_0)		: 43
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(state_ns_a3_0[5])		: 32
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(bmp_datace[0])		: 8
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(bmp_datace[8])		: 8
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(bmp_datace[16])		: 8
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(sd_init_done)		: 2
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(N_342_0)		: 32
 CLK(sys_clk_c[0]), C(GND), P(GND), CE(width_0_sqmuxa)		: 16
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(header_1_0_sqmuxa)		: 8
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(header_0_0_sqmuxa)		: 8
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(N_344_i_0)		: 23
 CLK(sys_clk_c[0]), C(GND), P(rst_n_c_i_0), CE(N_344_i_0)		: 6
 CLK(sys_clk_c[0]), C(GND), P(rst_n_c_i_0), CE(un1_state43_1_0_a2)		: 2
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(bmp_len_cnte)		: 32
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(rd_cnte)		: 10
 CLK(sys_clk_c[0]), C(rst_n_c_i_0), P(GND), CE(q_rege)		: 32

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:44s; CPU Time elapsed 0h:00m:34s; Memory used current: 239MB peak: 460MB)

Process took 0h:00m:44s realtime, 0h:00m:34s cputime
# Tue May  7 16:41:38 2019

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